JPS5912651A - ビタ−ビ復号器の同期回路 - Google Patents

ビタ−ビ復号器の同期回路

Info

Publication number
JPS5912651A
JPS5912651A JP57120945A JP12094582A JPS5912651A JP S5912651 A JPS5912651 A JP S5912651A JP 57120945 A JP57120945 A JP 57120945A JP 12094582 A JP12094582 A JP 12094582A JP S5912651 A JPS5912651 A JP S5912651A
Authority
JP
Japan
Prior art keywords
phase
signal
metric
output
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57120945A
Other languages
English (en)
Japanese (ja)
Other versions
JPH038141B2 (enrdf_load_stackoverflow
Inventor
Yutaka Yasuda
豊 安田
Yasuo Hirata
康夫 平田
Yukitsuna Furuya
之綱 古谷
Shuji Murakami
修司 村上
Katsuhiro Nakamura
勝洋 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK, NEC Corp, Nippon Electric Co Ltd filed Critical Kokusai Denshin Denwa KK
Priority to JP57120945A priority Critical patent/JPS5912651A/ja
Publication of JPS5912651A publication Critical patent/JPS5912651A/ja
Publication of JPH038141B2 publication Critical patent/JPH038141B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045Arrangements at the receiver end
    • H04L1/0054Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Landscapes

  • Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP57120945A 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路 Granted JPS5912651A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57120945A JPS5912651A (ja) 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57120945A JPS5912651A (ja) 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路

Publications (2)

Publication Number Publication Date
JPS5912651A true JPS5912651A (ja) 1984-01-23
JPH038141B2 JPH038141B2 (enrdf_load_stackoverflow) 1991-02-05

Family

ID=14798854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57120945A Granted JPS5912651A (ja) 1982-07-12 1982-07-12 ビタ−ビ復号器の同期回路

Country Status (1)

Country Link
JP (1) JPS5912651A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH038141B2 (enrdf_load_stackoverflow) 1991-02-05

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