JPS59125630A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS59125630A
JPS59125630A JP58000807A JP80783A JPS59125630A JP S59125630 A JPS59125630 A JP S59125630A JP 58000807 A JP58000807 A JP 58000807A JP 80783 A JP80783 A JP 80783A JP S59125630 A JPS59125630 A JP S59125630A
Authority
JP
Japan
Prior art keywords
film
glass
films
metallic film
passivation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58000807A
Other languages
Japanese (ja)
Inventor
Tatsuro Okazaki
岡崎 達郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP58000807A priority Critical patent/JPS59125630A/en
Publication of JPS59125630A publication Critical patent/JPS59125630A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Abstract

PURPOSE:To reduce the cracks and exfoliation of passivation films by coating the surface of a semiconductor substrate on the side where there is little passivation film with a first electrode metallic film, coating the surface of the semiconductor substrate on another side with a second electrode metallic film thinner than the first electrode metallic film and removing the metallic films on the passivation films. CONSTITUTION:The insides of grooves 2 are coated with the glass passivation films 3, the first electrode metallic film 5 is evaporated on the surface on the cathode side, and the second electrode metallic film 4 thinner than said metallic film 5 is evaporated on the anode side, and the metallic films 4 on the glass films 3 are removed through photo-etching technique, etc. When the semiconductor element is manufactured by a process of such order, the generation of cracks in the glass films 3 is very few, and the glass films 3 are hardly exfoliated particularly. It is the most desirable that the thickness of the metallic film 5 on the cathode side is particularly made to be 0.7-1.0mum and the thickness of the metallic film 4 on the anode side 0.5-0.7mum.

Description

【発明の詳細な説明】 本発明は半導体基板の表裏面にガラスパシベーション膜
が非対称に覆われた半導体素子全製造する方法に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device in which the front and back surfaces of a semiconductor substrate are asymmetrically covered with glass passivation films.

半導体素子は、そのpn接合露出部の表面保護のために
シリコン酸化膜、リンガラス膜、窒化シリコン膜、ガラ
ス膜およびそれらの積み重ねによる多層膜で構成烙れた
パシベーション膜を設けることが行なわれている。
In order to protect the surface of the exposed pn junction of a semiconductor device, a passivation film consisting of a silicon oxide film, a phosphorus glass film, a silicon nitride film, a glass film, and a multilayer film formed by stacking these films is provided. There is.

この場合、特に半導体素子の高耐圧化や、より低価格化
のための樹脂封止金するには、熱膨張係数がシリコンに
近いガラスにより厚い膜にしたり、単独では厚くできな
いシリコン酸化膜、リンガラス膜、窒化シリコン膜等を
適切な組み合せにより積み重ねることが行なわれている
In this case, in order to increase the voltage resistance of semiconductor devices and to use resin encapsulation metals to lower prices, it is necessary to make a thick film using glass whose thermal expansion coefficient is close to that of silicon, or use a silicon oxide film or phosphor that cannot be thickened by itself. Glass films, silicon nitride films, etc. are stacked in appropriate combinations.

このようなパシベーション膜を多層にしたり、ガラス膜
の場合のように淳<シたりすると、これらのパシベーシ
ョン膜と半導体基板の熱膨張係数の差に基因する応力に
よって半導体基板のパシベーション膜側に曲率中心をも
つそりが一層大きくなることは容易に考えられる。
When such a passivation film is made into multiple layers, or when it is layered as in the case of a glass film, the center of curvature is created on the passivation film side of the semiconductor substrate due to stress caused by the difference in thermal expansion coefficient between these passivation films and the semiconductor substrate. It is easy to imagine that the sled with .

このような半導体基板のパシベーション膜は、これを被
着せしめた直後の段階には、熱画芋や物理的衝$を与え
ないかぎりパシベーション膜にクラックやはがれが生じ
ない程度の膜厚に制側jすることは、それほど難かしく
にない。
Immediately after the passivation film is deposited on such a semiconductor substrate, the film thickness must be controlled to a level that will not cause cracks or peeling unless the passivation film is exposed to heat or physical force. It's not that difficult to do.

しかし、このような半導体基板、1.’llち前述の工
うなそりの大きい基板はこの段階ではクランクなどがな
くても、埒らに、例えばフォトエッチングI+’Jなど
において、フォトレジスト膜を、P、布して、パクーン
合せのためにこの半導体基板とフォトマスク板を重ね合
せろ際にこの置板が押しつけられてそりのない水平な状
態にされろときにも、このバシベーンヨン!4¥にクラ
ックが入らない膜厚にしておかなけれ幻′ならない。
However, such a semiconductor substrate, 1. Even if there is no crank or the like at this stage, for the substrate with large warpage as described above, a photoresist film is applied to it by photo etching I+'J, etc., for pattern alignment. Even when this semiconductor substrate and photomask plate are stacked together, the mounting plate is pressed down to make it horizontal without warping. The thickness of the film must be such that no cracks appear in the film.

才だ、当然ながら前述の゛β導体基板に電極金属膜を蒸
11などにより被着せしめ、その金属膜を7オトエノテ
ング技術により所定のパターンに加工する必・皮があり
、そのためそりが埒らに大きくなったり、再度フォトマ
スクが押しつけられたりすルノテ、パシベーション膜は
薄くきれねばならない。従って、この工程捷でを浮めて
クラックやはがれが発生しなu) 、1:つな多層のパ
シベーション膜や、所望の1−“7さのガラス膜などに
しておくことは困難である。
Naturally, there is a need to deposit an electrode metal film on the aforementioned β conductor substrate by steaming, etc., and then process the metal film into a predetermined pattern using the 7-oto-enoting technique, which results in warpage. If the passivation film becomes larger or the photomask is pressed again, the passivation film must be cut thin. Therefore, it is difficult to create a 1:2 multilayer passivation film or a desired 1-7 glass film without causing cracks or peeling during this process.

特に半導体基板の直径が76m]ソ上で、しかも樹脂封
止による汚染の影、#を除き、特に600V以上の高耐
圧にさえも劣化しないような多層膜や厚いガラス膜にし
ておくことは困難である。
In particular, it is difficult to make a multilayer film or thick glass film that does not deteriorate even at high withstand voltages of 600 V or more, especially on a semiconductor substrate with a diameter of 76 m, excluding the contamination caused by resin sealing. It is.

魂だ、嘔らにこ負、らのム着などシてよって、鵠、1金
4金属膜を・ζシベーノヨン膜の上7>・r〕全面Cζ
、U一つ1、フォトエツチング技杯丁+−c、、t:す
、・2ンベ一シヨンII位上の金属膜を除フモすると、
・くゾペーション月負−にで。
It's my soul, and I'm so proud of myself, and I'm wearing 1 gold 4 metal membranes.
,U11,Photoetching technique +-c,,t:su,2 When the metal film on the board II is removed,
・Kuzopation monthly negative.

この金曜嘆に、J:る応力が1爵間的に開放さ−L]、
て、・(シベーンヨン膜にクラ、夕が入ることも=lE
 jシVこ多い。
On this Friday, the stress of J: is suddenly released -L],
(It's also possible for the evening to enter the film.)
There are a lot of jshiv.

例えは、第1図はガラス膜で・々シベーションを施した
ダイオード素子の断面ly、1ヲ示す。、 7(pシ1
ノコン基板1(では、その両面からの拡散にJ: +2
 、それぞハi層、nl一層が設けられてい・る。1)
)脅frillから1列え(寸10011mのprlj
妾合イ栗を北越える躍−2力;ユノf 7 りK 、J
:り形成埒れ、そのji112の(〕U ll1l i
’c、は厚す1.5/zmツガラス、l[93で+t2
わt]7、そオLJ’J、外の斗(而は電杼金X(’=
 n’) 4および5VCよって+1ジわ、てし)る。
For example, FIG. 1 shows a cross section of a diode element which has been subjected to sivation with a glass film. , 7(pshi1
Nocon board 1 (Then, for diffusion from both sides, J: +2
, a high i layer and a nl layer are provided, respectively. 1)
) 1 row from the threat frill (prlj of size 10011m
Concubine I Kuri Goes North - 2 Power; Yuno f 7 RiK, J
:ri formation, its ji112(]U ll1l i
'c, thickness 1.5/zm glass, l [+t2 at 93
wat] 7, Soo LJ'J, Tonoto (but Denshukin X ('=
n') +1 due to 4 and 5 VC.

電極金属としてはシリコンi+lllからモI)フ゛テ
ン(、Mo)−ニッケル(Ni)−金(Au)あるワ・
はクロム(Cr)−二、ケルー金などの多層A着+1.
’;sが用1./)られ、その全体の厚では05〜20
/J、m程度である。
The electrode metals range from silicon i + lll to moi) - nickel (Ni) - gold (Au).
is chromium (Cr)-2, multi-layer A-based such as Keru gold +1.
';s is used1. /) and its total thickness is 05-20
/J, m.

このようなダイオード素子を製造するときは、従来第2
図(a)に示すように、先ずン42の中を溶I独ガラス
膜3で被己し、次いで渦2図1b+に示すように、アノ
ード(ijlの電(返金属膜4r蒸着し、坏ら1(第2
区1(C)に示すように、ガラスlj〆3の上の金属膜
?フォトエツチング技術により除去・rる。しヤきシ、
ここ才でのニオ呈に一!I≧ると、tjlJ述のように
ガラス膜にクラックやはプ)−れが生じることが多かっ
た。
Conventionally, when manufacturing such diode elements, the second
As shown in Figure (a), the interior of the tube 42 is first covered with a molten glass film 3, and then, as shown in Figure 1b, the inside of the vortex 2 is coated with a molten glass film 3. et al. 1 (second
As shown in Section 1 (C), the metal film on the glass lj〆3? Removed and rubbed using photo-etching technology. Shayakishi,
One of the best at this age! When I≧, cracks and peeling often occur in the glass film as described in tjlJ.

このことは金に1漠によって、ノく・ンベーゾヨン膜だ
けのときに比べ1、づらに−そう半導体基板のそりが太
きくな、っているためと考えらnる。
This is thought to be due to the fact that the warp of the semiconductor substrate is considerably thicker than in the case of using only the oxide film.

本発明L1このような点に鑑みてなでれ/ζものであり
、半導体の炙裏面Vこ・(シベーション膜カー夛¥、対
称に1)°すわれだものにおいても、半導体基板のそり
f 少f、仁〈シて、パシベーション膜のクラノクペ−
r−1がれの発生の少tcい半導体素子の製造方法全提
供すること全目的とする。
The present invention L1 In view of these points, it is a smooth/ζ thing, and even in a good product, the warpage of the semiconductor substrate is avoided. f Small f, Jin
It is an object of the present invention to provide a method for manufacturing a semiconductor device with less occurrence of r-1 peeling.

前記281の電極金属膜より薄1./42の電極金属膜
を被着し、最後に前記ノくシベーシ7ン膜」二の金属膜
を除去することにより達成をれる。
1. Thinner than the electrode metal film of 281 above. This can be achieved by depositing an electrode metal film of /42 and finally removing the second metal film of the base layer.

以下、本発明の一実施(+Q全全図用し)て説明する。Hereinafter, one implementation of the present invention (using all +Q diagrams) will be explained.

第3図(al乃至(dlは本発明の一実施例を工程11
直に示しており、第2図と同様に第3図(alに示′f
?XO<4i2の中eガラスパシベーション膜で覆い、
次1y)で第3図+b)に示すように六ソード側の表面
に第1の電極金属膜5を蒸着し、その後、第3図(cl
に示すように、アノードl1lllに前記金属膜5より
薄い第2の電極金属膜4全蒸着し、最後に、第3図1(
d)に示すように、ガラス1摸3の七の金属膜4をフォ
トエツチング技術などで除去する。このよ′うな11「
(の工程で製造した場合、ガラス膜3におけろクラ。
FIG. 3 (al to (dl) represent an embodiment of the present invention in step 11
As shown in Figure 2, Figure 3 (al.
? Covered with a medium e glass passivation film with XO<4i2,
Next, in step 1y), the first electrode metal film 5 is deposited on the surface of the six-sword side as shown in FIG. 3+b), and then, as shown in FIG.
As shown in FIG.
As shown in d), the metal film 4 on the glass 1 and 3 is removed by photo-etching or the like. 11 like this
(When manufactured by the process of (), the glass film 3 has a crack.

りの発生は非常に少なく、贅してガラス膜にに力すれが
生じることけほとんどない。特に六ソート”1則cvt
jJE膜5 )厚iが(1,7−1,Ottm、アノー
ド’ +1(Ifの金属膜4の厚芒を0.5〜0.7.
amとすることが最も重重しい。
The occurrence of scratches is extremely low, and there is almost no chance of damage to the glass film. Especially the 6 sort “1 rule cvt”
jJE film 5) The thickness i of the metal film 4 is (1, 7-1, Ottm, anode' + 1 (If) is 0.5 to 0.7.
Am is the most important.

このような本発明の効果は次のような理由によるものと
考えられる。
Such effects of the present invention are believed to be due to the following reasons.

即ち、第3図(alにっづ−て、第3図(blのように
カソードl1illに第1の金属膜5の047〜10μ
mを全面に入着すると、シリコン基板の厚さにもよるが
、第3図(alのときに、ガラス膜3によるシリコン基
板1のそりの曲率中心がこの図のようにアノード側にあ
ったものが、曲率半径が大きくなるが、または第3図(
blのようにカソード側にそりの曲率中心が移動する。
That is, as shown in FIG.
When the silicon substrate 1 is deposited on the entire surface, depending on the thickness of the silicon substrate, the center of curvature of the warp of the silicon substrate 1 due to the glass film 3 was on the anode side as shown in this figure. However, the radius of curvature becomes larger, or as shown in Fig. 3 (
The center of curvature of the warp moves toward the cathode as indicated by bl.

いずれにしても、第3図(alに比べて、そりが少なく
なる。次に第3図(clのようにアノード側に第2の金
属膜4の0.5−+0.7μmを蒸着すると、再びそり
の曲率中心がアノード側の方向に移動するが、第3図1
alのそりよりは少なくなっている。このようなそりの
程度シリコン基板にフォトエッチンクのハターン合せの
ためにフォ) マスク板全アノードill!Iがも押し
あてても、シリコン基板およびガラス膜の受ける応力は
少ないので、ガラスのクラックが少なくなる。まして、
はがれなどはほとんど発生しない。
In any case, the warpage will be less than that shown in Fig. 3 (al).Next, if a second metal film 4 of 0.5-+0.7 μm is deposited on the anode side as shown in Fig. 3 (cl), The center of curvature of the warp moves toward the anode side again, but as shown in Fig. 3,
The warpage is smaller than that of al. Due to the degree of warpage, the entire anode of the mask plate is ill! Even if the silicon substrate and the glass film are pressed against each other, the stress applied to the silicon substrate and the glass film is small, so there are fewer cracks in the glass. not to mention,
Peeling hardly occurs.

また、ガラス膜上の金属膜が除去てれて、応力開放され
てもシリコン基板のそりが少ないのでクラックが非常に
少なくなる。
Furthermore, even if the metal film on the glass film is removed and the stress is released, there is little warpage of the silicon substrate, resulting in very few cracks.

さらに金属膜5による応力が大きくて、カソード側への
そりが太きいため、アノード側へ金属膜4を蒸着せしめ
ても、なおそりの曲率中心がカソード側にあるときは、
フォトマスク板によってシリコン基板に押しあてても、
これによりガラス膜の受ける力は圧縮応力であり、クラ
ッタなどは発生しない。た、だしカソードII!Iへ蒸
着[,1:る金属膜5f被着せしめたとき、すててガラ
スにクラ、りが入る程度に厚い全縮1膜にすることは論
外である。
Furthermore, since the stress caused by the metal film 5 is large and the warpage toward the cathode side is large, even if the metal film 4 is deposited on the anode side, if the center of curvature of the warp is still on the cathode side,
Even if it is pressed against a silicon substrate using a photomask plate,
As a result, the force that the glass film receives is compressive stress, and clutter does not occur. Ta-dashi cathode II! When a metal film 5f is vapor-deposited on I, it is out of the question to make it into a fully shrunk film so thick that cracks and glue enters the glass.

例えば金属膜5の厚烙を2.0zzm以上にするとその
おそれが強くなる。
For example, if the thickness of the metal film 5 is set to 2.0 zzm or more, this possibility increases.

以上の説明ではシリコン基板の一主面のみにガラス膜が
被着せしめられているが、非対称であれは両1判に核着
きれていてもか寸わない。才だパシベーション膜として
は、ガラス膜だけでなく、酸化膜、窒化膜、リンガラス
膜などの多層膜でもよいことは明らかである。をらにメ
サ碑閘造のものについて説明埒れているがブレナー形(
を造であっても本発明は適用をれる。
In the above explanation, the glass film is deposited on only one main surface of the silicon substrate, but if the glass film is asymmetrical, it may be possible to adhere the glass film to both sides. It is clear that the passivation film may be not only a glass film but also a multilayer film such as an oxide film, a nitride film, or a phosphorus glass film. There is a detailed explanation of the mesa monument structure, but the Brenner type (
The present invention is applicable even if the

以上のように、本発明によれば半導体基板の表裏面にパ
シベーション膜が非t、J詐に覆われたものにおいて、
前記パシベーションI莫の存在しないが、寸たけ少ない
1f19の表面に第1の金厚膜を被着し、次いで他の1
則の表面に前記第1の金、萬脱より、偉い第2の金属膜
を被着し、最後に前記パシベーション膜上の金厚膜を除
去することKより樹脂刊正に工ろlダ雫や、高耐圧によ
る劣化を防止できるような多層あるいは厚いガラスj嘴
にしても、これらのパシベーション膜にクラ、りや!は
がれが発生することを非常に少なくすることができろと
いつ愛几た効果を得ろことができろ。
As described above, according to the present invention, in a semiconductor substrate whose front and back surfaces are covered with a passivation film in a non-t or J-shaped manner,
A first thick gold film is deposited on the surface of 1f19, which is free of the passivation I, but has a small amount, and then the other one is deposited.
Deposit a second metal film on the surface of the passivation film, which is stronger than the first gold film, and finally remove the thick gold film on the passivation film. Even if a multi-layered or thick glass beak is used to prevent deterioration due to high withstand voltage, these passivation films will not work! The occurrence of peeling can be greatly reduced and the beautiful effect can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はダイオード、3子基板の断面図、第2図は従来
の製1′北工程に分けるダイオード素子基板の断面図、
第3図は本発明に、【る製造工程におけろダイオード基
板の断面図である。 1・・・シリコン基板、3・・ガラス膜、4・・・アノ
ー矛  1  胆
Figure 1 is a cross-sectional view of the diode and triplet board, Figure 2 is a cross-sectional view of the diode element board divided into the conventional manufacturing 1' north process.
FIG. 3 is a sectional view of a diode substrate in the manufacturing process according to the present invention. 1...Silicon substrate, 3...Glass film, 4...Anor spear 1.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板の表裏面が非対称のパシベーション膜で覆わ
れた半導体素子の製造方法において、前金属膜を被着し
、最後に前記パシベーション膜上の金属膜を除去するこ
とを特徴とする半導体素子の製造方法。
A method for manufacturing a semiconductor device in which the front and back surfaces of a semiconductor substrate are covered with asymmetric passivation films, characterized in that a metal film is first deposited, and finally the metal film on the passivation film is removed. Method.
JP58000807A 1983-01-07 1983-01-07 Manufacture of semiconductor element Pending JPS59125630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58000807A JPS59125630A (en) 1983-01-07 1983-01-07 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58000807A JPS59125630A (en) 1983-01-07 1983-01-07 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS59125630A true JPS59125630A (en) 1984-07-20

Family

ID=11483947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58000807A Pending JPS59125630A (en) 1983-01-07 1983-01-07 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS59125630A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009138847A (en) * 2007-12-06 2009-06-25 Tokai Rubber Ind Ltd Fluid-sealed vibration control device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009138847A (en) * 2007-12-06 2009-06-25 Tokai Rubber Ind Ltd Fluid-sealed vibration control device

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