TW541652B - Method for fabricating a circuit layer - Google Patents

Abstract

A method is suited for fabricating at least one circuit layer on wafer that is provided with a first surface and a corresponding second surface. The method includes forming at least one sub-dielectric layer and warpage resistance layer respectively onto the first surface and the second layer, then forming at least one opening through the sub-dielectric layer, and next forming a metal layer into the opening and onto the sub-dielectric layer.

Description

541652

Gai Lei I: This is a chip structure 'and, in particular, a chip structure for improving the resistance-capacitance retardation problem. The current trend of the development of integrated circuit components in households, all of them is toward high-accumulation levels: ^ degrees, small size, multi-function, etc., so the volume of the chip's 0. Is J wave is toward a reduced design As far as semiconductor manufacturing is concerned, semiconductor devices with a line width of 浐 ϊ have entered mass production. In order to make the contact configuration of the back-end packaged wafers compatible with each other, in general, the wafers are in process: reconfigured the circuit layer so that the contact layout can be rearranged. However, when the current layer is re-arranged to 4 layers, 4 ′ of wafer warpage often occurs as described below. Refer to FIG. 1 and FIG. 2 for details, which are schematic cross-sectional views showing a method for manufacturing a dielectric layer of a conventional re-arranged line layer on a wafer. The wafer 1 10 has a small surface 112 and a corresponding second surface 114, and the wafer 110 further has an inquiry contact 116, which is arranged on the first surface 2 of the wafer 110. Next, proceed to the step of making a reconfigured circuit layer, wherein the step of making a reconfigured green layer includes a step of making a dielectric layer, as described below, which is a spin coating method to form a dielectric layer. 12 to the first surface 12 of the wafer 110, as shown in FIG. After that, the heating process is performed to make the dielectric solidify at 120. As the dielectric layer 120 is cured, there will be shrinkage, so that the wafer 110 will form a dielectric layer 120. The warpage on one side is as shown in the figure, and as the number of the dielectric layers 120 of the re-arranged wiring layer gradually increases, the degree of warpage of the wafer 110 will become more serious. In addition, because the thermal expansion coefficient of the dielectric layer 120 is different from the thermal expansion coefficient of the wafer 110, the wafer may also be warped during the curing or cooling process.

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时 ， #: "'第 约 2 图' When the wafer 110 has a serious warping phenomenon △ 二 ^ 付 付 Yue Yuan 110 is placed on the bearing platform of the machine. It is in smooth contact with the contact surface of the wafer 110, and the Japanese company is located between the contact surface of the carrier platform and the contact surface of the wafer 110. = If the vacuum nozzle is inhaling air, the outside air enters into the nozzle = and the wafer 110 cannot be firmly sucked on the carrier platform. When the wafer 110 is rotating at a high speed, the wafer 丨丨 0 will fly away and the wafer 110 will break. crack. In addition, when the wafer 110 has a slight curvature phenomenon, a problem of misalignment may occur during the exposure process, and the exposed pattern may have a large error. Therefore, one of the objectives of the present invention is to provide a method for manufacturing a circuit layer, which can reduce the degree of warpage of a wafer, so that the wafer can be firmly adsorbed on the supporting platform of the machine by a vacuum nozzle. Another object of the present invention is to provide a method for manufacturing a circuit layer, which can reduce the degree of wafer waviness, so that during the exposure process, the accuracy of pattern alignment can be increased, and the pattern error caused by the exposure can be reduced. Before describing the present invention, the use of space prepositions is defined. The so-called space; 丨 month means that the spatial relationship between two things is accessible or inaccessible. For example, object A is on object B. The meaning of ~ means that object A can be directly disposed on object B, and object A is in contact with object B; or object a is disposed in the space on object B. , A is not in contact with B. μ According to the above and other objectives of the present invention, 'a method for making a circuit layer is proposed, by which a circuit layer is suitable for making a circuit layer on a Japanese yen, and the wafer has a first surface and a corresponding first section. Second surface 'its line layer production 541652 5. Invention description (3) The production step is carried out, and at least one of the subroutines of the line production step, the line production step includes: steps-the first: 1 electrical layer to "Hai The first surface is formed and at least one frame is being formed, and is being formed .: 2i: Step two:% formation is at least-the opening is opened to the top. Step one is formed-the metal layer is in the mouth and the current is μ thousand. After the dielectric layer step, according to the preferred embodiment of the / H Ming 'its _ _ in the production of the circuit, the next step is to remove the anti-curvature layer on the surface of the circuit production step, which removes the anti-warpage丄? Into dry money engraving, grinding or peeling. In addition, Bu Ke = curved layer on the second surface, and then a sub-dielectric layer m = use: combined method to form "ϊ: ^ Ι 仃In the first step of the production step, an anti-curvy layer can be formed by spin coating first. Divination - of the present; after use or may be "on the stick, then the anti-warped solid layer. Forming the anti-warping layer to the second surface by applying a ^ Τ ^ ^ # ^ # The material of the sub-dielectric layer can be curled:. In a better case, the material is the same as that of the anti-warping layer, such as

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With the imine, the thermal expansion coefficient of the sub-dielectric layer is approximately equal to that of the warpage-resistant layer. According to the above and other objects of the present invention, a semiconductor circuit structure is provided, which includes at least a wafer, at least a sub-dielectric layer, at least a metal layer, and at least an anti-warping layer. The wafer has a first surface and a corresponding second surface. The sub-dielectric layer is located on the first surface of the wafer, and the sub-dielectric layer has at least one opening through the sub-dielectric layer and the metal layer is located. In the sub-dielectric = ^ opening and on the sub-dielectric layer. The anti-warping layer is located on the two surfaces of the wafer, and the number of the sub-dielectric layers is equal to the number of the anti-warping layers. As described above, the method for manufacturing the circuit layer of the present invention is due to the sub-media lightning 2 The anti-warping layer will shrink during the curing process. Therefore, the: 3 warping layer can: warp the side of the wafer to the side of the sub-dielectric layer. Control the thickness and material of the anti-warping layer so that the shrinkage stress of the γ-ququing layer is equal to the sub-media lightning spread ... When closing the load-bearing platform, * load: = thin, so when the wafer is placed on the bearing surface Contact, you can dream at this time: = The contact surface can be in close contact with the wafer. The carrier is set to = = solid;: At speed, the wafer is still available-during the exposure process with a solid solid, you can avoid wafer charm Therefore, in order to reduce the accuracy of the alignment of the exposed pattern, the above-mentioned and other objects of the present invention can be clearly understood.

541652 V. Description of the invention (5) The detailed description is as follows: Symbols of the drawings. 110 Wafer 112 First surface 114 Second surface 116 Contact 120 Dielectric layer 210 Wafer 212 First surface 214 Second surface 216 Contact 220 Dielectric layer 222 Anti-reflection layer 260 Dielectric layer 262 Anti-warping layer 282 First dielectric layer 284 First metal layer 286 Conductor layer 288 Reconfiguration circuit layer 292 Open a 294 Open σ 296 Contact

9536twf.ptd Page 8 541652 V. Description of the invention (6) ------- For examples, please refer to Figures 3 to 8 for the edge of the wafer according to the present invention. A schematic cross-sectional view of a method for configuring a wiring layer. The wafer 210 has a first surface 212 and a corresponding second surface 214. The wafer 21 has a plurality of contacts 216 disposed on the first surface 212 of the wafer 21G. Next, the step of manufacturing a reconfigured circuit layer is performed, which uses a spin coating method to form a sub-dielectric layer 2220 on the first surface 212 of the wafer 21 ′, and then uses the spin coating method <, Forming an anti-curvature layer on the second surface 214 of the wafer 2 10, as shown in FIG. 3; however, it is also possible to form an anti-curvature layer 2 2 2 to the second surface of the wafer 2 1 0 first. 2 1 4, and then a sub-dielectric layer 220 is formed on the first surface 212 of the wafer 210. After the sub-dielectric layer 2 2 0 and the anti-warping layer 2 2 2 are respectively formed on the first surface 2 丨 2 and the first surface 214 of the wafer 2 1 0, a heating process is performed to make the sub-dielectric The layer 220 and the anti-magma layer 222 are cured. θ Because the sub-dielectric layer 220 and the anti-warping layer 222 will shrink during the curing process, so the anti-bell warp layer 2 2 2 can prevent the wafer 2 1 0 from going to the sub-dielectric layer 2 2 The warpage of 0 is warped. In a better case, by controlling the thickness and material of the warpage-resistant layer 222, the shrinkage stress of the warpage-resistant layer 222 is equal to the shrinkage stress of the sub-dielectric layer 2 2 0. The wafer 210 can be maintained in a non-warped state, wherein the thermal expansion coefficient of the sub-dielectric layer 220 may be approximately equal to the thermal expansion coefficient of the anti-warpage layer 222. For example, the anti-buckling layer 222 may be configured with the same material as the sub-dielectric layer 220, for example, both are polyimide, and the anti-warping layer 222 and the sub-dielectric layer 220 are also controlled to have the same Thickness, so that the shrinkage stress of the anti-charm layer 2 2 2 can be equal to

9536twf.ptd Page 9 541652 V. Description of the invention (7) The shrinkage stress of the sub-dielectric layer 220 is the same as that of today. For example, the Shiye Marenji Temple Riri ® 21 〇 will be able to maintain the non-warped 2 electrical layer 282 and complete the production. The first dielectric layer 282 in the basin is made of the sub-dielectric layer 22f). M Λ, L /, A Brother .282 ^ 's production methods are repeated the previous process, and will not be described here. ;, If the first dielectric layer 282 is a photosensitive material, then only a lithography step is required, so that the opening 29 2 can be formed in the first dielectric layer 282 to expose the contacts 216, forming the structure shown in FIG. 4; if the first dielectric layer 282 is a non-photosensitive material, a lithographic etching step must be performed next, so that the opening 292 can be formed in the first dielectric layer. The electrical layer 282 exposes the contacts 216. After that, a first metal layer 284 can be formed in the opening 292 of the first dielectric layer 284 and on the first dielectric layer 282. The first metal layer 284 can be composed of multiple sub-metal layers. Each sub-metal layer can be formed by sputtering, steaming or electric ore. 'The lithographic silver engraving can be used to form the first metal layer 284 to define the circuit pattern' as shown in Figure 5. Shown structure. Next, a spin-coating method can be used to form a sub-dielectric layer 260 on the first dielectric layer 282 and the first metal layer 284, and then a spin-coating method can be used to form a warpage resistant layer. 2 6 2 onto the anti-curvy layer 2 2 2 as shown in FIG. 6; however, it is also possible to form the anti-warping layer 2 6 2 onto the anti-warping layer 222 first, and then form the sub-dielectric layer 260 to the first A dielectric layer 282 and a first metal layer 284. Next, the heating process can be performed to cure the sub-dielectric layer 260 and the anti-metamorphic layer 262. The shrinkage stress of the anti-metamorphic layer 262 can be controlled by controlling the thickness and material of the anti-metastatic layer 262.

9536uvf.pt d p.10 541652 V. Description of the invention (8) The state of the dielectric layer 2 6 0 is in the state of receiving and transmitting, and i A square ° \ is enough to keep the day and night 210 without wanting to protect this The layer m will be made as / f such as / ^, which will not be described here. As shown in 260, where the protective layer 286 is made of a sub-dielectric layer. The protective layer 286 can also be made of a multi-layer dielectric layer. In the manufacturing process, the protective layer 286 is made of a photosensitive material on the first material, and then only β ^ φ m ^ is required, so that the opening 294 can be formed in the protective layer 286, with ^ #layer, gold, and ^ layer. 284, where the first layer of gold ^ σ damage system exposed by the opening 294 is defined as contact 2 9 6, and the contact 2 9 6 can be electrically connected with a drawing) to form the contact shown in FIG. 7 The right protection layer 286 is a non-photosensitive material, and then the step of lithography is followed, so that the opening 292 can be formed in the first layer of metal layer 2 8 4 to protect the road. The reconfiguration circuit layer 2 8 8 is completed, and the reconfiguration circuit layer 288 is composed of the first dielectric layer 282, the protective layer 286, and the first metal layer 284. After the reconfiguration circuit layer 288 is manufactured, the anti-warping layers 222 and 262 can be removed by using wet etching, dry etching, grinding, or peeling to form a pattern as shown in FIG. 8. The above process can greatly reduce the warpage of the wafer 210, so when the wafer 2 is placed on the carrier platform of the machine, the contact surface of the carrier platform can closely contact the wafer 210. Surface contact, at this time, the wafer 21 can be firmly sucked by the vacuum nozzle to the main 3 on the carrying platform. Even when the wafer 21 is rotating at a high speed, the wafer 210 can be firmly fixed on the carrying platform. In addition, during exposure

Page 11 541652 V. Description of the invention (9) In the process of light ', the accuracy of pattern alignment can also be increased, and the pattern error exposed. As described above, as long as a sub-dielectric layer is formed on one side of the wafer, an anti-warping layer is formed on the other side of the wafer to prevent the wafer from warping. However, after reconfiguring the circuit layer as a component, it is also possible to leave the anti-curvy layer on the second surface of the wafer, and this removal of the anti-curvy layer is an optional step.

In addition, in the above process, the reconfiguration circuit layer is composed of a first dielectric layer, a first metal layer, and a protective layer. However, the present invention is not limited to the above applications. The layer may also be formed by alternately stacking multiple dielectric layers and multiple metal layers, and the manufacturing method thereof is to repeat the steps of manufacturing the first dielectric layer and the first metal layer in the foregoing embodiment. To repeat it, and finally to form a protective layer to protect the uppermost metal layer. And each dielectric layer is not limited to a single sub-dielectric layer, but may also be formed by stacking multiple sub-dielectrics. In addition, the protective layer is not limited to a sub-dielectric layer, and may also be formed by laminating multiple sub-dielectrics. In addition, in the foregoing embodiment, the sub-dielectric layer and the anti-warping layer are both made by spin coating and curing. However, the present invention is not limited to the above-mentioned applications, but the sub-dielectric layer and the anti-warping layer The curved layer can also be posted <

Formed on one side of the first surface of the wafer and on the second surface of the wafer, respectively. In the foregoing embodiments, the wafer is used as an example, however, the present invention can also be applied to other substrates, such as a substrate. In summary, the present invention has at least the following advantages:

541652 V. Description of the Invention (1) 1. The method of manufacturing the circuit layer of the present invention, because the substrate is cured, and the process will shrink, so it will be borrowed from the next; One side of the sub-dielectric layer is warped. In a better case, the thickness and material of the anti-warping layer made of I 纩 H 2 make the anti-warping thickness equal to: = ,. Therefore, when the wafer is placed; ==::, it can be in close contact with the wafer's contact surface. 9 An empty sound absorbs the wafer firmly on the carrier flat. When the circle is rotating at high speed, the wafer is still Can be firm = 2 years of new song 2. Therefore, in the method of making Λ / circuit layer, because the accuracy of the wafer can be avoided, the pattern alignment can also be increased during the first exposure process. , So it can reduce the pattern error exposed. The present invention has been disclosed as above in a preferred embodiment, but it is not a god. Anyone who is familiar with this skill can make various kinds of things without departing from the fine armor and crime of the present invention. ^ ^ w Departure range should be regarded as ethical material. ^ ^ move /, retouch, so the scope of the present invention's application # patent scope as defined. 541652

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Claims (1)

541652 VI. Scope of patent application 1 · A method for making a circuit layer, which is suitable for making a circuit layer on a wafer, and the wafer has a first surface and a corresponding second surface, the circuit layer. The manufacturing method includes: performing a circuit manufacturing step, and the flow of the circuit manufacturing step is performed at least once, wherein the circuit manufacturing step includes: Step 1: forming at least one sub-dielectric layer on the first surface and forming at least one reactance Warping the layer onto the second surface, step two: forming at least one opening in the sub-dielectric layer, step three: forming a metal layer in the opening and on the sub-dielectric layer. 2 · The method for fabricating a circuit layer as described in item 1 of the scope of patent application, wherein after performing the circuit fabrication step, the next step is to form the circuit formed on the second surface in the flow of the circuit fabrication step each time. Anti-warping layer removed. 3. The method for fabricating a circuit layer as described in item 2 of the scope of the patent application, wherein the method of removing the anti-warping layer is one selected from the group consisting of wet etching, dry etching, grinding and stripping. 4 · The method for fabricating a circuit layer as described in item 1 of the scope of the patent application, wherein when performing the step 1 of the circuit fabrication step, the sub-dielectric layer is first formed on the first surface, and then the resistance to warping is formed. Layer onto the second surface. 5 · The method for making a circuit layer as described in item 1 of the scope of patent application, wherein when performing the step 1 of the circuit production step, the warpage-resistant layer is first formed on the second surface, and then the sub-dielectric is formed. Layer to the first surface 9536twf.ptd Page 15 541652 6. The scope of patent application. 6. The method for fabricating a circuit layer as described in item 1 of the scope of patent application, wherein when performing the step 1 of the circuit fabrication step, the sub-dielectric layer is formed on the first surface by spin coating, and then The sub-dielectric layer is cured. 7. The method for making a circuit layer as described in item 1 of the scope of patent application, wherein in step 1 of the step of making the circuit, the warpage-resistant layer is formed on the second surface by spin coating, and then The warpage-resistant layer is cured. 8. The method for fabricating a circuit layer as described in item 1 of the scope of patent application, wherein when performing step one of the circuit fabrication step, the sub-dielectric layer is formed on the first surface in a laminating manner. 9. The method for fabricating a circuit layer as described in item 1 of the scope of patent application, wherein when performing step one of the circuit fabrication step, the warpage-resistant layer is formed on the second surface in a laminating manner. 10. The method for fabricating a circuit layer according to item 1 of the scope of the patent application, wherein the degree of warpage of the wafer caused by the sub-dielectric layer is approximately equal to the degree of warpage of the wafer caused by the anti-warpage layer. 11. The method for fabricating a circuit layer according to item 1 of the scope of patent application, wherein the material of the sub-dielectric layer is the same as that of the anti-Zhaoqu layer. 1 2. The method for fabricating a circuit layer as described in item 1 of the scope of the patent application, wherein the thermal expansion coefficient of the sub-dielectric layer is approximately equal to the thermal expansion coefficient of the anti-warping layer. 1 3. The method for making the circuit layer as described in item 1 of the scope of patent application, 9536twf.ptd Page 16 541652 6. Scope of patent application Where the sub-media is amine. … The material and the material of the anti-warping layer are all 14 kinds of circuit layer production methods of Poly-Aya, and the bamboo shoots are made by Xi Shilu: on-substrate, and the base two sea: method is suitable for production-line two surface The method of making the / Hai line layer includes: surface and corresponding-the first line is made half a doudou t is performed at least once, farming / step, and the flow of the line production step is a step-the line production step includes: and at least -I tortoise = to form at least one sub-dielectric layer on the first surface and a curved layer onto the second surface, and :: make at least one opening in the sub-dielectric layer, and- A metal layer is formed in the opening and the sub-dielectric layer is formed. After you enter the production process of the circuit, the next step is to remove the 湳 t layer in the green production process. In Captain J, the warpage resistance formed on the second surface is ^ 5, and the method for making the circuit layer described in item 14 of Shen Qing's patent scope is transferred from the method of removing the warpage resistance layer. It is one of the freshness of the family consisting of wet etching, dry etching, grinding and stripping from ^ ^ ^ Chen. Basin 16 · According to the method for making a circuit layer described in item 4 of the scope of the patent application, when performing step one of the circuit production step, the sub-dielectric layer is first formed on the first surface to form the An anti-warping layer is on the second surface. 7 1 7 · The method for making a circuit layer as described in the scope of the patent application, wherein when performing the steps of the circuit production step, the anti-glamour is first formed The 17th buy 9536twf.ptd, patent application scope Curved layer to this surface. After t is formed on the surface, the sub-dielectric layer is then formed to the first-line circuit layer manufacturing method, and the sub-dielectric layer is fixed by spin coating after 1 8 In progress, Γ asks for the 14th household patent in the scope of the patent to form this = step-by-step of the line production step. Μ ′ 丨 an electrical layer on the first surface According to the method for preparing a circuit layer described in the scope of application for patent No. 14, when performing the steps of the circuit production step, the anti-warpage layer is spin-coated on the second surface, and then the Anti-warping layer 20. The method for making a circuit layer as described in item 14 of the scope of the patent application. Second, when performing the step / step of the circuit production step, the sub-dielectric layer is formed to the first in a laminating manner. On the surface. 2 1 · The method for fabricating a circuit layer as described in item 4 of the scope of the patent application, wherein when step 〆 of the circuit fabrication step is performed, the warpage-resistant layer is formed on the second surface in a laminating manner. 2 2 · The method for fabricating a circuit layer as described in item 4 of the patent application scope, wherein the degree of warpage of the substrate caused by the sub-dielectric layer is approximately equal to the degree of warpage of the substrate caused by the anti-warpage layer . 2 3 · The method for fabricating a circuit layer as described in item 4 of the patent application scope, wherein the material of the sub-dielectric layer is the same as that of the anti-warping layer. 24. The method for fabricating a circuit layer according to item 14 of the scope of the patent application, wherein the thermal expansion coefficient of the sub-dielectric layer is approximately equal to the thermal expansion coefficient of the anti-warping layer. 9536twf.ptd Page 18 541652 VI. Application for Patent Scope 2 5 · The method for making a circuit layer as described in Item 14 of the patent application scope, wherein the material of the sub-dielectric layer and the material of the anti-warping layer are both poly醯 imine. 2 6 · A method for manufacturing a sub-dielectric layer on a wafer, by which the method is suitable for making a sub-dielectric layer on a wafer, the wafer having a first surface and a corresponding second surface, When the sub-dielectric layer is formed on the first surface of the wafer, an anti-warping layer is also formed on the second surface of the wafer. 2 7. The method for manufacturing a sub-dielectric layer on a wafer according to item 26 of the scope of patent application, wherein the sub-dielectric layer is first formed on the first surface, and then the anti-warping layer is formed on the first surface. On the surface. 2 8. The method for manufacturing a sub-dielectric layer on a wafer according to item 26 of the scope of the patent application, wherein the warpage-resistant layer is first formed on the second surface, and then the sub-dielectric layer is formed on the second surface. On the surface. 2 9. The method for manufacturing a sub-dielectric layer on a wafer according to item 26 of the scope of patent application, wherein the sub-dielectric layer is formed on the first surface by spin coating, and then the sub-dielectric layer is formed. The electrical layer is cured. 30. The method for manufacturing a sub-dielectric layer on a wafer as described in item 26 of the patent application scope, wherein the warpage-resistant layer is formed on the second surface by spin coating, and then the warpage-resistant layer is formed. The curved layer is cured. 3 1. The method for manufacturing a sub-dielectric layer on a wafer as described in item 26 of the patent application scope, wherein the sub-dielectric layer is formed on the first surface in a laminating manner. 3 2. The method for manufacturing a sub-dielectric layer on a wafer as described in item 26 of the patent application scope, wherein the warpage-resistant layer is formed to the second table in a laminating manner. 9536twf.ptd Page 19 541652 6. Scope of patent application Surface. 3 3. The method for manufacturing a sub-dielectric layer on a wafer as described in item 26 of the patent application scope, wherein the degree of warpage of the wafer caused by the sub-dielectric layer is approximately equal to that caused by the anti-surface warping layer Degree of thinking. 3 4. The method for manufacturing a sub-dielectric layer on a wafer according to item 26 of the scope of the patent application, wherein the material of the sub-dielectric layer is the same as that of the anti-glamour layer. 3 5. The method for manufacturing a sub-dielectric layer on a wafer as described in item 26 of the scope of patent application, wherein the thermal expansion coefficient of the sub-dielectric layer is approximately equal to the thermal expansion coefficient of the warpage-resistant layer. 3 6. The method for manufacturing a sub-dielectric layer on a wafer according to item 26 of the scope of the patent application, wherein the material of the sub-dielectric layer and the material of the anti-warping layer are polyimide. 37. A semiconductor circuit structure, including at least: a wafer having a first surface and a corresponding second surface; at least one sub-dielectric layer on the first surface of the wafer And the sub-dielectric layer has at least one opening penetrating the sub-dielectric layer; at least one metal layer is located in the opening of the sub-dielectric layer and on the sub-dielectric layer; and at least one anti-warping curve A layer on the second surface of the wafer. 38. The semiconductor circuit structure according to item 37 of the scope of the patent application, wherein the degree of warpage of the wafer caused by the sub-dielectric layer is approximately equal to the degree of warpage of the wafer caused by the anti-warpage layer. 9536twf.ptd Page 20 541652 6. Scope of patent application 39. The semiconductor circuit structure described in item 37 of the scope of patent application, wherein the material of the sub-dielectric layer is the same as that of the anti-warping layer. 40. The semiconductor circuit structure according to item 37 of the scope of the patent application, wherein the thermal expansion coefficient of the sub-dielectric layer is approximately equal to the thermal expansion coefficient of the warpage-resistant layer. 41. The semiconductor circuit structure as described in item 37 of the scope of the patent application, wherein the material of the sub-dielectric layer and the material of the anti-glamour layer are both polyimide. ❿ 4 2. The semiconductor circuit structure according to item 37 of the scope of the patent application, wherein the number of the sub-dielectric layers is equal to the number of the anti-curvature layers. 9536twf.ptd Page 21