JPS59121965A - Semiconductor device - Google Patents

Abstract

PURPOSE:To integrate a high resistance element consisting of an impurity diffusion layer in an integrated circuit containing a high dielectric-resistance element by forming an impurity low concentration region of the same conduction type as two impurity high concentration regions of a conduction type reverse to a base body between the impurity high concentration regions and forming a channel stopper region at a position separate from the impurity high concentration regions. CONSTITUTION:A resist layer 34 is formed for a patterning forming the impurity high concentration diffusion regions 8, 10 on the high dielectric resistance 17' side, and boron ions are implanted 35. The resist layer 34 is removed, boron ions are implanted 38 to the whole surface in both the high dielectric-resistance element 15' and the high dielectric resistance 17' and diffused into a substrate 1, and the impurity low concentration diffusion region 38 is formed around a drain region 37 of the high dielectric-resistance element 15. The whole is thermally treated in order to control the depth of the diffusion layers of the source and drain diffusion regions 36, 37 of the high dielectric-resistance element 15' section and the high concentration diffusion regions 8, 10 of the high dielectric resistance 17' section, thin oxide films formed to electrode window sections are removed through etching extending over the whole surface, Al electrodes 7a, 7b, 7c are patterned and the high dielectric-resistance element is formed, and Al electrodes 7a, 7b are patterned and a high dielectric-resistance element equipment is formed between the impurity high concentration diffusion regions 8, 10.

Description

[Detailed Description of the Invention] 1) Technical Field of the Invention The present invention relates to a high voltage resistance element consisting of an impurity diffusion layer provided on a semiconductor substrate, and particularly relates to a high voltage resistance element that can be formed in an integrated circuit with a fine vacuum. Regarding elements.

(2) Background of the technology Various resistance elements have been proposed in the past in which a resistor is formed by forming an impurity diffusion layer on a semiconductor substrate, but the resistance value is generally 100Ω with an error of about ±20%. ~30Ω
A certain degree is used.

Generally, to obtain high resistance, an interrupt type resistor is used. In other words, by creating an n+ emitter/vine diffusion layer in the p-type base diffusion layer, reducing the thickness of the base diffusion layer, and superimposing the emitter/vine diffusion layer on most of the high concentration base diffusion layer, a high resistance value can be achieved. The obtained method is known, but it has drawbacks such as a large tolerance.

In addition to such resistive elements, MO3 resistors are also known.

Since these require a large area, an MO3 resistor is used as the load resistor.For example, the MO3 load resistor is a MOSFET.
A typical MOS type resistor element structure is used, such as one in which the gate and drain of an ET are short-circuited by an AN electrode, and will be described in detail below.

(3) Prior Art and Problems Figure 1 is a cross-sectional view of a conventional MO3 resistor, and Figure 2 is a cross-sectional view of a conventional resistor in which an impurity diffusion layer is formed on a substrate, as previously proposed by the applicant. .

In FIG. 1, reference numeral 1 denotes an n-type substrate made of, for example, silicon, on which a filled oxide film 2 and an oxide film 3 are formed, and a P+ impurity high concentration diffusion region 4 is formed below the oxide film 3.

Electrode windows 5a and 5b are formed in the oxide film 3, and the oxide film 3
An insulating layer 6 such as PSG (phosphorus silica glass) is formed on the filled oxide film 2, and Aβ is formed on the electrode windows 5a and 5b.
Electrodes 7a and 7b are patterned to form electrodes 7a and 7b.
A resistor is constructed between 7b and 7b.

Figure 2 shows the resistor proposed by the applicant, 2M03FET.
There are P+ impurity high concentration diffusion regions 8.10 at the lower ends of the electrode windows 5a and 5b corresponding to the drain and source, and a P− impurity low concentration diffusion region 9 is provided between the high impurity concentration diffusion regions. The dose of the low impurity concentration diffusion region 9 is 10'λ~11013Ato/c++1, and the dose of the high impurity concentration diffusion region 8.10 is IOA tom/
It is about crA. Note that 11 is a channel stopper which is in contact with the high impurity concentration diffusion region 8.10. Since the other configurations are the same as those in FIG. 1, repeated explanation will be omitted. Such a configuration has the disadvantage that a high voltage resistance cannot be obtained. Currently, a display circuit as shown in FIG. 3 for driving a high voltage device such as a fluorescent display tube is used as a high voltage integrated circuit, and a high voltage resistance resistor I7 is used in such a circuit. In other words, in Fig. 3, the integrated circuit section has P-MO31.
3 and an N-MO314, and an output drive transistor consisting of, for example, a P-MOS, which serves as a drive section, and the transistor is configured as a high-voltage element and is connected to a high-voltage element. “ON” and “ON” are applied to the grid G of the fluorescent display tube 20 through the pad 16.
OFF voltage is supplied to make the fluorescent display tube 20 eosinic.

A voltage of about -30V is applied to the cathode C of the fluorescent display tube 20 from a voltage source 18 of, for example, about -35V through a zener 19, and a high voltage resistor 17 of about 10 OKΩ is connected between the voltage source 18 and the grid 0. This prevents flickering when blinking.

Since such a high voltage resistor 17 is attached externally to each fluorescent display tube, the value of one resistor is low in terms of cost, but in a system having a large number of fluorescent display tubes, This increases the mounting area, which is a major problem in making the system more compact.

(4) Object of the Invention In view of the above-mentioned conventional drawbacks, the first object of the present invention is to integrate a high resistance element made of an impurity diffusion layer in an integrated circuit including a high breakdown voltage element.

A second object of the present invention is to integrate high-voltage resistors.

The third object of the present invention is to
The object of the present invention is to provide a high-voltage resistor having a breakdown voltage of -40V or more at a voltage of about 0μ/100μ).

Still another object of the present invention is to provide a manufacturing method that allows a high voltage resistor to be obtained at the same time as a high voltage element such as a high voltage transistor or a high voltage protection element.

(5) Structure of the Invention According to the present invention, the object is to provide two high impurity concentration regions of opposite conductivity type to the semiconductor substrate in an active region separated by a thick insulating film in contact with the thick insulating film. At the same time, a low impurity concentration region of the same conductivity type as the high impurity concentration region is provided between the high impurity concentration regions, and the high impurity concentration Vi
This is achieved by a semiconductor device characterized by including a high breakdown voltage resistance element having a channel stopper region formed at a position spaced apart from the region.

(6) Embodiment of the Invention An embodiment of the present invention will be described in detail below with reference to FIGS. 4 to 6.

FIG. 4 (al, (bl) is a cross-sectional view and a plan view of a high breakdown voltage resistor according to the present invention, and two high impurity concentration diffusion regions 8
．． The low impurity concentration diffusion region 9 formed between 10 and 10 has the same conductivity type as the high impurity concentration diffusion region, and is between the channel stopper 11 at the lower end of the filled oxide film 2, which is a thick insulating film, and the high concentration diffusion region 8 and 10. 2 is provided with a cavity 22, and compared to the case where a channel cut stopper collides with the high impurity concentration diffusion regions 8 and 10 proposed by the present applicant as shown in FIG. A high-voltage resistor with a withstand voltage of 40V or more could be obtained. A diffusion region is formed in the semiconductor substrate as described above, and instead of connecting the external resistor 17 as shown in FIG. The process of forming the drive output MO5FET, which is the high breakdown voltage element 15, on the substrate at the same time will be described with reference to FIG.

In FIG. 5, the manufacturing process of the high voltage resistor 15 is shown on the left side of the drawing, and the manufacturing process of the high voltage resistor 17' is shown on the right side of the drawing.

In FIG. 5 [8], the substrate 1 is made of silicon with a concentration of 5×1
019 cm-2, and an oxide film 40 is formed on the substrate 1.
After forming (SiO2) to a constant thickness of 500 layers, a nitride film 23 (Si3Na) of 100 nm is formed on the insulating film 40 made of SiO2.
The nitride film 23 is selectively etched by exposing the resist 24 to light using a mask that defines the active region, as shown in FIG. 5(b).

FIG. 5 (bl) shows that a resist 25 for channel cutting is applied on the nitride film 23 and the insulating film 40, patterned with a mask, and a window is opened, and then phosphorus (P) is ion-implanted 27 through the window opening 26. .Dose amount is 6 x 10'''Cm
A channel stopper region 11.11 is formed in the substrate 1 by implanting at 80 K eV at -'.

Next, when the resist film 25 is removed and thermally oxidized using the nitride film 23 as a mask, a filled oxide film, that is, a thick insulating film 2
is formed. (FIG. 5(C)) Here, the nitride film 23 and the oxide film 40 formed under the nitride film 23 are removed.

Next, as shown in FIG. 5(di), a gate oxide film 30 is formed between the thick insulating films 2. The thickness of the gate oxide film 30 is approximately 700 mm.

Boron (B+) is injected into the gate oxide film '30 of the high voltage element 15 shown on the left side of FIG.
A threshold control N31 is formed by implanting about 10//cm-1 of. Thickness G ~ The layer on the insulating film 2 is the resist layer 28 .

The high breakdown voltage resistor 17' shown on the right side of dl in FIG. However, a resist layer 28 may be formed over the entire surface of the di-11-oxide film 30 and the thick insulating film 2 to prevent boron implantation.

Next, as shown in FIG. 5(e), the resist layer 28 is removed, and as shown on the left side of the high breakdown voltage element 15, polysilicon is coated on the gate oxide film 30 and patterned to form the gate 32 portion.

Next, on the high voltage element 15 side, the gate oxide film 30 in the active region is removed, leaving only the gate oxide film 30 under the polysilicon gate 32. At this time, the gate oxide film 30 on the high voltage resistor 17' side is also removed.

Then, a new oxide film 33 is added at 50° as shown in Fig.
After forming a resist layer 34 to a certain thickness and applying a resist layer 34, a source 36 is formed.
Then, patterning is performed to remove the drain 37 region, and boron ions are implanted 35 at a dose of 10''cm-'.

On the high voltage resistor 17' side, a resist layer 34 is used for patterning to form a high impurity concentration diffusion region 8.10.
is formed and boron is ion-implanted 35 at a dose of 101 cm-'.

Next, after removing the resist layer 34 as shown in FIG. A low impurity concentration diffusion region 39 is formed around the drain region 37 of the high voltage element 15 by diffusing into the substrate 1 .

Next, PSG 6 is formed on the thick oxide film 2 and the oxide film 33 by CVD or the like as shown in FIG. 5fh).

Next, holes for source, drain, and gate electrode windows are formed in the high voltage resistor 15, while windows are opened in the two high impurity concentration diffusion regions 8 and 10 in the high voltage resistor 17'. Next, a thin oxide film is grown to suppress out-diffusion of phosphorus from the PSG film 6. Next, the source and drain diffusion regions 36 and 37 of the high voltage element 15 and the high voltage resistance 17
After carrying out heat treatment to control the depth of the diffusion layer of the high concentration diffusion region 8.10 in the part '' and removing the thin oxide film formed in the electrode window part by etching the entire surface, A7! Electrode 7
Pattern a, 7b, and 7c to form a high voltage element,
Further, by patterning the Aβ electrodes 7a and 7b, a high breakdown voltage resistance element is constructed between the high impurity concentration diffusion regions 8° and 10°.

Through the manufacturing process as described above, the manufacturing process shown in FIG. 4 (al, (bl)
The high voltage resistor shown in is constructed.

In the above embodiment, the high voltage element 15 and the high voltage resistance 17 are
Although we have explained the case where it is formed on a type conductivity type substrate, FIG.
~(As shown in il, high voltage resistance element 15a and high voltage resistance 1
7a', an n-type well is formed in a p-type conductivity type substrate, and a p-type source/drain region or a low and high concentration diffusion region is formed in the well, or a p-type well is formed in an n-type substrate and the well is formed. An n-type source, train region, or low and high concentration diffusion region may be formed inside.

FIG. 6G describes the manufacturing process of a high breakdown voltage element and a high breakdown voltage resistor in which an n-type well is formed in a p-type substrate to form a p-type low concentration or high concentration region.

FIG. 6 shows the process of simultaneously manufacturing the high voltage resistor 15a on the left and the high voltage resistor 17a' on the right.

In FIG. 6 (al), the substrate 1 is p-type 20ΩcITl silicon, and an oxide film (SiO2) 40 is formed on the substrate.
After forming a nitride film 23 (St
3Na) to a thickness of 1,000 layers and patterning the nitride film 23 using a mask that defines the active region, only the nitride film 23 below the resist film 24 is left. Next, as shown in Figure 6 (bl), a window was opened and phosphorus (P+) was added at a dose of 4 x 10" cm -' to form an N well.
, 422 ion implantation at 250K eV then 1200
Running is performed for about 360 minutes in a N2 atmosphere at .degree. C. to form an n-type well 43 in the p-type substrate.

Next, as shown in FIG. 6(C), a resist 25 for channel cutting is formed on the 1% nitride 23 and insulating film 40, a window opening 26 is formed by ordinary photolithography, and phosphorus (P) is formed. Ion implantation 27 is carried out.

The dose in this case is 6 x 10"cm-' = 80
By implanting at K eV, a channel cut region n+ is formed in the N well 43. Thereafter, the manufacturing steps from FIG. 6 (dl to 01) are the same as the manufacturing steps from FIG. 5(C) to fhl, and the drain region 37 is
゜Source area 36. Since the rest is the same except that the gate electrode 32, high concentration diffusion regions 8, 10 and low concentration diffusion regions 9 are formed, repeated explanation will be omitted.

Note that FIG. 6 (gl to (1)) shows an enlarged view of the N well 43 portion.

The above explanation has been limited to the manufacturing process of the high voltage resistor 15 (15a) and the high voltage resistor 17'(17a'), but in reality the integrated circuit 12 has a C-MO3 configuration, and the reverse channel side is It is masked during the above manufacturing process. In addition, when manufacturing the reverse channel side, the high voltage resistor 15 (15a) and the high voltage resistor 17'(17a') are used.
can be considered to be masked.

(7) Effects of the Invention As explained in detail above, according to the high breakdown voltage resistor of the present invention, the depletion layer from the high impurity concentration regions 8 and 10 normally extends only to the substrate side, but in the case of the present invention. Since the channel cut region formed surrounding the high impurity concentration region 8.10 is spaced apart 22 as shown in FIG. 4, the depletion layer also expands in this region, thereby increasing the breakdown voltage. I can do it. In the case of FIG. 4, the breakdown voltage has been increased to -40V or more.

At this time, the values are such that the width of the low concentration region 9 between the two high concentration regions 8 and 10 is 10 μm, the length is 100 μm, and the distance is 3 μm.

In addition, since a high resistance value can be formed in a fine pattern by arbitrarily selecting the dose of the low impurity concentration diffusion region, it greatly contributes to the miniaturization of high voltage integrated circuits.

In addition, although the above embodiment describes an example that is applicable to a high voltage device such as a fluorescent display tube, the present invention is not limited to this, and the high voltage resistor of the present invention can be applied to a high voltage circuit that requires a high voltage resistance. is clear.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional MO3 resistor, Figure 2 is a cross-sectional view of a resistor in which a conventional impurity concentration diffusion layer is formed on a substrate. FIG. 4(a) is a circuit diagram illustrating a case where a high voltage resistor is used in a high voltage device (tube high voltage device). (bl is a side sectional view and a plan view of the high voltage resistor of the present invention,
Figures (a) to (h) are side sectional views showing the process of simultaneously forming the high voltage resistor of the present invention (a high voltage resistor (MOS) transistor), and Figures 6 (al to (il) are the resistors of the present invention). 1. It is each side sectional view which shows the process of forming a high voltage resistance and a high voltage resistance element simultaneously showing an Example. 1... Substrate, 2... Thick insulating film, 3.33.4
0...Oxide film, 4. 8. 10... High impurity concentration diffusion region, 5a, 5b... Electrode window, 6...
Insulating layer, such as PSG, 7a. 7b... Electrode, 9.39... Low impurity concentration diffusion region, -11... Channel stopper, 12...
Integrated circuit, 15,152...high voltage element,
17.17', 11a' --- High voltage resistance, 20.
...Fluorescent display tube, 23...Nitride film, 24, 25
, 28. 34... Resist, 30... Gate oxide film, 32... Kate electrode 36... Source region, 37... Train region, 43...
・N-type well region t+1 No. Il, ¥1 et h Fig. 2 1

Claims (1)

[Claims] Two high impurity concentration regions of the opposite conductivity type to the semiconductor substrate are formed in contact with the thick insulation film in an active region separated by a thick insulating film of a semiconductor substrate, and the high impurity concentration is formed between the high impurity concentration regions. What is claimed is: 1. A semiconductor device comprising a high breakdown voltage resistance element comprising a low impurity concentration region of the same conductivity type as the high impurity concentration region and a channel stopper region formed at a position spaced apart from the high impurity concentration region.