JPH10335641A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device where signals of large amplitude can be applied to a gate electrode by improving the device in operating withstand voltage. SOLUTION: N<-> source/drain regions 13 are formed on the surface of a semiconductor layer 11. A silicon oxide film is deposited to from an oxidation- resistant film 16. The diffusion window edge 18 of the N<-> source/drain regions 13 is made to recede from the edge 17 of the oxidation-resistant film 16 by a certain distance X. LOCOS oxide films 19 and 20 are formed using the oxidation-resistant film 16, and a gate electrode 23 is formed extending to an intermediate portion over the LOCOS oxide film 19. N<-> type impurity ions are implanted for the formation of N<+> source/drain regions 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device incorporating a high withstand voltage MOS element, and more particularly to an improvement in the operating withstand voltage.

[0002]

2. Description of the Related Art When an element for controlling a voltage amplitude of, for example, several tens of volts is integrated in a MOS type LSI, it is necessary to design and manufacture the element separately from other small signal elements. . 4 and 5 show a method of manufacturing a conventional high voltage MOS device. Incidentally, such an element is disclosed in, for example, JP-A-6-26.
No. 8262.

First, referring to FIG. 4A, a resist mask 2 is formed on a P-type semiconductor layer 1, and N-type source / drain regions 3 are formed by ion-implanting phosphorus (P). I do. Thereafter, the resist mask 2 is removed, and a heat treatment is applied to diffuse the source / drain region 3 to a desired depth. Referring to FIG. 4B, a new thin silicon oxide film 4 is formed on the surface of the semiconductor layer 1, a silicon nitride film is deposited thereon, and the silicon nitride film is patterned to form an oxidation-resistant film 5.

Referring to FIG. 4C, LOCOS oxide films 6 and 7 are formed on source / drain regions 3 by applying an oxidizing heat treatment to the whole. Referring to FIG. 5D, a gate electrode 8 made of polycrystalline silicon is formed on semiconductor layer 1 between LOCOS oxide films 6, and N-source / drain regions 3 between LOCOS oxide films 6 and 7 are formed. N on the surface
+ Source / drain regions 9 are formed.

The LOCOS oxide film 7 is an oxide film for element isolation. The LOCOS oxide film 6 is provided for the purpose of improving the dielectric strength between the gate electrode 8 and the source / drain regions 3 and 9. The end of the resist mask 2 for forming the N-source / drain region 3 and the end of the oxidation-resistant film 5 for forming the LOCOS oxide film 5 are aligned with each other. At the lower portion of the electrode 8, the edge of the LOCOS oxide film 6 coincides with the edge of the LOCOS oxide film 6.

[0006]

When a large-amplitude signal is controlled between the source and drain by applying a small-amplitude signal to the gate, the breakdown voltage should be maintained by the gate-drain breakdown voltage (Vdg). Withstand voltage when the source-drain voltage is changed with the gate open (BVds)
It is. However, in the case where a signal having a large amplitude of several tens of volts is applied to the gate as in a level shift circuit or the like, in addition to the above characteristics, the voltage between the source and drain when the voltage is applied to the gate is increased. The withstand voltage (operating withstand voltage) is the most important characteristic.

FIG. 6 shows a conventional operation withstand voltage characteristic. The gate voltage VG is kept constant, and the source-drain voltage Vds
Is measured when the current Ids between the source and the drain is changed and the characteristic when the gate voltage VG is changed in, for example, a step of 10 V is plotted. In a conventional device, particularly an N-channel device, for example, when a gate voltage is about 40 V, a desired source-drain voltage Vd
It was clarified that the element itself was destroyed due to the junction breakdown only by applying s. Therefore, there is a drawback that the operation withstand voltage is small and a signal with a desired amplitude cannot be controlled. Although it is possible to improve the operation withstand voltage simply by increasing the gate width W, the pattern size is increased.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has a structure in which the edge of a diffusion window in a source / drain region is set back from the edge of an oxidation-resistant film of a LOCOS oxide film. An object of the present invention is to provide a method of manufacturing a semiconductor device in which the operating voltage is improved by increasing the channel length GL.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.
This will be described in detail with reference to FIG. 1 to 4 are sectional views showing a method of manufacturing an integrated circuit according to the present invention in the order of steps. First, referring to FIG. 1A, a P-type semiconductor layer 11 made of a silicon semiconductor substrate or the like is prepared, and its surface is initially oxidized to form an oxide film. A resist film is formed on the oxide film, and a desired pattern is exposed and developed using a photomask to form a resist mask 12. Phosphorus (P) is ion-implanted from above with an acceleration voltage of 100 KeV and a dose of about 3E12 to form N-type source / drain regions 13.
Thereafter, the resist mask 12 is removed, and 100
By giving a heat treatment at 0 ° C. for several hours, the N-source
The drain region 13 is diffused to a diffusion depth of about 2.0 μ.

Referring to FIG. 1B, a new oxide film 14 having a thickness of about 500.degree. Is formed on the substrate surface, and a silicon nitride film is deposited thereon by a normal pressure CVD method or the like. Forming a resist mask on the silicon nitride film, patterning the silicon nitride film with the resist mask, and an oxidation-resistant film 15 located on the surface of the N-source / drain region 13;
An oxidation resistant film 16 located on the surface located on the P-type semiconductor layer 11 between the N-source / drain regions 13 is formed.
In design, the line width of the oxidation-resistant film 16 is substantially equal to the gate length GL (5 to 6 μ) of this transistor. And FIG.
In the step (A), the position 18 at the end of the resist mask 12 for forming the N-source / drain region 13 is set back by about 1.0 to 2.0 μ with respect to the position 17 at the end of the oxidation-resistant film 15. deep. The retracted length (X in the drawing) is hereinafter referred to as minus overlap OL.

Referring to FIG. 1C, LOCOS oxide films 19 and 20 are formed by thermally oxidizing the entire substrate in an oxidizing atmosphere. By retreating the position 18 of the resist mask 12 with respect to the position of the oxidation resistant film 16,
The end of the N-source / drain region 13 terminates below the LOCOS oxide film 19. Referring to FIG. 2A, LOC
The surface of the substrate surrounded by the OS oxide films 19 and 20 is cleaned and newly oxidized to form a gate oxide film 2 having a thickness of 500 to 2000 Å.
1 and then LOCOS oxide film 19 and LOCOS
N-source / drain region 13 sandwiched between oxide films 20
The thick oxide film also formed on the surface of the substrate is removed and oxidized again to form a thin oxide film 22. A gate electrode 23 is formed on the oxide films 21 and 22 by depositing a polysilicon layer having a thickness of about 2000 ° by a CVD method and performing phosphorus doping thereon, and then patterning the polysilicon layer. The gate electrode 23 covers part of the upper part of the LOCOS oxide film 19. Then, phosphorus (P) is adjusted to 60 KeV, 5.
Ion implantation is performed at an impurity concentration of about 0E13, and heat treatment is applied to form N + source / drain regions 24.

The device obtained by the above method is shown in FIG.
As shown in (A), the effective gate length Leff is increased by the amount provided with the negative overlap OL with respect to the designed gate length GL. Further, as shown in FIG. 2B, the end of the N-source / drain region 13 is
By terminating at the lower portion of the COS oxide film 19, the impurity concentration of phosphorus in the portion closest to the channel is higher than in the conventional case (the hatched portion 25 in the figure). This is due to the segregation (pile-up) of phosphorus due to the formation of the LOCOS oxide film 19. Since this region can be considered as an N + layer equivalently, the resistance value is small, and therefore, the gradient of the drain electric field is small inside the rising portion 25. Therefore, the elimination of the potential difference between the source and the drain is mainly performed inside the P-type semiconductor layer 11.

As a result of measuring the operating withstand voltage of the device manufactured by the above method in the same manner as the characteristic diagram shown in FIG. 6, when the source-drain voltage Vds was changed to a maximum of 80 V, the conventional device was found to have a gate voltage. While VG = 40V resulted in destruction, overlap OL was minus 1.0μ.
, It can withstand up to VG = 70 V, and when the overlap OL is -1.5 μm, V
Can withstand up to G = 100V, overlap O
When L was set to −2.0 μm, no destruction occurred even at VG = 100 V.

At the same time, a decrease in leakage current Isub from the channel to the semiconductor layer 11 during operation was observed. FIG. 3 shows that the source-drain voltage Vds is 6
FIG. 11 is a characteristic diagram showing a measured substrate current Isub when the gate voltage is fixed at 0 V and the gate voltage is changed from 0 V to 100 V.
In the conventional product having the overlap OL = 0, the gate voltage VG
Draws a curve that once saturates and peaks with the increase of, then rises again. Since the substrate current Isub is superimposed and flows through the drain junction, the large substrate current Isub is a factor that lowers the withstand voltage of the element, and such a phenomenon that increases again is considered to be a factor that lowers the operating withstand voltage. ing. On the other hand, in the case where the overlap OL is provided, a curve which rises again as in the related art is not observed, and the overlap OL is further reduced by -1.
When the value was changed from 0μ to −2.0μ, it was confirmed that the larger the value was, the lower the maximum substrate current value was. This is considered to be attributable in part to the fact that the impurity concentration in the N-source / drain region 13 adjacent to the channel is substantially increased due to the pile-up.

Therefore, according to the present invention, the operating withstand voltage of the element can be improved by retreating the end of the N-source / drain region 13. This makes it possible to form a high withstand voltage complementary circuit in combination with the P-channel element.

[0016]

As described above, according to the present invention, the N-source / drain region 13 and the LOCOS oxide film 19 are formed.
By adjusting the positions, the operation withstand voltage of the element can be greatly increased without increasing the pattern size.
In addition, since only a mask change is required, there is an advantage that the method can be performed without any additional process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing method of the present invention.

FIG. 2 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 3 is a characteristic diagram for explaining the present invention.

FIG. 4 is a cross-sectional view for explaining a conventional example.

FIG. 5 is a circuit diagram for explaining a conventional example.

FIG. 6 is a characteristic diagram illustrating a conventional example.

Claims (2)

[Claims] 1. A semiconductor device according to claim 1, wherein a source layer is formed on a surface of the semiconductor layer of one conductivity type.
A step of forming a diffusion window for forming a drain; a step of forming a first source / drain region by diffusing an impurity of the opposite conductivity type from the diffusion window; an upper portion of the source / drain region;
Forming an oxidation-resistant mask on the one conductivity type semiconductor layer between the drain regions; selectively oxidizing the surface of the semiconductor layer to form a LOCOS insulating film; On the semiconductor layer, the LO
Forming a gate electrode extending halfway to the upper part of the COS oxide film, wherein the position of the diffusion window is changed so that the effective value of the gate length is increased. A method of manufacturing a semiconductor device, wherein the semiconductor device is retracted from a position. 2. The semiconductor device according to claim 1, wherein said semiconductor layer is P-type,
2. The method according to claim 1, wherein the drain region is N-type.