JPS59121951A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To isolate an element effectively and practically by forming a first insulator region for isolating the element buried in a groove formed to a base body and a second insulator region for isolating the element with an inclined plane more gentle than said region. CONSTITUTION:A silicon oxide film 22, a silicon nitride film 23 and a CVD silicon oxide film 24 are each formed on the surface of a silicon semiconductor substrate 21. The silicon oxide film 24 is patterned, a resist 25 is applied, the resist 25 is patterned, and the silicon nitride film 23 and the silicon oxide film 22 are etched selectively. The substrate 21 is etched, and the upper end surface of a select oxide film formed is lowered. Boron ions are implanted to form a P<+> region 26, and an element isolation (a field oxide film) 27 is formed through select oxidation. The resist is applied again, and the silicon nitride film 23 and the silicon oxide film 22 are each etched selectively. The exposed section of the substrate 1 is etched to form the groove for isolating the buried element, a P<+> type region 28 is formed in the groove, silicon oxide is buried in the groove on which a silicon oxide film 29 is formed, and the whole surface of the silicon nitride film 23 is etched. Accordingly, the semiconductor device, in which element isolations of different size mix and exist and which contains the element isolations of small size which cannot be attained through select oxidation, can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a semiconductor device including an element isolation region and a manufacturing method thereof.

(2) Prior Art and Problems Today's integrated circuit element isolation is mostly performed by selective oxidation. Referring to FIG. 1, after thinly oxidizing the surface of a silicon semiconductor substrate 1, a silicon nitride film 3 is usually deposited.
・Cutning and opening a window (Figure 1 (A)). When placed in an oxygen atmosphere, the silicon nitride film 3 blocks oxygen penetration, so only the window portion 4 is selectively oxidized (see Figure 1 (A)). Figure 1 (→).However, since oxygen does not only diffuse downward from the window, it also diffuses laterally from the edge of the window toward the bottom of the silicon nitride film 3, causing oxygen to diffuse to the edge of the window. A so-called bird's beak 5 is formed.The horizontal size of the bird's beak 5 is approximately half the thickness of the oxide film 4, and the thickness is 1 μm.
In the case of an oxide film of m, wide bird peaks of about 0.4 to 0.5 μm are formed at both ends, so the total peak is about 0.8 to 0.5 μm.
It becomes 1 μm. Therefore, this bird peak becomes an obstacle when trying to increase the density.

Therefore, a method has been proposed in which #I is formed in a silicon semiconductor substrate and silicon oxide, polycrystalline silicon, or the like is buried therein. However, this method has the following problems when there is a large difference in the dimensions of the element isolation regions. Referring to FIG. 2, rhenostore is applied onto a silicon semiconductor substrate 6, and selectively etched using a resist pattern of zq p -= nf L,'c as a mask to form a groove A with a large dimension and a groove with a small dimension. Consider the case of forming B (Fig. 2 (a)). Remove resist 7 and create grooves A and B.
A silicon oxide film 8 is formed by oxidizing the inside of the grooves A and H, and a silicon oxide layer 9 is deposited thereon by the CVD method to fill the insides of the trenches A and H (FIG. 2(b)). At this time, the surface of the silicon oxide layer above the small groove B becomes flat, but a depression is formed in the silicon oxide layer above the large groove A. Therefore, when the entire surface is etched to remove excess silicon oxide outside the grooves, the small grooves B are filled with silicon oxide, but the large grooves B hit the recesses in the original silicon oxide layer. Therefore, there is a problem that the silicon oxide inside the groove is etched and the inside of the groove is not filled (Figure 2 (c)).
).

(3) Purpose of the Invention The present invention is based on the inventor's discovery of the problems of the prior art as described above, and aims to perform effective and practical element isolation in a highly integrated semiconductor device.

(4) Structure of the Invention A semiconductor device according to the present invention that achieves the above object includes a first element isolation insulator region embedded in a groove formed in a semiconductor substrate, and a first element isolation insulator region formed in the semiconductor substrate. and a second element isolation insulator region having a gentler slope with respect to the inner surface of the semiconductor substrate than the first element isolation insulator region.

Further, a method for manufacturing a semiconductor device according to the present invention which similarly achieves the above object includes selectively oxidizing a first region of a semiconductor substrate to form an oxide region. and forming a trench in a second region different from the first region of the semiconductor substrate, and filling the entire trench with an insulator.

The feature of the present invention is, in short, that the above-mentioned embedding method is used for element isolation in parts of a semiconductor device that require a high degree of integration; The purpose is to utilize oxidation. For example, in a memory semiconductor device, referring to FIG. 3, the embedding method is used in the memory cell portion 12 of the semiconductor chip 11 to increase the degree of integration and storage capacity, while at the same time separating the peripheral circuits 13 and them. A selective oxidation method may be used for the region 14. Insulating trenches formed by the embedding method have a steep slope with respect to the surface of the substrate because the grooves are formed by etching, whereas oxide films formed by the selective oxidation method have a gentle slope with respect to the surface of the substrate known as Bird's peak.

(5) Examples of the invention The following is a detailed explanation using examples. Element isolation is carried out by selective oxidation for large dimensions and by embedding for small dimensions. I will explain. In general, element isolation by the embedding method is for small dimensions that do not differ greatly, while element isolation by the selective oxidation method is for relatively large dimensions, and differences in the dimensions of the filter do not matter.

Please refer to FIG. A silicon oxide film (500 mm thick) 22, a silicon nitride film (1500 mm thick) 23, and a CVD silicon oxide film (150 mm to 200 mm thick) 24 are formed on the surface of the silicon semiconductor substrate 21 (FIG. 4). (stomach)). The silicon oxide film 24 is turned 79 times to form a 4' turn in a self-aligned manner for both the element isolation region by selective oxidation and the element isolation region by burying (FIG. 4(b)). .

A resist (thickness: 1 μm) 25 is applied, leaving the resist above the window of the pattern for the device isolation region by embedding, and applying resist on the window of the pattern for device isolation by selective oxidation. The resist 25 is patterned so as to be removed, and the patterned resist 2
The silicon nitride film 23 is selectively etched using 5 and the silicon oxide film 24 as a mask, and the silicon oxide film 22 is selectively etched in the same pattern as the resulting silicon nitride film 23 (FIG. 4e-9). Optionally, a silicon semiconductor substrate 2
The exposed portion of 1, that is, the portion to be selectively oxidized, is subjected to anisotropic etching (KOH) or isotropic etching (dry etching).
The upper end surface of the selective oxide film to be formed is lowered. After ion-implanting boron to form a door region 26, selective oxidation is performed to form an element isolation (field oxide film) 27 (see FIG. 4).
).

Renost (not shown) is applied again, and this time the regimen on the window part of the silicon oxide film 24 for the element isolation region by embedding is removed, and the silicon nitride film 23 and the silicon oxide film 22 are selectively coated. Etching. The exposed portion of the silicon semiconductor substrate 1 is anisotropically etched or isotropically etched to form trenches for buried element isolation. After ion-implanting boron into the groove to form a V-shaped region 28, it is oxidized to form a silicon oxide film (thickness 1500X) on the surface.
29 (Fig. 4 (e)). Silicon oxide film 29
Silicon oxide or PSG with a low phosphorous concentration is buried in the groove formed by CVD, or silicon oxide is buried with a 4' ivy (see reference numeral 30 in FIG. 4(f)1). The entire surface of the silicon nitride film 23 is etched.

A large-sized element isolation 27 formed by selective oxidation and a small-sized element isolation 30 formed by embedding coexist in the silicon semiconductor substrate 1 (FIG. 4(G)).

Selectively, in the same manner as in the above example, a silicon oxide film 22, a silicon nitride film 23, and a silicon oxide film 24 were formed on a silicon semiconductor substrate 21, and patterned with the silicon oxide film 24 (FIG. 4(A)). .

After (b)), contrary to the above example, the buried element isolation may be formed first and then the selective oxidation element isolation may be formed. A resist 31 is applied on the patterned silicon oxide film 24, and the resist on the window portion of the silicon oxide film 24 for element isolation by embedding is removed, and the silicon nitride film 23 and the silicon oxide film 22 are selectively removed. Etching.

The exposed silicon semiconductor substrate 21 is anisotropically or isotropically etched to form a trench for embedding (see FIG. 4).
stomach)). The resist 31 is removed, and the silicon nitride film in the selectively oxidized region is selectively etched and removed using new renost (not shown).

Boron ions are implanted to form P+ type regions 32 and 33 in both the buried trench and the selective oxidation region, and the regions are oxidized and covered with a silicon oxide film (1500i thick) 34.

Into the embedding trench, bury silicon oxide or PSG with a low phosphorous concentration using CvD, or silicon oxide using suzetta (see 35 in Figure 4). Etch the entire surface of the silicon oxide or PSG35. A silicon nitride film (thickness: 500×) 36 is formed on the surface, leaving it only in the groove. Using the patterned film as a mask, apply Renost (not shown) and apply the silicon nitride film 36 to the area to be selectively oxidized. At the same time, the formed silicon nitride film (not shown) is etched and removed, and the resist is removed (FIG. 4). Using the silicon nitride film 23.36 as a mask, an element isolation (field oxide film) 37 is formed by selective oxidation, and the entire surface of the silicon nitride film 23.36 is etched. Element isolation 35 by embedding on silicon semiconductor substrate 1
and element isolation 37 by selective oxidation coexist (see Figure 4).
).

(6) Effects of the Invention As is clear from the above explanation, the present invention makes it practical to manufacture semiconductor devices in which element isolations of different sizes coexist and include element isolations of small dimensions that cannot be achieved by selective oxidation. It becomes possible to provide.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a semiconductor device in order of process to explain element isolation by selective oxidation, Figure 2 is a cross-sectional view of a semiconductor device in order of process to explain element isolation by embedding, and Figure 3 is a plan view of a memory semiconductor device. 4A and 4B are sectional views showing the steps of manufacturing a semiconductor device to explain the present invention in detail. 1.6.21...Substrate, 4.27.37...Selective oxide film, 30.35...Buried region, 11...Memory semiconductor device, 12...Memory cell section. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney 1) Yukio Patent attorney Akiyuki Yamaguchi Figure 4 (a) (d) ′) 7 Italy) 9 26 28 (f) 628 (g)

Claims (1)

[Scope of Claims] 1. A first element isolation insulator region embedded in a groove formed in a semiconductor substrate; 1. A semiconductor device comprising a second element isolation insulator region which also has a gentle slope than the isolation insulator region. 2. selectively oxidizing a first region of the semiconductor substrate to form an oxide region; forming a groove in a second region of the semiconductor substrate different from the first region; 1. A method for manufacturing a semiconductor device, comprising the step of filling the area with an insulator.