JPS59121850U - Ｌｓｉチツプ - Google Patents

Ｌｓｉチツプ

Info

Publication number
JPS59121850U
JPS59121850U JP1983015633U JP1563383U JPS59121850U JP S59121850 U JPS59121850 U JP S59121850U JP 1983015633 U JP1983015633 U JP 1983015633U JP 1563383 U JP1563383 U JP 1563383U JP S59121850 U JPS59121850 U JP S59121850U
Authority
JP
Japan
Prior art keywords
lsi chip
circuits
chip
recorded
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983015633U
Other languages
English (en)
Inventor
徹 山下
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP1983015633U priority Critical patent/JPS59121850U/ja
Publication of JPS59121850U publication Critical patent/JPS59121850U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図イは本考案に係るＬＳＩチップの平面図、同図口
は同チップの側面図、第２図乃至第４図は同チップのボ
ンディングを説明する図である。 １はＬＳＩチップ、２及び３は駆動回路、４は半田バン
プ、５は回路基板、６はボンディングパターン。

Claims (1)

    【実用新案登録請求の範囲】
  1. 略同−機能を有する複数個の表示体駆動回路と、これら
    回路の各端子を具えて成ることを特徴とするＬＳＩチッ
    プ。
JP1983015633U 1983-02-04 1983-02-04 Ｌｓｉチツプ Pending JPS59121850U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983015633U JPS59121850U (ja) 1983-02-04 1983-02-04 Ｌｓｉチツプ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983015633U JPS59121850U (ja) 1983-02-04 1983-02-04 Ｌｓｉチツプ

Publications (1)

Publication Number Publication Date
JPS59121850U true JPS59121850U (ja) 1984-08-16

Family

ID=30146957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983015633U Pending JPS59121850U (ja) 1983-02-04 1983-02-04 Ｌｓｉチツプ

Country Status (1)

Country Link
JP (1) JPS59121850U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5636148A (en) * 1979-08-31 1981-04-09 Fujitsu Ltd Semiconductor device and its manufacture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5636148A (en) * 1979-08-31 1981-04-09 Fujitsu Ltd Semiconductor device and its manufacture

Similar Documents

Publication Publication Date Title
JPS59121850U (ja) Ｌｓｉチツプ
JPS60141129U (ja) リ−ドレスチツプキヤリアの端子構造
JPS60169860U (ja) 混成集積回路
JPS59185853U (ja) マイクロ波集積回路用金属パツケ−ジ
JPS5999477U (ja) 混成集積回路装置
JPS59107139U (ja) 回路基板のｉｃチップ実装構造
JPS5942045U (ja) フラツトパツケ−ジ集積回路取付装置
JPS59121856U (ja) プリント基板
JPS6096846U (ja) 半導体集積回路装置
JPS59115641U (ja) 回路基板のモ−ルド流れ防止構造
JPS58182458U (ja) 回路ユニツト
JPS58114064U (ja) 印刷配線板
JPS60194372U (ja) 混成集積回路
JPS59143050U (ja) 半導体装置
JPS6076058U (ja) 電子部品の実装構造
JPS5936259U (ja) 多角すいピンチツプキヤリア
JPS614463U (ja) ハイブリツド集積回路
JPS59176175U (ja) プリント回路基板
JPS60130672U (ja) プリント配線基板
JPS58191651U (ja) 集積回路
JPS605170U (ja) 半導体素子用プリント基板
JPS6039245U (ja) ワイヤ−ボンデイングの位置決めマ−ク
JPS6078158U (ja) 混成集積回路基板
JPS58124977U (ja) 回路素子の実装構造
JPS59106671U (ja) ハンダごてチツプ