JPS59117618A - Data bus controller - Google Patents

Abstract

PURPOSE:To transfer data with a high reliability, by switching a data bus, where a parity error is detected, to another data bus. CONSTITUTION:If the parity error is detected by the first parity check circuit 1, it is reported to a byte switching control circuit 13. The circuit 13 instructs the retry to an input control circuit 7 as well as an output control circuit 12. The circuit 12 switches an output switching circuit 9 to the side of a transfer register 10 to transmit data to a data bus 102. The circuit 7 switches an input switching circuit 5 to the side of the data bus 102 to store the output of the circuit 5 in an input register 3. The output control circuit 12 switches the output switching circuit 9 to the side of a transfer register 11 to transmit data to the data bus 102. The circuit 7 switches an input switching circuit 6 to the side of the data bus 102 to store the output of the circuit in an input register 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data bus transfer device having a multi-byte transfer data bus.

(Prior Art) Conventionally, in this type of data bus transfer device, when a parity error is detected in a unit byte of data to be transferred, a message indicating that the corresponding process and the following process cannot be executed is detected. In addition, if one of the multiple devices connected to the data bus fails, it may affect other devices that have not failed. There is a drawback in that as the number of devices connected to this data bus increases, the reliability of data transfer may further deteriorate.

(Object of the Invention) The object of the present invention is to provide a structure in which, when a parity error is detected by a parity pit added to each byte, the data bus on which the corresponding parity error is detected is switched to another data bus. The object of the present invention is to provide a data access control device that eliminates the above drawbacks and can perform data transfer with i% reliability.

(Structure of the Invention) A data bus controlled ill device according to the present invention includes a plurality of transfer registers, a plurality of output switching circuits, a plurality of input switching circuits, a plurality of input registers, and a plurality of parity check circuits. , output control circuit, and input fl\ll+
1111 circuit and a byte switching control circuit.

Each of the plurality of transfer registers is for storing data in byte units. The plurality of output switching circuits are for switching the contents of the plurality of transfer registers and sending them to the corresponding plurality of data buses. Each input switching circuit is used to switch the contents of a plurality of data buses as input and output the corresponding byte of data.

The plurality of input registers are for correspondingly storing the outputs of the respective input switching circuits. multiple bars
The gamma check circuit is for individually performing parity checks on the outputs of a plurality of input registers.

The output control circuit is for controlling each of the plurality of output switching circuits during data transfer. The input control circuit is for individually controlling the plurality of five input switching circuits and the plurality of input registers during data transfer.

When a parity error is detected in the parity check, the byte switching control circuit performs a corresponding data transfer attempt to control the input control circuit and output control circuit.

One of the plurality of parity check circuits included in the present invention is a When a parity error is detected in the input switching circuit, the input switching circuit and the output switching circuit are switched at the same time, and data can be retransferred without using the data bus on the side where the parity error was detected.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

An embodiment of a data bus control device according to the present invention is shown in FIG. In FIG. 1, the data bus control device includes first and second parity check circuits 1 and 2, first and second input registers 3.4, and first and second input switching circuits 5.6. , input control circuit 7, and the first and l'!
2 output switching circuits 8 and 9, first and second transfer registers 10 and 11, an output control circuit 12, and a byte switching control circuit 13, and further includes first and second data buses 103, 102.

The first and second transfer registers 10 and 11H are for transferring the first and second bytes, respectively. The first output switching circuit 8 is connected to the first transfer register 10.
This is used to switch the contents of the transfer register 11 and the contents of the second transfer register 11 and send it to the first data bus 101. Second output switching circuit 9r/'i first transfer register 10
This is used to switch the contents of the transfer register 11 and the contents of the second transfer register 11 and send it to the second data bus 102. The first input switching circuit 5 connects the first and second data buses 1
This is for manually switching the data of 01 and 102 and inputting the data of l<1 byte to the first input register 3. The second input switching circuit 6 is for inputting and switching the data on the data buses 101 and 102 of the first data bus 2, and providing the second byte of data to the second input register 4. The first input register 3\'i is used to temporarily hold the data of the first byte and send it to the first parity check circuit l. Second input register 4
This is for temporarily holding the second byte of data and sending it to the second parity check circuit 2. 1st
A parity check circuit 1 is used to check whether the contents of the first input register 3 are valid in units of bytes using a parity check method, and to notify the byte switching control circuit 13 whether the result is correct or not. It is something. The second parity check circuit 2 uses a parity check method to check whether the contents of the second input register 49 are normal or not in byte units, and notifies the byte switching control circuit 13 whether or not the result is correct. It is something.

The input side section 1 circuit 7 is for controlling the first and second input switching circuits 5 and 6 and the first and second input registers 3 and 4 during data transfer. Output control circuit 1
Reference numeral 2 is for controlling the first and second output switching circuits 8 and 9 during data transfer. Byte switching control circuit 13 When detecting parity, I of the corresponding data transfer
J) Lie, input control circuit 7 and output control circuit 12
The purpose is to control the

The first parity check circuit 11C, 1 is connected to the first parity error signal line 103 so that the state becomes 1 when a parity error is detected. The second parity error signal line 104 is connected to a line in which a parity error is detected by the second parity check circuit 2.
V: is configured so that the state becomes 1. The signal on the first byte output instruction line 112 is
At the same time, the first output is switched off for the first data bus 101 (this is to give permission for data to be output from the output circuit 8). The signal on the second byte output instruction line 113 switches the input of the first output switching circuit 9 during data transfer, and also outputs data from the second output switching circuit 9 to the second data bus 102. The output request line 108 is used to input data sent from the output control circuit 12 during data transfer to the input control circuit 7.The output request line 109
When the state of the signal on the H1 output request line 108 becomes 1,
The signal on the output request line 109 becomes 1 if data input can be accepted. 1st byte input switching line 115
is used to instruct the first input switching circuit 5 to switch during data transfer. The second byte input switching line 114 is connected to the second input switching circuit 6 during data transfer.
This is to instruct switching to. The first byte input storage line 111 is for instructing the storage of data into the first input register 3, and the second byte input storage line 110 is for instructing the storage of data into the second input register 4. It is for. The data transfer line 106 is for reporting the presence or absence of data transfer to the byte switching control circuit 13. First error detection retry instruction line 10
5C. This is for giving the output of the byte switching control circuit 13 to the input control circuit 7, and is for issuing a control m11 instruction to the input control circuit 7 at the time of retry due to parity error detection during data transfer. It is.

Second Error Detection IJ) The lie instruction line 107 is for giving the above information to the output control circuit 12 and instructing control.

When data is stored in the first transfer register 10 and the second transfer register 11 during data transfer, the output control circuit 1
2, the state of the signal on the output request line 108 becomes 1. When the state of the signal on the output request line 108 becomes 1, the state of the signal on the output permission line 109 becomes 1 if the input control circuit 7 can receive the data. Output permission line 1
When the state of 09 becomes 1, the output control circuit 12 switches the first output switching circuit 8 to the first byte output instruction line 112.
is switched to the first transfer register 10 and sent to the first data bus 101. At the same time, the second output switching circuit 9 is switched to the second transfer register 11 side by the second byte output instruction line 113, and data is sent from the second output switching circuit 9 to the $2 data bus 102. let

At this time, the first input switching circuit 5 is controlled from the input control circuit 7 via the byte input switching line 115 of '1J4i, and the first input switching circuit 5 is switched to the first data bus 101 side. At this time, similarly, the second input switching circuit 6 is controlled via the second byte input switching line 114,
The second input switching circuit 6 is switched to the second data bus 102 side.

As a result, the state of the signal on the first byte input storage line fill is set to 1, and the output of the first input switching circuit 5 is set to 1.
input register 3, and changes the state of the signal on the second byte input storage line 110 to 1. Then, the output of the second input switching circuit 6 is stored in the second register 4. As described above, data transfer is performed when no parity error is detected.

Next, the parity error is detected by the first parity check circuit 1.
If a false error is detected, this state is reported to the byte switching control circuit 13 via the first byte parity error line 103.

Based on this report, the byte switching control circuit 13 instructs the input control circuit 7 to retry via the first error detection retry instruction line 105, and similarly, the second error detection IJ) retry instruction line 107 is sent to the input control circuit 7. Instructs the output-side shaft circuit 12 to retry via the output-side shaft circuit 12. In response to this instruction, the output control circuit 12 first outputs the second byte output instruction line 113.
The second output switching circuit 9 is switched to the first transfer register 10 side via the second data bus 102, and data is sent to the second data bus 102. The input control circuit 7 switches the first input switching circuit 5 to the second data bus 102 side via the first byte input switching line 115, and switches the first input switching circuit 5 to the second data bus 102 side via the first byte input switching line 115.
11 to store the output of the first input switching circuit 5 in the first input register 3. Next, the byte output instruction line 113 of the output control circuit 12Hffi2 causes the second
The output control circuit 9 is switched to the second transfer register 11 side, and the data is sent to the second data node 102.

The input control circuit 7 connects the second switching line 114 to the second input switching circuit 6iffi2(7) and the data bus 1.
02 side and the second manual switching circuit 6 to the second input register 4 using the second byte input storage line 110.
Store the output of When a parity error is detected by the second parity check circuit 2, the data is transferred to the first data bus 10 using the same method, contrary to the above method.
1 and transfer it.

Although this embodiment is an example of data transfer with a width of 2 bytes, it is possible to easily perform data transfer with a width of 3 bytes or more in the same manner.

(Effects of the Invention) As explained above, the present invention is capable of transferring data without using the data bus on which the error was detected when a parity error is detected (using the parity pit provided for each bit). This has the effect of significantly improving the reliability of data transfer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a data access control device according to the present invention. 1.2 Parity check circuit 3.4 Input register 5.6 Input switching circuit 7... Input control circuit 8.9... Output switching circuit 10, 11... Transfer register 12... Output control (b) path 13 Byte switching control circuit 101, 102... Data bus 103-115 ...Signal line patent applicant Hisashi Inoro, agent for NEC Corporation, patent attorney

Claims (1)

[Claims] a plurality of transfer registers each for storing data in byte units; a plurality of output switching circuits for switching the contents of the plurality of transfer registers and sending them to the corresponding plurality of data buses; a plurality of input switching circuits for switching the contents of the plurality of data buses as inputs and outputting corresponding byte data; and a plurality of input switching circuits for individually storing the outputs of the plurality of input switching circuits. an input register, a plurality of parity check circuits for individually performing parity checks on the outputs of the plurality of input registers, and outputs for respectively controlling the plurality of output switching circuits during data transfer. a control circuit; an input control circuit for individually controlling the plurality of input switching circuits and the plurality of input registers during the data transfer; and when a parity error is detected in the parity check;
a byte switching control circuit for controlling the input control circuit and the output control circuit by performing a corresponding data transfer trial, and when the parity error is detected in one of the plurality of parity check circuits; , characterized in that the input switching circuit and the output switching circuit are simultaneously switched so that data can be retransferred without using the data bus on the side where the parity error has been detected. Data bus controller.