JPS59117225A - Face down bonding device - Google Patents
Face down bonding deviceInfo
- Publication number
- JPS59117225A JPS59117225A JP22632182A JP22632182A JPS59117225A JP S59117225 A JPS59117225 A JP S59117225A JP 22632182 A JP22632182 A JP 22632182A JP 22632182 A JP22632182 A JP 22632182A JP S59117225 A JPS59117225 A JP S59117225A
- Authority
- JP
- Japan
- Prior art keywords
- positioning
- mark
- picture
- lines
- automation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75753—Means for optical alignment, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はフェイスダウンボンダに関する。[Detailed description of the invention] The present invention relates to a face-down bonder.
半導体装置にお(・て、チップ(回路素子)の電極と外
部リードとの接続を図る構造の1つとして第1図で示す
ように、テップlの電極を盛り上げてバンプ電極2とし
、このバンプ電極2を直接配線基板3の配線層4に重ね
合せるようにして接続するいわゆるフェイスダウンボン
ディングが知られている。このボンディングにあたって
フェイスダウンボンダが用いられている。As shown in Fig. 1, one of the structures for connecting the electrodes of a chip (circuit element) and an external lead in a semiconductor device is to raise the electrode of the tip 1 to form a bump electrode 2. So-called face-down bonding is known in which the electrode 2 is connected directly to the wiring layer 4 of the wiring board 3 by overlapping it.A face-down bonder is used for this bonding.
このフェイスダウンボンダにあっては、基板パターンと
チップパターンの位置合せが必要となる。In this face-down bonder, it is necessary to align the substrate pattern and the chip pattern.
この場合、位置合せ機構としては、ハーフミラ−を用い
た光学系を利用する方法(図示せず)、また、第2図(
al、 (blで示すような、2つの工業用テレビカメ
ラ(ITV)を用いて画像処理を利用する方法がある。In this case, as the positioning mechanism, there is a method using an optical system using a half mirror (not shown), and a method using an optical system using a half mirror (not shown),
There is a method that uses image processing using two industrial television cameras (ITV), as shown in al and (bl).
すなわち、基板3をテーブル5上に載置するととも罠、
透明ガラヌ板6上にチップ1をそのバンプ電極部分を下
面圧して載置し、第1のITV7により基板3のパター
ンを、また第2のITV8によりテップ1のパターンを
それぞれ写し、画像処理により、第2図(b)のように
モニタテレビ10で両パターン12.13を目視認識す
る。That is, when the substrate 3 is placed on the table 5, the trap,
The chip 1 is placed on a transparent Galanu plate 6 with its bump electrode portion pressed downward, the pattern of the substrate 3 is copied by the first ITV 7, the pattern of the step 1 is copied by the second ITV 8, and by image processing, As shown in FIG. 2(b), both patterns 12 and 13 are visually recognized on the monitor television 10.
そして、チップlを下端に真空吸着保持する支持ツール
9の降下地点11の位置に、チップパターン13あるい
は、基板パターン12を位置(重ね)合せした後、支持
ツール9によって基板3にテップ1を重ね合せかつ熱を
利用してそれぞれの接続部の接続を図る。この時、チッ
プ1は、支持ツール9によってその上面を吸着保持され
る。また、位置合せ(アライメント)は支持ツール9あ
るいは、透明ガラス板6、およびテーブル5をXY方向
に移動させたり、回転させたりし1行なう。Then, after positioning (overlapping) the chip pattern 13 or the substrate pattern 12 at the position of the drop point 11 of the support tool 9 that holds the chip l at the lower end by vacuum suction, the support tool 9 overlaps the tip 1 on the substrate 3. Each connection section is connected using heat. At this time, the upper surface of the chip 1 is held by suction by the support tool 9. Further, alignment is performed by moving or rotating the support tool 9, the transparent glass plate 6, and the table 5 in the XY directions.
ところで、従来、この位置合せ手順としては、まず、第
3図ta+に示すように支持ツール9を移動させて透明
ガラス板6上に臨ませ、第2のITV8によって支持ツ
ール先端像11をモニタテレビ10の画面中央に写し出
す。その後テーブル5を移動制御して支持ツール先端像
11に、第1の1TV7によって同モニタテレビ10に
写し出される基板パターン12を重ね合せて位置合せす
る。By the way, conventionally, in this positioning procedure, the supporting tool 9 is first moved to face the transparent glass plate 6 as shown in FIG. Project it in the center of the screen of 10. Thereafter, the movement of the table 5 is controlled so that the support tool tip image 11 and the substrate pattern 12 projected on the monitor television 10 by the first TV 7 are superimposed and aligned.
つぎに第3図(blで示すように支持ツール9を移動さ
せた後基板パターン12と第2のITV8によって写し
出されるチップパターン13とを透明ガラス板6を移動
制御して、両パターンを重ね合せて位置合せする。Next, after moving the support tool 9 as shown in FIG. to align.
このように、従来は、基準となるパターンを順次かえて
位置合わせを行なうという方法がとられていた。しかし
、この方法では、一工程で少な(とも2回位置合せを行
なうことになり、作業の能率向上、自動化ケ図るうえで
太ぎた障害となっていた。In this way, conventionally, a method has been used in which the reference pattern is sequentially changed to perform alignment. However, with this method, alignment is performed less than once (twice) in one process, which poses a serious obstacle to improving work efficiency and automating the process.
したがって、本発明の目的は、作業の能率向上を図るこ
とができるとともに、自動化にも適する構造の7エイス
ダウンポンダを提供することにある。Therefore, an object of the present invention is to provide a 7-eighth downponder having a structure that can improve work efficiency and is also suitable for automation.
このような目的を達成する為に、本発明は、目視認識す
る像または画面上に、基準となるマークを配し、この基
準マークにそれぞれの接続物、被接続物画像を1ね合せ
る構造の位置合せ機構を有するボンダとするものであっ
て以下実施例により本発明を説明する。In order to achieve such an object, the present invention has a structure in which a reference mark is arranged on a visually recognized image or screen, and each connected object and connected object image is aligned with this reference mark. The present invention, which is a bonder having an alignment mechanism, will be explained below with reference to Examples.
第4図は、本発明の一実施例による7エイスダウンボン
ダの位置合せ機構を示す。同図に示すように、モニタテ
レビ10の画面上に、それぞれ相互に平行となる縦2本
横2本の電子ライン14を引き、画面中央に四角枠から
なるマークを設ける。FIG. 4 shows an alignment mechanism for a 7-eighth down bonder according to one embodiment of the present invention. As shown in the figure, two parallel electronic lines 14 and two horizontal lines 14 are drawn on the screen of a monitor television 10, and a mark consisting of a rectangular frame is provided at the center of the screen.
この四角枠のマークは、支持ツール先端像の位置に設定
し基準マーク15とするっこの位置合せ機構における、
位置合せは、基準マーク15に基板パターン12および
チップパターン13を移動させ、両パターンを重ね合せ
るだけで行なえる。In this alignment mechanism, this square frame mark is set at the position of the support tool tip image and serves as the reference mark 15.
Alignment can be performed simply by moving the substrate pattern 12 and chip pattern 13 to the reference mark 15 and overlapping both patterns.
このような実施例によれば、位置合せ時における支持ツ
ールの移動という動作(操作)が不用となり、1回で、
位置合せ作業を完了することができる。したがって、作
業性が向上するとともに、操作が簡素であることから自
動化も可能である。According to such an embodiment, the operation (operation) of moving the support tool during alignment is unnecessary, and the operation can be performed in one time.
The alignment work can be completed. Therefore, work efficiency is improved, and since the operation is simple, automation is also possible.
なお、本発明は、前記実施例に限定されない。例えば、
接眼ミクロを基準マークとしてもよい。また、基準マー
クは他の形状でもよい。さらに、接続物および被接続物
は基板、チップ以外のものでよいことは勿論である。Note that the present invention is not limited to the above embodiments. for example,
The eyepiece micro may be used as a reference mark. Further, the reference mark may have other shapes. Furthermore, it goes without saying that the connecting object and the connected object may be other than substrates and chips.
以上のように本発明によれば、対向する対象物の位置合
せが1回ですみ、作業能率の向上を図ることができる。As described above, according to the present invention, opposing objects only need to be aligned once, and work efficiency can be improved.
また自動化が容易になる。It also makes automation easier.
第1図はフェイスダウン構造を示す正面図、第2図(a
)、 (b)は従来のフェイスダウンボンダにおける位
置合せ機構を示す概略図、第3図(a)、 (blは、
従来の位置合せ方法を示す概略図、第4図は、本発明の
一実施例によるフェイスダウンボンダの位置合せ方法を
示す概略図。
1・・・チップ、2・・・バンプ電極、3・・・基板、
4・・・配線層、5・・・テーブル、6・・・透明ガラ
ス、7・・・第1のI T V (1)、8・・・第2
のI T V (2)、9・・・支持ツール、10・・
・モニタテレビ、11・・・支持ツール先端像、13・
・・チップパターン、12・・・基板ノくターン、14
・・・電子ライン、15・・・基準マーク。Figure 1 is a front view showing the face-down structure, Figure 2 (a
), (b) are schematic diagrams showing the alignment mechanism in a conventional face-down bonder, and FIGS. 3(a) and (bl are,
FIG. 4 is a schematic diagram showing a conventional alignment method. FIG. 4 is a schematic diagram showing a face-down bonder alignment method according to an embodiment of the present invention. 1... Chip, 2... Bump electrode, 3... Substrate,
4... Wiring layer, 5... Table, 6... Transparent glass, 7... First ITV (1), 8... Second
ITV (2), 9...Support tool, 10...
・Monitor TV, 11...Support tool tip image, 13・
...Chip pattern, 12...Substrate turn, 14
...Electronic line, 15...Reference mark.
Claims (1)
て接続物と被接続物の位置合せを行なった後、両パター
ンを重ね合せ、その後接続物と被接続物との接続を図る
フェイスダウンボンダにおいて、前記両パターンが同時
に認識できる画面内に基準マークを設置し、この基準マ
ークにそれぞれ両パターンを位置合せすることによって
接続物と被接続物との位置合せを行なうことを特徴とす
るフェイスダウンボンダ。Face-down method that simultaneously recognizes the patterns of the connecting object and the connected object that face each other, aligns the connecting object and the connected object, then superimposes both patterns, and then connects the connecting object and the connected object. In the bonder, a reference mark is installed in a screen where both the patterns can be recognized at the same time, and the bonding object and the object to be connected are aligned by aligning both patterns with the reference mark. Down bonder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22632182A JPS59117225A (en) | 1982-12-24 | 1982-12-24 | Face down bonding device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22632182A JPS59117225A (en) | 1982-12-24 | 1982-12-24 | Face down bonding device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59117225A true JPS59117225A (en) | 1984-07-06 |
JPH0380346B2 JPH0380346B2 (en) | 1991-12-24 |
Family
ID=16843355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22632182A Granted JPS59117225A (en) | 1982-12-24 | 1982-12-24 | Face down bonding device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59117225A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007503111A (en) * | 2003-08-21 | 2007-02-15 | ヘッセ・ウント・クナイプス・ゲーエムベーハー | Adjusting the bonding head element with the aid of a camera |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS574131A (en) * | 1980-06-10 | 1982-01-09 | Nippon Abionikusu Kk | Device for mounting of semiconductor chips |
-
1982
- 1982-12-24 JP JP22632182A patent/JPS59117225A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS574131A (en) * | 1980-06-10 | 1982-01-09 | Nippon Abionikusu Kk | Device for mounting of semiconductor chips |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007503111A (en) * | 2003-08-21 | 2007-02-15 | ヘッセ・ウント・クナイプス・ゲーエムベーハー | Adjusting the bonding head element with the aid of a camera |
JP2011040780A (en) * | 2003-08-21 | 2011-02-24 | Hesse & Knipps Gmbh | Method of aligning bonding head elements and ultrasonic wave bonder |
JP4685773B2 (en) * | 2003-08-21 | 2011-05-18 | ヘッセ・ウント・クナイプス・ゲーエムベーハー | Setting operation method of bonding head and ultrasonic bonder |
Also Published As
Publication number | Publication date |
---|---|
JPH0380346B2 (en) | 1991-12-24 |
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