JPH03160738A - Facedown chip and its manufacture and its mounting board - Google Patents

Facedown chip and its manufacture and its mounting board

Info

Publication number
JPH03160738A
JPH03160738A JP1300306A JP30030689A JPH03160738A JP H03160738 A JPH03160738 A JP H03160738A JP 1300306 A JP1300306 A JP 1300306A JP 30030689 A JP30030689 A JP 30030689A JP H03160738 A JPH03160738 A JP H03160738A
Authority
JP
Japan
Prior art keywords
chip
wafer
mounting
pads
positioning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1300306A
Other languages
Japanese (ja)
Inventor
Kenichi Kuroiwa
黒岩　健一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1300306A priority Critical patent/JPH03160738A/en
Publication of JPH03160738A publication Critical patent/JPH03160738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To facilite the positioning of a chip by forming a mark for positioning a chip in the regular relative relation to a pad, on the rear of a chip where a desired element, a circuit, and a pad for mounting are formed on the surface. CONSTITUTION:In a chip 11 where a desired element, a circuit, and a pad for connection are formed on the surface (upside of the figure), chip positioning marks 13 consisting of two lines 13a and 13b crossing at right angles are made on the rear (downside of the figure). Such marks 13 are made in regular relation to the pads 12 arranged in two rows each comprising plural pieces, that is, the line 13a crosses the lineup direction of plural pieces of pads 12, while the line 13b is arrange in parallel with the lineup direction of plural pieces of pads 12. Hereby, if becomes possible to set the mounting position by making use of positioning marks formed at the rear, and the mounting on an opaque board become easier than a conventional one.

Description

【発明の詳細な説明】 〔概要〕 フェースダウンチップと、そのチップをウェーハより製
造する方法および、そのチップを実装する基板の横威に
関し、 光学的に不透明である基板に、フェースダウンボンディ
ングにてチップを搭載する技術の生産性向上を目的とし
、 表面に所望の素子と回路および実装用パ，ンドが形成さ
れたチップの裏面には、該パッドに対して一定の相対関
係で該チンプの位置決めマークが形成されてなること、 チップに分割する前のウェーハの裏面の各チップ領域に
は、該チップ領域の表面に形成された実装用パッドに対
して一定の相対関係である位置決めマークを形成し、 上下方向に対向する一対の位置センサの一方に対し他方
の位置センサの位置設定を行い、該一対の位置センサの
対向間には表面が上を向く該ウェーハを前後方向．左右
方向へ移動および回動可能に支持し、 下方の該位置センサ．咳ウェーハの裏面に形成した該位
置決めマークを用いて該ウェーハのＸＹ軸を設定し、 上方の該位置センサを用いて設定した咳ウエー八の表面
の所定箇所には該Ｘ−Ｙ軸に対応するプロセスマークを
形成し、 該プロセスマークを用いて前記素子と回路および実装用
パッドを形成したのち、 該ウェーハを複数のチンブに分割すること、前記チップ
を実装する基板の表面には、前記パッドに対向する電極
と、前記チップの裏面に形成された位置決めマークの延
長線に一致するパターンが形成されてなることを特徴と
し構威する。[Detailed Description of the Invention] [Summary] Regarding a face-down chip, a method for manufacturing the chip from a wafer, and the effectiveness of the substrate on which the chip is mounted, the present invention relates to a face-down chip, a method for manufacturing the chip from a wafer, and the effectiveness of the substrate on which the chip is mounted. With the aim of improving the productivity of chip mounting technology, on the back side of the chip, on which the desired elements, circuits, and mounting pads are formed, there is a device that positions the chimp in a certain relative relationship to the pad. Marks are formed on each chip area on the back side of the wafer before it is divided into chips. , The position of one of the pair of position sensors facing each other in the vertical direction is set relative to the other position sensor, and the wafer with its surface facing upward is placed between the pair of position sensors in the front-back direction. The position sensor is supported so that it can be moved and rotated in the left and right directions, and the position sensor is located below. The XY axes of the wafer are set using the positioning mark formed on the back surface of the cough wafer, and a predetermined location on the surface of the cough wafer set using the position sensor above corresponds to the XY axis. After forming process marks and forming the elements, circuits, and mounting pads using the process marks, dividing the wafer into a plurality of chips; The device is characterized in that a pattern is formed that corresponds to the extension line of the positioning mark formed on the back surface of the chip and the opposing electrodes.

〔産業上の利用分野〕[Industrial application field]

本発明は、フェースダウンボンデイングにて実装される
半導体装置等のチップとその製造方法および、そのチッ
プを実装する基板に関する。The present invention relates to a chip such as a semiconductor device mounted by face-down bonding, a manufacturing method thereof, and a substrate on which the chip is mounted.

〔従来の技術〕[Conventional technology]

近来、チンプオンボード（ＣＯＢ　ＨＣｈｉｐ　ｏｎＢ
ｏａｒｄ）方式によるチップ実装方法が提案されるよう
になった。一般に、バンプを使用したフェースダウンボ
ンディングであるＣＯＢ方式は、下面にパッドが形成さ
れたチップとチップ実装基板との位置合わせのため、該
基板にガラス等の透明基板を使用したチップオンガラス
（ＣＯＧ　；　Ｃｈｉｐ　ｏｎＧｌａｓｓ）であり、該
位置合わせは基板を透して行われている。Recently, COB HChip onB
A chip mounting method using the orard method has been proposed. In general, the COB method, which is face-down bonding using bumps, uses a chip-on-glass (COG) method, which uses a transparent substrate such as glass as the substrate, in order to align the chip with pads formed on the bottom surface and the chip mounting board. ; Chip on Glass), and the alignment is performed through the substrate.

他方、不透明基板にフェースダウンボンディングにてチ
ップを搭載することが、一部の半導体装置の製造に用い
られている。On the other hand, mounting a chip on an opaque substrate by face-down bonding is used in the manufacture of some semiconductor devices.

第５図はＣＯＢ方式で実装されたチップの側面図であり
、チップ１の表面（図示下面）に所望の素子と回路およ
び実装用パッドを形成し、チップ搭載基板２の上面には
該パッドが接続される電極を形成し、該パッドと電極と
はバンプ３にて電気的に費接続する。FIG. 5 is a side view of a chip mounted using the COB method. Desired elements, circuits, and mounting pads are formed on the surface of the chip 1 (bottom surface in the figure), and the pads are formed on the top surface of the chip mounting board 2. An electrode to be connected is formed, and the pad and the electrode are electrically connected by bumps 3.

チップ１と基板２とを接着する絶縁性接着剤４は、バン
プ３の周囲を固める。The insulating adhesive 4 that adheres the chip 1 and the substrate 2 hardens the periphery of the bump 3.

第６図は不透明基板にフェースダウンチップを搭載する
従来方法の説明図である。FIG. 6 is an explanatory diagram of a conventional method for mounting a face-down chip on an opaque substrate.

第６図において、基板２に対する位置決めマーク（図示
せず）が表面に形成されたチソプ１は、チップ１に対す
る位置決めマーク（図示せず）が上面に形成された基板
２の上方に支持され、その対向間に挿入したプリズム５
によって光学的に基板２とチップ１との位置関係を設定
したのち、プリズム５を取り除き、チップｌを基板２に
向けて移動し搭載する方法であった。In FIG. 6, a chip 1 having a positioning mark (not shown) formed on its surface with respect to the substrate 2 is supported above a substrate 2 having a positioning mark (not shown) formed on its top surface with respect to the chip 1. Prism 5 inserted between opposite sides
After optically setting the positional relationship between the substrate 2 and the chip 1, the prism 5 is removed, and the chip 1 is moved toward the substrate 2 and mounted thereon.

（発明が解決しようとする課題） 以上説明したように、不透明基板にチップをフェースダ
ウンボンディングする従来方法は、チップの位置決めに
プリズム等を必要とするため、チップの位置決めが面倒
かつ難しく、非量産的であるという．問題点があった。(Problems to be Solved by the Invention) As explained above, the conventional method of face-down bonding of chips to an opaque substrate requires a prism etc. for chip positioning, which makes chip positioning troublesome and difficult, making it difficult to mass-produce. It is said that it is accurate. There was a problem.

本発明の目的はかかる問題点を除去し、ＣＯＢ方式によ
るチップ実装技術を広く活用することである。An object of the present invention is to eliminate such problems and to widely utilize COB-based chip mounting technology.

〔課題を解決するための手段〕[Means to solve the problem]

本発明によるフェースダウンチップはその実施例を示す
第工図によれば、表面に所望の素子と回路および実装用
バッド１２が形成されたチップ１１の裏面には、パッド
１２に対して一定の相対関係でチップｌ１の位置決めマ
ーク１３が形成されてなることを特徴とし、 本発明によるフェースダウンチップの製造方法はその実
施例を示す第３図によれば、チップｌ１に分割する前の
ウェーハ２２の裏面の各チップ領域には、該チップ領域
の表面に形成された実装用パッドに対して一定の相対関
係である位置決めマーク２５と２６を形成し、 上下方向に対向する一対の位置センサ２７　，　２Ｂの
一方例えば２７に対し他方の位置センサ２８の位置設定
を行い、 一対の位置センサ２７，２Ｂの対向間には表面が上を向
くウェーハ２２を前後方向，左右方向へ移動および回動
可能に支持し、 下方の位置センサ２８，ウェーハ２２の裏面に形成した
位置決めマーク線２５と２６を用いてウェーハ２２のＸ
−Ｙ軸を設定し、 上方の位置センサ２７を用いて設定したウェーハ２２の
表面の所定箇所には該Ｘ−Ｙ軸に対応するプロセスマー
ク３２を形成し、 プロセスマーク３２を用いて前記素子と回路および実装
用バッド１２を形成したのち、 ウェーハ２２を複数のチップ１１に分割することを特徴
とし、 本発明によるフェースダウンチップ実装基板はその実施
例を示す第４図によれば、チップ１１を実装する基板３
３の表面には、バッド１２に対向する電極と、チップ１
１の裏面に形成された位置決めマーク１３の延長線に一
致するパターン３４．３５が形成されてなることを特徴
とする。According to a drawing showing an embodiment of the face-down chip according to the present invention, the back side of the chip 11 has desired elements, circuits, and mounting pads 12 formed on the front side, and has a certain relative position with respect to the pads 12. According to FIG. 3, which shows an embodiment of the face-down chip manufacturing method according to the present invention, a positioning mark 13 is formed for the chip l1. On each chip area on the back side, positioning marks 25 and 26 are formed in a fixed relative relationship with the mounting pad formed on the surface of the chip area, and a pair of position sensors 27 and 2B facing each other in the vertical direction are formed. For example, the position of the other position sensor 28 is set relative to one of the position sensors 27, and the wafer 22 with its surface facing upward is supported between the pair of position sensors 27 and 2B so as to be movable and rotatable in the front-back and left-right directions. Then, using the lower position sensor 28 and the positioning mark lines 25 and 26 formed on the back surface of the wafer 22, the
A process mark 32 corresponding to the X-Y axis is formed at a predetermined location on the surface of the wafer 22 set using the upper position sensor 27, and the process mark 32 is used to connect the elements. After forming the circuit and the mounting pad 12, the wafer 22 is divided into a plurality of chips 11. According to FIG. 4 showing an embodiment of the face-down chip mounting board according to the present invention, the chips 11 are Board 3 to be mounted
The surface of the chip 3 has an electrode facing the pad 12 and a chip 1.
It is characterized in that patterns 34 and 35 are formed that correspond to the extension line of the positioning mark 13 formed on the back surface of 1.

〔作用〕[Effect]

上記手段によるフェースダウンチップは、裏面に形成し
た位置決めマークを利用し実装位置が設定可能となり、
不透明基板への実装が従来のものより著しく容易となり
、 上記手段にて一対の位置センサを利用したフェースダウ
ンチップの製造方法は、該チップの量産が容易とし、 上記手段によるフェースダウンチップ実装基板は、前記
チップの実装を容易ならしめるようになる。With the face-down chip manufactured by the above method, the mounting position can be set using the positioning mark formed on the back surface.
Mounting on an opaque substrate is significantly easier than conventional methods, and the face-down chip manufacturing method using a pair of position sensors by the above means facilitates mass production of the chips. , which facilitates the mounting of the chip.

〔実施例〕〔Example〕

以下に、図面を用いて本発明方法の実施例を説明する。 Examples of the method of the present invention will be described below with reference to the drawings.

第１図は本発明の実施例によるチップの概略を示す斜視
図、第２図は本発明の他の実施例によりチップの裏面に
形成した位置決めマークの代表例の平面図である。FIG. 1 is a perspective view schematically showing a chip according to an embodiment of the present invention, and FIG. 2 is a plan view of a typical example of positioning marks formed on the back surface of a chip according to another embodiment of the present invention.

第１図において、表面（図の上面）に所望の素子と回路
および接続用のバッド１２を形成したチップ１１は、裏
面（図の下面）に直交する２本の線１３ａ，　１３ｂに
てなるチップ位置決めマークｌ３を形成してなる。In FIG. 1, a chip 11 on which desired elements, circuits, and connection pads 12 are formed on the front surface (top surface in the figure) is formed by two lines 13a and 13b orthogonal to the back surface (bottom surface in the figure). A positioning mark l3 is formed.

かかるマーク１３は、複数個ずつの２列に形成されたパ
ッド１２に対して一定の相対関係、即ち、線１３ａは複
数個のパッド１２の整列方向に直交する反面、線１３ｂ
は複数個のパッド１２の整列方向と平行に形成されたも
のである。The marks 13 have a certain relative relationship with the pads 12 formed in two rows of pads 12, that is, the line 13a is perpendicular to the alignment direction of the pads 12, while the line 13b is perpendicular to the alignment direction of the pads 12.
are formed parallel to the alignment direction of the plurality of pads 12.

第２図（イ）において、チップ１４の裏面に形成し位置
決めマーク１３に相当する位置決めマークｌ５は、４本
の線１５ａ，　１５ｂ，　１５ｃ，　１５ｄにて構威し
たものであり、線１５ａと１５ｂ．線１５ｃと１５ｄは
それぞれが平行す反面、線１５ａと１５ｂは線１５ｃと
１５ｄに対し直交する。In FIG. 2(a), the positioning mark l5 formed on the back surface of the chip 14 and corresponding to the positioning mark 13 is composed of four lines 15a, 15b, 15c, and 15d, and the lines 15a and 15b ．． Lines 15c and 15d are parallel to each other, while lines 15a and 15b are perpendicular to lines 15c and 15d.

第２図（０）において、チップ１６の裏面に形成し位置
決めマークｌ３に相当する位置決めマーク１７は、３本
の線１７ａ，　１７ｂ，　１７ｃにて構或したものであ
り、線１７ａと１７ｂが平行する反面、線１７ｃは線１
７ａと１７ｂに直交する。In FIG. 2(0), the positioning mark 17 formed on the back surface of the chip 16 and corresponding to the positioning mark l3 is composed of three lines 17a, 17b, and 17c, and the lines 17a and 17b are parallel to each other. On the other hand, line 17c is line 1
It is perpendicular to 7a and 17b.

第２図（ハ）において、チップＩ８の裏面に形成し位置
決めマーク１３に相当する一対の位置決めマークｌ９は
、２本の短い線１９ａと１９ｂが直交する十字形であり
、チップ裏面の対称コーナ部に形成させたものである。In FIG. 2(c), a pair of positioning marks l9 formed on the back surface of the chip I8 and corresponding to the positioning marks 13 are in the shape of a cross in which two short lines 19a and 19b intersect at right angles, and are located at symmetrical corners of the back surface of the chip. It was formed by

第２図（二）において、チップ２０の裏面に形成し位置
決めマーク１３に相当する一対の位置決めマーク２１は
角形であり、チップ裏面の対称コーナ部に形成させたも
のである。In FIG. 2(2), a pair of positioning marks 21 formed on the back surface of the chip 20 and corresponding to the positioning marks 13 are rectangular, and are formed at symmetrical corners of the back surface of the chip.

第３図は本発明の実施例により第１図に示すチップｌ１
の主要製造工程の説明図である。FIG. 3 shows a chip l1 shown in FIG. 1 according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of the main manufacturing process.

第３図（イ）において、縦方向の一点鎖ｔａ２３および
横方向の一点鎖線２４に沿って分断することで複数のチ
ップ１１に分割されるウェーハ２２の裏面には各チップ
領域を貫通する縦線（位置決めマークとなる一方の線）
２５と横線（位置決めマークとなる他方の線）２６を形
成する。In FIG. 3(a), the back surface of the wafer 22, which is divided into a plurality of chips 11 by dividing along the vertical dot chain ta23 and the horizontal dot chain line 24, has a vertical line penetrating each chip area. (One line serves as a positioning mark)
25 and a horizontal line (the other line serving as a positioning mark) 26.

各チップ領域の表面には同一素子と回路および実装用バ
ンドを形成し、そのパッドに対して一定の相対関係であ
る縦ｖＡ２５と横ｖＡ２６は、後述する如くウェーハ２
２を分割したとき、ウェーハ２２と共に分割され位置決
めマーク１３になる。The same elements, circuits, and mounting bands are formed on the surface of each chip area, and the vertical vA25 and horizontal vA26, which have a certain relative relationship with the pads, are wafer 2 as described later.
When the wafer 2 is divided, it is divided together with the wafer 22 and becomes the positioning mark 13.

他方、第３図（［１）に示す如く上下方向に対向する一
対の位置センサ２７と２８、例えば発光素子と受光素子
を内蔵した反射型位置センサ２７と２８は、センサ２７
の発光素子が発する光２９をセンサ２８の受光素子が受
けると共に、センサ２８の発光素子が発する光３０をセ
ンサ２７の受光素子が受けることによって、例えばセン
サ２７に対しセンサ２８の位置設定が行われる． 次いで、第３図（ハ）に示す如く一対のセンサ２７と２
８の対向間に設けられ左右方向．前後方向の移動および
回動可能な透明基板３１の上にウェーハ２２を固定する
。On the other hand, as shown in FIG. 3 ([1), a pair of position sensors 27 and 28 facing each other in the vertical direction, for example reflective position sensors 27 and 28 having a built-in light emitting element and a light receiving element, are connected to the sensor 27.
The light receiving element of the sensor 28 receives the light 29 emitted by the light emitting element of the sensor 28, and the light receiving element of the sensor 27 receives the light 30 emitted by the light emitting element of the sensor 28, thereby setting the position of the sensor 28 relative to the sensor 27, for example. ．． Next, as shown in FIG. 3(c), a pair of sensors 27 and 2
8 is installed in the left and right direction. The wafer 22 is fixed on a transparent substrate 31 that can be moved and rotated in the front and rear directions.

かかるウェーハ２２は所望の素子と回路およびパッドの
形成される表面が上向きであり、ウェーハ２２の裏面に
形成された線（Ｙ軸）２５と線（Ｘ軸）２６は、センサ
２８および透明基板３１の回動操作によって、透明基板
３１の左右，前後の移動方向と一致させる． 次いで、第３図（二）に示す如くセンサ２７を用いて設
定したウェーハ２２の表面の一対の所定箇所には、所定
箇所には線２５．２６即ちＸ軸とＹ軸に対応する十字形
プロセスマーク３２を形成し、そのプロセスマーク３２
を用いて各チップ領域の表面に所望の素子と回路および
パッド（１２）を形成せしめたのち、一点鎖線２３およ
び２４にそってウェーハ２２を分割すると、裏面には線
２５．２６が分断されマークｌ３の形成されたチップ１
１が完戒する。The surface of the wafer 22 on which desired elements, circuits, and pads are formed faces upward, and a line (Y axis) 25 and a line (X axis) 26 formed on the back surface of the wafer 22 are aligned with the sensor 28 and the transparent substrate 31. By rotating the transparent substrate 31, the direction of movement of the transparent substrate 31 is made to match the left and right and front and rear movement directions. Next, as shown in FIG. 3(2), at a pair of predetermined locations on the surface of the wafer 22 set using the sensor 27, lines 25 and 26, that is, cross-shaped processes corresponding to the X and Y axes, are placed at the predetermined locations. forming a mark 32 and forming the process mark 32;
After forming desired elements, circuits, and pads (12) on the front surface of each chip area using the wafer 22, the wafer 22 is divided along the dashed lines 23 and 24, and marks 25 and 26 are cut on the back side. Chip 1 with l3 formed
1 is fully admonished.

第４図は本発明の実施例によるチップ実装基板の説明図
である。FIG. 4 is an explanatory diagram of a chip mounting board according to an embodiment of the present invention.

第４図において、チップ１１を搭載する基板３３の表面
には、チップ１１を正しい位置に搭載したとき、位置決
めマーク１３を構戒する線１３ａと１３ｂの延長線に一
致するパターン３４　．　３５を形成してなる．従って
、基板３３の正しい位置にチップ１ｌを搭載するには、
線１３ａ．１３ｂがパターン３４．３５と一致させれば
よいことになる。In FIG. 4, the surface of the substrate 33 on which the chip 11 is mounted has a pattern 34. 35 is formed. Therefore, in order to mount the chip 1l in the correct position on the board 33,
Line 13a. 13b should match patterns 34 and 35.

なお、第４図においてパターン３４．３５は、チップ１
１の位置決め専用に形成してよいが、基板３３が必要と
する導体パターン等を利用することができる。Note that patterns 34 and 35 in FIG.
Although it may be formed exclusively for the positioning of the substrate 33, it is also possible to use a conductive pattern or the like required by the substrate 33.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によるフェースダウンチッ
プは、裏面の位置決めマークを利用し実装位置の設定が
可能となって不透明基板への実装が従来のものより著し
く容易となり、 本発明により一対の位置センサを利用したフェースダウ
ンチップの製造方法は、裏面に位置決めマークの形成さ
れたチップの量産を容易とし、さらに、本発明によるフ
ェースダウンチップの実装基板は、チップの実装を容易
ならしめる効果を有する。As explained above, the face-down chip according to the present invention makes it possible to set the mounting position using the positioning mark on the back side, making mounting on an opaque substrate much easier than with conventional ones. The face-down chip manufacturing method using a sensor facilitates the mass production of chips with positioning marks formed on the back surface, and the face-down chip mounting board according to the present invention has the effect of facilitating chip mounting. .

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例によるチップの斜視図、第２図
は本発明の他の実施例による位置決めマークの代表例、 第３図は本発明の実施例により第１図に示すチップの主
要製造工程の説明図、 第４図は本発明の実施例によるチップ実装基板の説明図
、 第５図はＣＯＢ方式で実装されたチップの側面図、 第６図は不透明基板にフェースダウンチップを搭載する
従来方法の説明図、 である。 図中において、 １１，１４，１６，１８．２０はチップ、１２はパッド
、 １３，　１５．　１７．　１９．２１はチップの位置決
めマーク、２２はウェーハ、 ２５は縦線（位置決めマークとなる一方の線）、２６は
横線（位置決めマークとなる他方の線）、２７．２８は
位置センサ、 ３２はチップ表面のプロセスマーク、 ３３はチップ搭載基板、 ３４．３５は基板表面のパターン、 水発り１７１’）１世の実袴イ列１−ようイ立４【決ハ
マフの１Ａ表例 第 ２ 図 （ハノ （ニノ 菖１２１ ３４ハ９ターン 水発明の寅斃例１：ｔう＋，７７゛実旋基損の説明図第
　４　図 ＣＯＢ方３テＦ：Ｆ’＝ａ７：＋　．．ｊ　７Ｍｌ１５
（Ｓ２１第５爛 下ｉ明基＠．１：フ１ 従来万去の浚明礫 スタフ′／＋・ノアと塔東Ｔる 第 ６ 闇1 is a perspective view of a chip according to an embodiment of the present invention, FIG. 2 is a representative example of a positioning mark according to another embodiment of the present invention, and FIG. 3 is a perspective view of a chip shown in FIG. 1 according to an embodiment of the present invention. An explanatory diagram of the main manufacturing process. Figure 4 is an explanatory diagram of a chip mounting board according to an embodiment of the present invention. Figure 5 is a side view of a chip mounted using the COB method. Figure 6 is a diagram showing a face-down chip mounted on an opaque substrate. This is an explanatory diagram of the conventional method of mounting. In the figure, 11, 14, 16, 18. 20 are chips, 12 are pads, 13, 15. 17. 19.21 is the chip positioning mark, 22 is the wafer, 25 is the vertical line (one line that will be the positioning mark), 26 is the horizontal line (the other line that will be the positioning mark), 27.28 is the position sensor, 32 is the chip Process mark on the surface, 33 is the chip mounting board, 34.35 is the pattern on the board surface, Mizuhari 171') 1st generation's actual hakama A row 1 - Yoi iri 4 [Katsuhamafu's 1A table example Fig. 2 ( Hano (Nino Iris 121 34ha 9 turn water invention example 1: t +, 77゛Explanatory diagram of actual rotary base loss Figure 4 COB direction 3teF:F'=a7:+ ..j 7Ml15
(S21 5th Erosion i Akimoto @.1:F1 Conventional Banryō no Kakereki Stuff'/+・Noah and Toto Tru 6th Darkness

Claims (1)

【特許請求の範囲】 〔１〕表面に所望の素子と回路および実装用パッド（１
２）が形成されたチップ（１１、１４、１６、１８、２
０）の裏面には、該パッド（１２）に対して一定の相対
関係で該チップ（１１、１４、１６、１８、２０）の位
置決めマーク（１３、１５、１７、１９、２１）が形成
されてなることを特徴とするフェースダウンチップ。 〔２〕チップ（１１）に分割する前のウェーハ（２２）
の裏面の各チップ領域には、該チップ領域の表面に形成
された実装用パッドに対して一定の相対関係である位置
決めマーク（２５と２６）を形成し、上下方向に対向す
る一対の位置センサ（２７、２８）の一方（２７または
２８）に対し他方の位置センサ（２８または２７）の位
置設定を行い、 該一対の位置センサ（２７、２８）の対向間には表面が
上を向く該ウェーハ（２２）を前後方向、左右方向へ移
動および回動可能に支持し、 下方の該位置センサ（２８）、該ウェーハ（２２）の裏
面に形成した該位置決めマーク（１３）を用いて該ウェ
ーハ（２２）のＸ−Ｙ軸を設定し、 上方の該位置センサ（２７）を用いて設定した該ウェー
ハ（２２）の表面の所定箇所には該Ｘ−Ｙ軸に対応する
プロセスマーク（３２）を形成し、 該プロセスマーク（３２）を用いて前記素子と回路およ
び実装用パッド（１２）を形成したのち、該ウェーハ（
２２）を複数のチップ（１１）に分割することを特徴と
するフェースダウンチップの製造方法。 〔３〕請求項１に記載の前記フェースダウンチップ（１
１、１４、１６、１８、２０）を実装する基板（３３）
の表面には、前記パッド（１２）に対向する電極と、該
チップ（１１、１４、１６、１８、２０）の裏面に形成
された位置決めマーク（１３、１５、１７、１９、２１
）の延長線に一致するパターン（３４、３５）が形成さ
れてなることを特徴とするフェースダウンチップ実装基
板。[Claims] [1] Desired elements and circuits and mounting pads (1) on the surface
2) formed chips (11, 14, 16, 18, 2)
Positioning marks (13, 15, 17, 19, 21) for the chips (11, 14, 16, 18, 20) are formed on the back surface of the chip (11, 14, 16, 18, 20) in a certain relative relationship to the pad (12). A face-down tip that features a [2] Wafer (22) before being divided into chips (11)
Positioning marks (25 and 26) are formed on each chip area on the back surface of the chip area in a fixed relative relationship with the mounting pad formed on the surface of the chip area, and a pair of position sensors facing each other in the vertical direction are formed. The position of the other position sensor (28 or 27) is set relative to one (27 or 28) of the pair of position sensors (27, 28), and between the pair of position sensors (27, 28) there is a The wafer (22) is supported so as to be movable and rotatable in the front-rear direction and left-right direction, and the wafer (22) is moved using the position sensor (28) located below and the positioning mark (13) formed on the back surface of the wafer (22). (22), and a process mark (32) corresponding to the X-Y axis is placed at a predetermined location on the surface of the wafer (22) set using the upper position sensor (27). After forming the elements, circuits, and mounting pads (12) using the process marks (32), the wafer (
22) into a plurality of chips (11). [3] The face-down chip (1
1, 14, 16, 18, 20)) (33)
On the surface thereof, there are electrodes facing the pads (12) and positioning marks (13, 15, 17, 19, 21) formed on the back surface of the chips (11, 14, 16, 18, 20).
1. A face-down chip mounting board characterized in that a pattern (34, 35) is formed that corresponds to an extension line of ).
JP1300306A 1989-11-17 1989-11-17 Facedown chip and its manufacture and its mounting board Pending JPH03160738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1300306A JPH03160738A (en) 1989-11-17 1989-11-17 Facedown chip and its manufacture and its mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1300306A JPH03160738A (en) 1989-11-17 1989-11-17 Facedown chip and its manufacture and its mounting board

Publications (1)

Publication Number Publication Date
JPH03160738A true JPH03160738A (en) 1991-07-10

Family

ID=17883190

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1300306A Pending JPH03160738A (en) 1989-11-17 1989-11-17 Facedown chip and its manufacture and its mounting board

Country Status (1)

Country Link
JP (1) JPH03160738A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0587949U (en) * 1992-04-24 1993-11-26 セイコー電子工業株式会社 Semiconductor chip
JP2007300052A (en) * 2006-04-28 2007-11-15 Chukaminkoku Taiwan Hakumaku Denshotai Ekisho Keijiki Sangyo Kyokai Flip-chip packaging part, and manufacturing method
JP2011191390A (en) * 2010-03-12 2011-09-29 Dainippon Printing Co Ltd Display device and method for manufacturing display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0587949U (en) * 1992-04-24 1993-11-26 セイコー電子工業株式会社 Semiconductor chip
JP2007300052A (en) * 2006-04-28 2007-11-15 Chukaminkoku Taiwan Hakumaku Denshotai Ekisho Keijiki Sangyo Kyokai Flip-chip packaging part, and manufacturing method
JP2011191390A (en) * 2010-03-12 2011-09-29 Dainippon Printing Co Ltd Display device and method for manufacturing display device

Similar Documents

Publication Publication Date Title
JPS61111561A (en) Semiconductor device
US5393696A (en) Method for forming multilayer indium bump contacts
KR100881183B1 (en) Semiconductor chip having a different height bump and semiconductor package including the same
US6278193B1 (en) Optical sensing method to place flip chips
US6319750B1 (en) Layout method for thin and fine ball grid array package substrate with plating bus
KR100589530B1 (en) Electronic component device, method for manufacture of same, and aggregated circuit board
KR100924552B1 (en) Substrate for semiconductor package and semiconductor package having the same
JPH03160738A (en) Facedown chip and its manufacture and its mounting board
JPS59220947A (en) Manufacture of semiconductor device
JPH11260768A (en) Semiconductor device and its manufacture
KR20000010954A (en) Method for manufacturing semiconductor apparatus, and film carrier tape
JP2001237346A (en) Method of manufacturing semiconductor device mounting substrate and semiconductor device
JPH0612614Y2 (en) Circuit board unit
JPS6343392A (en) Manufacture of circuit board
JPH0529532A (en) Semiconductor module structure
TW463270B (en) Electronic device without the requirement of bonding
JPS62137818A (en) Manufacture of semiconductor device
JPH07131141A (en) Transferring method for flux
JPH07240431A (en) Alignment mark of circuit board and its manufacture
JPH09275105A (en) Transferring board and method for forming electrode for semiconductor device
JPS60198740A (en) Semiconductor device
JPH0483355A (en) Packaging method of semiconductor element
US8278769B2 (en) Compound semiconductor device and connectors
JPS63275155A (en) Manufacture of semiconductor device
KR20010065254A (en) Substrate for manufacturing semiconductor package