KR20010065254A - Substrate for manufacturing semiconductor package - Google Patents
Substrate for manufacturing semiconductor package Download PDFInfo
- Publication number
- KR20010065254A KR20010065254A KR1019990065126A KR19990065126A KR20010065254A KR 20010065254 A KR20010065254 A KR 20010065254A KR 1019990065126 A KR1019990065126 A KR 1019990065126A KR 19990065126 A KR19990065126 A KR 19990065126A KR 20010065254 A KR20010065254 A KR 20010065254A
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- South Korea
- Prior art keywords
- semiconductor package
- chip mounting
- semiconductor
- conductive pattern
- region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
본 발명은 반도체 패키지 제조용 부재에 관한 것으로서, 더욱 상세하게는 반도체 패키지의 제조공정중에 와이어 본딩 공정시, 와이어 본딩장치의 와이어 본딩 기준점이 되는 인식마크의 위치가 변경 개선된 반도체 패키지 제조용 부재에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a member for manufacturing a semiconductor package, and more particularly, to a member for manufacturing a semiconductor package in which a position of a recognition mark which is a wire bonding reference point of a wire bonding apparatus is changed during a wire bonding process during a manufacturing process of a semiconductor package. .
통상적으로 반도체 패키지는 전자기기의 집약적 발달과 소형화 경향으로 인하여 고집적화, 소형화, 고기능화의 추세에 병행하여, 상기 반도체 칩탑재판의 저면이 외부로 노출된 구조의 반도체 패키지, 솔더볼과 같은 인출단자를 포함하는 볼 그리드 어레이 반도체 패키지, 리드프레임, 인쇄회로기판, 필름등의 부재를 이용한 반도체 패키지등 다양한 종류의 패키지가 경박단소화로 개발되어 왔고, 개발중에 있다.In general, the semiconductor package includes a semiconductor package having a structure in which the bottom surface of the semiconductor chip mounting board is exposed to the outside and a lead terminal such as solder balls, in parallel with the trend of high integration, miniaturization, and high functionality due to the intensive development and miniaturization of electronic devices. Various types of packages, such as ball grid array semiconductor packages, lead frames, printed circuit boards, and semiconductor packages using films and the like, have been developed in light and short and short.
상기 부재중의 하나로서, 리드프레임은 골격을 이루는 사이드레일과, 반도체칩이 실장될 수 있는 칩탑재판과, 칩탑재판과 간격을 두고 사이드레일에 일체 형성된 다수의 리드와, 칩탑재판을 잡아줄 수 있도록 칩탑재판의 각 모서리를 사이드레일에 연결시켜주는 타이바로 구성되어 있다.As one of the members, the lead frame includes a side rail forming a skeleton, a chip mounting plate on which semiconductor chips can be mounted, a plurality of leads integrally formed on the side rails at a distance from the chip mounting plate, and a chip mounting plate. It is composed of tie bars that connect each edge of the chipboard to the side rails so that they can be lined up.
특히, 상기 리드프레임에는 3 ×3, 4 ×4등 매트릭스 형태로 다수의 칩탑재영역이 형성되어 있다.In particular, a plurality of chip mounting regions are formed in the lead frame in a matrix form such as 3 × 3, 4 × 4.
또한, 상기 부재중의 하나로서, 인쇄회로기판에도 수지층을 중심으로 상면 중앙에는 다수의 매트릭스로 된 칩탑재영역이 형성되어 있고, 그 외곽에는 칩탑재영역에 실장되는 반도체 칩과 와이어로 본딩되는 신호전달용, 접지용등 전도성패턴이 형성되어 있다.In addition, as one of the members, a printed circuit board also includes a chip mounting area formed of a plurality of matrices in the center of the upper surface of the printed circuit board, and a signal bonded to a semiconductor chip and a wire mounted in the chip mounting area on the outside thereof. Conductive patterns such as transfer and ground are formed.
한편, 상기와 같은 부재에서 특히, 인쇄회로기판의 반도체패키지 영역내에서 칩탑재영역에 인접한 위치에는 첨부한 도 2에 도시한 바와 같이 한군데 내지 두군데 구석 부위에 와이어 본딩시의 기준점이 되는 인식마크(14)가 새겨져 형성되어 있다.On the other hand, in such a member, in particular, the mark adjacent to the chip mounting area in the semiconductor package area of the printed circuit board as a reference mark at the time of wire bonding to one or two corners as shown in FIG. 14) is carved and formed.
상기와 같은 부재를 이용하여 반도체 패키지를 제조하는 공정중에서 부재의 칩탑재영역에 반도체 칩을 부착하는 공정 다음으로, 반도체 칩의 본딩패드와 부재의 본딩영역간에 와이어를 부착하는 공정이 진행되는데, 반도체 패키지 영역내에 형성된 인식마크를 와이어 본딩 장치가 인식하여, 이것을 기준점으로 와이어 본딩을 실시하게 된다.Attaching the semiconductor chip to the chip mounting region of the member in the process of manufacturing the semiconductor package using the member as described above Next, the process of attaching a wire between the bonding pad of the semiconductor chip and the bonding region of the member is carried out, the semiconductor The wire bonding apparatus recognizes the recognition mark formed in the package area, and wire bonding is performed to the reference point.
그러나, 복잡한 전도성패턴이 서로 인접되어 형성되어 있는 경우에는, 인식마크를 형성하는 작업이 어렵고, 인식마크를 작게 형성하더라도 와이어 본딩장치가 인식마크를 인식하지 못하는 에러를 일으키는 단점이 있다.However, when complex conductive patterns are formed adjacent to each other, it is difficult to form a recognition mark, and even when the recognition mark is made small, the wire bonding apparatus may cause an error that the recognition mark is not recognized.
더욱이, 반도체 패키지 영역이 매트릭스 타입으로 형성된 부재의 경우에는 반도체 패키지의 크기가 매우 경박단소화로 제조되기 때문에 인식마크의 크기는 더욱 작아서, 와이어 본딩장치가 인식마크를 인식하지 못하는 에러가 발생하여 와이어 본딩 작업에 불편을 주는 단점이 있었다.Furthermore, in the case of a member in which the semiconductor package region is formed in a matrix type, the size of the recognition mark is smaller because the size of the semiconductor package is manufactured in a very thin and small size, so that the wire bonding apparatus does not recognize the recognition mark. There was a disadvantage in that the bonding work inconvenient.
따라서, 본 발명은 상기와 같은 점을 해결하기 위하여 부재의 반도체 패키지 영역 밖에 인식마크를 형성하여, 반도체 패키지 영역내에는 인식마크가 없어진 공간을 전도성패턴 공간으로 활용할 수 있고, 와이어 본딩 장치가 와이어 본딩시 쉽게 인식마크를 인식할 수 있게 하여 종래의 와이어 본딩시의 에러발생을 방지할 수 있도록 한 반도체 패키지 제조용 부재를 제공하는데 그 목적이 있다.Therefore, in order to solve the above problem, the present invention forms a recognition mark outside the semiconductor package region of the member, so that the space in which the recognition mark is missing in the semiconductor package region can be used as the conductive pattern space, and the wire bonding apparatus is wire bonded. It is an object of the present invention to provide a member for manufacturing a semiconductor package that can easily recognize a recognition mark at the time of the present invention, thereby preventing the occurrence of an error in the conventional wire bonding.
도 1은 본 발명에 따른 반도체 패키지 제조용 부재를 나타내는 평면도,1 is a plan view showing a member for manufacturing a semiconductor package according to the present invention,
도 2는 종래의 반도체 패키지 제조용 부재를 나타내는 평면도.2 is a plan view showing a conventional member for manufacturing a semiconductor package.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 패키지 영역 12 : 부재10 semiconductor package region 12 member
14 : 인식마크 16 : 반도체 칩14: recognition mark 16: semiconductor chip
18 : 전도성패턴18: conductive pattern
이하 첨부도면을 참조로 본 발명을 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 수지층과, 수지층상에 형성된 칩탑재영역과, 이 칩탑재영역의 주변에 형성된 전도성패턴(18)으로 구성된 다수의 반도체 패키지 영역(10)을 포함하는 반도체 패키지 제조용 부재에 있어서, 상기 부재의 반도체 패키지 영역(10) 밖에 와이어 본딩시의 기준이 되는 인식마크(14)를 형성하여서 된 것을 특징으로 한다.The present invention provides a semiconductor package manufacturing member comprising a resin layer, a chip mounting region formed on the resin layer, and a plurality of semiconductor package regions 10 including conductive patterns 18 formed around the chip mounting region. It is characterized in that the recognition mark 14 serving as a reference for wire bonding is formed outside the semiconductor package region 10 of the member.
여기서 상기와 같은 특징으로 이루어진 본 발명을 실시예로서, 첨부한 도 1을 참조로 더욱 상세하게 설명하면 다음과 같다.Herein, the present invention having the features as described above will be described in more detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 따른 반도체 패키지 제조용 부재를 나타내는 평면도로서, 도면부호 12는 반도체 패키지 제조용 부재중의 하나인 인쇄회로기판을 나타낸다.1 is a plan view showing a member for manufacturing a semiconductor package according to the present invention, wherein reference numeral 12 denotes a printed circuit board which is one of the members for manufacturing a semiconductor package.
상기 부재(12)는 스트립 형태로 된 수지층상에 다수의 반도체 패키지 영역(10)이 형성되는데, 이 반도체 패키지 영역은 반도체 패키지의 경박단소화를 실현할 수 있도록 3 ×3등 매트릭스 타입으로 다수개가 형성되어진다.A plurality of semiconductor package regions 10 are formed on the resin layer in the form of a strip, and a plurality of the semiconductor package regions are formed in a matrix type such as 3 × 3 so as to realize light and small size reduction of the semiconductor package. It is done.
상기 반도체 패키지 영역(10)내에는 반도체 칩이 실장되는 칩탑재영역과 그 바깥쪽에 형성된 전도성패턴(18)으로 구성되어 있고, 반도체 패키지 영역(10)의 바깥쪽에는 상기 칩탑재영역과 전도성패턴으로 구성된 반도체 패키지 영역(10)을 지지하는 수지층으로 형성되어 있다.The semiconductor package region 10 includes a chip mounting region in which a semiconductor chip is mounted and a conductive pattern 18 formed outside thereof, and the chip mounting region and a conductive pattern on the outside of the semiconductor package region 10. It is formed of the resin layer which supports the structured semiconductor package region 10. FIG.
여기서 상기 부재의 반도체 패키지 영역의 바깥쪽에 인식마크(14)를 형성하는 바, 바람직하게는 매트릭스 타입의 반도체 패키지 영역(10)의 각 구석쪽에서 벗어난 위치에 형성하는 것이 바람직하다.Here, the identification mark 14 is formed outside the semiconductor package region of the member, and preferably, it is formed at a position deviated from each corner of the matrix type semiconductor package region 10.
한편, 종래에 칩탑재영역과 인접한 전도성패턴(18)에 형성된 인식마크는 배제되고, 이 배제된 위치에는 전도성 패턴(18)을 연장시켜 형성할 수 있게 됨에 따라, 전도성패펀(18)를 형성하는 공간활용도가 넓어지게 된다.On the other hand, the conventional recognition mark formed on the conductive pattern 18 adjacent to the chip mounting area is excluded, and the conductive pattern 18 is formed by extending the conductive pattern 18 at the excluded position. The space utilization is widened.
따라서, 상기 부재(12)의 칩탑재영역에 반도체 칩을 실장시킨 후, 와이어 본딩 공정을 진행시키는 바, 와이어 본딩장치가 상기 반도체 패키지 영역 바깥쪽에 형성된 인식마크(14)를 인식하고, 이곳을 기준점으로 하여, 반도체 칩(16)의 본딩패드와 전도성패턴(18)의 와이어 본딩영역간에 와이어로 본딩하는 작업을 용이하게 진행하게 된다.Therefore, after mounting the semiconductor chip in the chip mounting region of the member 12, the wire bonding process is performed, the wire bonding apparatus recognizes the recognition mark 14 formed on the outside of the semiconductor package region, the reference point As a result, the operation of bonding the wire between the bonding pad of the semiconductor chip 16 and the wire bonding region of the conductive pattern 18 can be easily performed.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 제조용 부재에 의하면, 종래에 부재의 반도체 패키지 영역내에 전도성패턴과 함께 형성되어 있던 인식마크를 반도체 패키지 영역 밖에 형성함으로써, 와이어 본딩장치가 인식마크를 용이하게 식별하여 와이어 본딩작업을 에러없이 진행할 수 있고, 종래의 인식마크가 제거된 자리에는 전도성패턴을 형성할 수 있어, 전도성패턴의 공간활용도를 높일 수 있는 효과를 제공하게 된다.As described above, according to the member for manufacturing a semiconductor package according to the present invention, the wire bonding apparatus facilitates the recognition mark by forming the recognition mark that has been conventionally formed with the conductive pattern in the semiconductor package region of the member outside the semiconductor package region. The wire bonding operation can be performed without error, and the conductive pattern can be formed in the place where the conventional recognition mark is removed, thereby increasing the space utilization of the conductive pattern.
Claims (1)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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KR1019990065126A KR20010065254A (en) | 1999-12-29 | 1999-12-29 | Substrate for manufacturing semiconductor package |
JP2000123164A JP3314304B2 (en) | 1999-06-07 | 2000-04-24 | Circuit board for semiconductor package |
US09/589,713 US6512288B1 (en) | 1999-06-07 | 2000-06-07 | Circuit board semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019990065126A KR20010065254A (en) | 1999-12-29 | 1999-12-29 | Substrate for manufacturing semiconductor package |
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KR1019990065126A KR20010065254A (en) | 1999-06-07 | 1999-12-29 | Substrate for manufacturing semiconductor package |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100848062B1 (en) * | 2006-11-13 | 2008-07-23 | 앰코 테크놀로지 코리아 주식회사 | PCB for manufacturing semiconductor package |
Citations (6)
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JPH05243284A (en) * | 1992-02-27 | 1993-09-21 | Nec Yamagata Ltd | Semiconductor device |
JPH0677349A (en) * | 1992-08-27 | 1994-03-18 | Fujitsu Ltd | Semiconductor package and is manufacture |
JPH0964093A (en) * | 1995-08-30 | 1997-03-07 | Sharp Corp | Electronic component |
JPH09223722A (en) * | 1996-02-15 | 1997-08-26 | Toshiba Microelectron Corp | Position recognizing mark, tab tape, semiconductor device and printed circuit board |
KR19990031267U (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Structure of Micro Film for Micro Ball Grid Array Semiconductor Package |
KR19990031265U (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Structure of Micro Film for Micro Ball Grid Array Semiconductor Package |
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1999
- 1999-12-29 KR KR1019990065126A patent/KR20010065254A/en not_active Application Discontinuation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05243284A (en) * | 1992-02-27 | 1993-09-21 | Nec Yamagata Ltd | Semiconductor device |
JPH0677349A (en) * | 1992-08-27 | 1994-03-18 | Fujitsu Ltd | Semiconductor package and is manufacture |
JPH0964093A (en) * | 1995-08-30 | 1997-03-07 | Sharp Corp | Electronic component |
JPH09223722A (en) * | 1996-02-15 | 1997-08-26 | Toshiba Microelectron Corp | Position recognizing mark, tab tape, semiconductor device and printed circuit board |
KR19990031267U (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Structure of Micro Film for Micro Ball Grid Array Semiconductor Package |
KR19990031265U (en) * | 1997-12-30 | 1999-07-26 | 마이클 디. 오브라이언 | Structure of Micro Film for Micro Ball Grid Array Semiconductor Package |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100848062B1 (en) * | 2006-11-13 | 2008-07-23 | 앰코 테크놀로지 코리아 주식회사 | PCB for manufacturing semiconductor package |
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---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |