JPS5911537U - multi-channel counter - Google Patents
multi-channel counterInfo
- Publication number
- JPS5911537U JPS5911537U JP10633782U JP10633782U JPS5911537U JP S5911537 U JPS5911537 U JP S5911537U JP 10633782 U JP10633782 U JP 10633782U JP 10633782 U JP10633782 U JP 10633782U JP S5911537 U JPS5911537 U JP S5911537U
- Authority
- JP
- Japan
- Prior art keywords
- channel
- channel counter
- control unit
- count input
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案の１実施例であり、第２図は、そのチ
ャンネルａに於る動作タイムチャートである。
図中説明に引用した信号は下記の通り、１：制御部、２
ａ〜２ｎ：フリップフロップ回路、３ａ〜３ｎ：計数信
号入力部、４ａ〜４ｎＨミル４ｎＨフリツプフロツプッ
ト入力、６ａ〜６ｎ：フリップフロップ回路の出力、７
ａ〜７ｎＨ制御部の計数要求信号入力、８ａ〜８ｎ：制
御部の計数要求信号リセット出力。FIG. 1 shows one embodiment of the present invention, and FIG. 2 is an operation time chart for channel a. The signals cited in the explanation in the figure are as follows: 1: control section, 2
a to 2n: flip-flop circuit, 3a to 3n: counting signal input section, 4a to 4nH mill 4nH flip-flop input, 6a to 6n: output of flip-flop circuit, 7
a to 7nH control unit count request signal input, 8a to 8n: control unit count request signal reset output.
Claims (1)
カウント入力部を備え、各チャンネルに、各チャンネル
のカウント入力記号によってセットされ、制御部からの
リセット信号により、各チャンネル単独にリセットきれ
るフリップフロップ回路を設けた事を特徴とする多チヤ
ンネルカウンタ。Equipped with a microcomputer control unit and a count input unit for multiple channels, each channel is equipped with a flip-flop circuit that is set by the count input symbol of each channel and can be reset for each channel independently by a reset signal from the control unit. A multi-channel counter featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10633782U JPS5911537U (en) | 1982-07-15 | 1982-07-15 | multi-channel counter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10633782U JPS5911537U (en) | 1982-07-15 | 1982-07-15 | multi-channel counter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5911537U true JPS5911537U (en) | 1984-01-24 |
Family
ID=30248882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10633782U Pending JPS5911537U (en) | 1982-07-15 | 1982-07-15 | multi-channel counter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5911537U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52140263A (en) * | 1976-05-19 | 1977-11-22 | Hitachi Ltd | Multi-input pulse integrator |
-
1982
- 1982-07-15 JP JP10633782U patent/JPS5911537U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52140263A (en) * | 1976-05-19 | 1977-11-22 | Hitachi Ltd | Multi-input pulse integrator |
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