JPS59114619A - Power source controlling system - Google Patents

Abstract

PURPOSE:To execute exactly disconnection control of a power source by cutting a low-order power source only in case when all high-order devices are in a state that the power source is cut, when a power source cutting indication is outputted from some high-order device. CONSTITUTION:A power source control device 2 is interposed between a central processing unit 1 being a high-order device, and a peripheral device 3 being a low-order device, and turn-on and turn-off of a power source to the peripheral device 3 are controlled by an indication from the central processing unit 1. When cutting the power source, power source cut state signals OFS1, OFS2 from each central processing unit 1 become an AND signal OFS3 through an AND gate 11, and also power source cutting signals OFF1, OFF2 are inputted to a pulse generating circuit 17 through AND gates 14, 15 and an OR gate 16 together with the OFS3. In this way, when the OFF1 or the OFF2 is turned on, the power source of the peripheral device 3 is cut by a power source control part 10 only in case when both the OFS1 and the OFS2 are turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a system for controlling power on/off of a lower-level device that is shared by a plurality of higher-level devices. More specifically, the present invention provides a system for controlling the power supply of peripheral systems based on commands from the main systems and organizations in a computer organization consisting of a plurality of main systems and common peripheral systems. Power control method suitable for % formula % Referring to FIG. 1, the concept of power control of a computer organization will be explained. Here, it is assumed that there are two central processing units 1 and two peripheral devices 3 common to them.

Each central processing unit 1 has a power control mechanism and controls the power control device 2 through a power control interface 4. Further, the power supply control device 2 controls power on and off of the peripheral device 3 through a power supply control interface 5. Here, when the power supply control device 2 receives a power-on instruction from one central processing unit 10, it immediately sends a power-on command to the peripheral device 3, waits to receive disconnection commands from the two central processing units 1, and then sends a power-on command to the peripheral device 3. A disconnection instruction is sent to 3. As a result, the power control mechanism of the central processing unit 1 receives commands from the operator, commands from the program,
The power to the central processing unit 1 can be turned on and off in response to commands from the remote maintenance center through the line, and the power to the peripheral devices 3 can be turned on and off via the power supply control device 2. The peripheral device 3 is a common resource for the central processing unit 1, and the power control device 2 makes sure that the peripheral device W3 is also powered on while at least one of the central processing unit 1 is powered on. It's meant to be controlled.

According to such power supply control, the number of power-on operations during operation and maintenance is kept to a minimum, thereby reducing the power consumption of the computer organization.

There are various methods for realizing the above-mentioned power supply control depending on the format of the signal from the central processing unit and the configuration of the power supply control device, and two typical conventional methods will be described below.

FIG. 2 is a block diagram showing the first conventional method, and the third
The figure is a timing diagram of the signals in FIG.

In this power control system, each central processing unit 1 outputs power-on instruction signals ONI, ON2 and power-off instruction signals 0FFI, 0FF2.

The power supply control device 2 is ONl at an OR gate (OR) 18.
Creates the OR signal ON of ON2 and sends it to the power supply control unit 10.
input as an input trigger. That is, when either ON1 or ON2 is turned on while the peripheral device 3 is powered off, ON is turned on and the power control unit 10 turns on the power to the peripheral device 3. Further, when the UNI and ON2 are turned on, the flip-flop (FF) 6.7 is set, and its outputs F1 and F2 are turned on.

When UFFI and 0FF2 from each central processing unit 1 are turned off, FF6.7 is reset. The outputs F1 and F2 of these FFs 6.7 are logically summed by an OR gate (OR) 8, and the output F12 thereof is inputted to the pulse generation circuit 9.

This pulse generating circuit 9 is triggered when F12 transitions from an on state to an on state, and turns the output OFF on for a certain period of time. The power control unit 10 turns off the power to the peripheral device 3 at the rise of OFF. That is, the peripheral device 3 is powered off in response to a disconnection instruction from the slower one of the two central processing units 1 .

FIG. 4 is a block diagram showing the second conventional method, and the fifth
The figure is a timing diagram of the signal. In this power control system, each central processing unit 1 outputs power-off state signals 0FSI and 0FS2 that are turned on when the power to the central processing unit 1 is turned off.

Since the charging instructions are exactly the same as in the previous example, they are omitted from the diagram.

The power supply control device 2 creates an AND signal 0FS3 of 0FS1 and 0FS2 using an AND gate (AND) Jl. The pulse generation circuit 12 turns the output OFF and turns it ON for a certain period of time at the rising edge of (J F S 12).
When FF is turned on, the power to the peripheral device 3 is cut off. That is, when both OFS1 and OFS2 are turned on, the peripheral device 3 is powered off. Further, the power supply control unit 10 turns on the power of the peripheral device 3 when the ON signal created in the same manner as in the previous example is turned on.

The first and second power supply control methods described above have the following drawbacks regarding power-off control of peripheral devices.

The first power control method is that when a central processing unit in a computer organization is unable to send out a power-off instruction due to a power failure, it cannot be disconnected even if it receives a power-off instruction from the remaining normal central processing unit. becomes.

In this case, it is necessary to manually turn off the power to all peripheral devices.

In the second power control method, when one central processing unit has finished operating and its power-off state signal is on, only the other central processing unit is operating, and the If a power failure occurs and the power-off status signal is turned on, the power to the peripheral devices will also be turned off at the same time.

In this case, it is not necessary to power off the peripheral device, but it takes time to start up the peripheral device when recovering from a failure (peripheral devices such as magnetic disks require a certain amount of time after power is turned on until operation becomes stable). ).

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a power control system that improves the above-mentioned drawbacks regarding power cut-off.

[Summary of the invention]

When applied to a computer system, for example, the power control method of the present invention causes each central processing unit to send out a power cut instruction signal to peripheral devices and a power state signal indicating the power state of its own device. When the power supply control unit receives a line disconnection instruction signal from one of the central processing units, only when the power status signals from all central processing units indicate the power-off status, the power supply to the peripheral devices is switched off. cut.

[Embodiments of the invention]

FIG. 6 is a block diagram showing one embodiment of the present invention, and FIG. 7 is a timing diagram of its signals.

J6, parts corresponding to those in FIGS. 1 to 5 are given the same reference numerals. In addition, the central processing unit k1 outputs a power-on instruction signal, and the logical sum of these signals, 1δ ON, is created by the power supply control unit 2, but this is the same as in Figure 2, so it is omitted in the figure. It is.

In the tS control device 2, the AND signal 0 of the power-off state signal ops 1 sent from each central processing unit 1 and the UF52 (a signal that turns on when the power of the central processing unit itself is turned off) is
Create FS3 using AND gate (AND) 11. In addition, the power-off instruction signal output from each central processing unit 1 is turned OFF.
AND signal CKzSCK of 0FF2 and the above 0FS3
2 with A/Toge) (AND) 14.15 respectively. A logical phase signal CK3 of these CKI and CK2 is generated by an OR game (OR) 16 and input to a pulse generation circuit 17. When CK3 is turned on, this pulse generating circuit 17 turns on the output OFF for a certain period of time. Power control unit 1
0 turns off the power to the peripheral device 3 when OFF is turned on.

That is, when OF'FI or 0FF2 turns on, OF'FI
Power off the peripheral device 3 only when both S1, (,1FS2 are on).

According to such a method, power supply control can be performed with higher reliability than the two conventional methods described above.

First, even if one of the central processing units 1 has a failure that prevents it from sending out a power-off instruction signal (for example, 0FF1),
As long as the power-off state signal (OFSI) is sent normally, the power to the peripheral device 3 can be normally turned off by the power-off instruction signal (OFF2) from the other central processing unit 1. Also, when one central processing unit 1 has finished its operation and its power-off state signal (for example, 0FSI) is on, a power failure occurs in the other central processing unit 1 that is in operation, and its power-off state occurs. Even if the signal (UF82) is turned on, the power to the peripheral device 9 is not turned off unless the power cut-off instruction signal (OFF2) is turned on. Therefore, the trouble of restarting the peripheral device 3 at the time of failure recovery is saved.

In the above embodiment, each central processing unit sends out a power-off state signal that turns on when the power is off, but it may also send a power-on state signal that turns on when the power is on. In this case, the power control device may turn off the power to the peripheral devices when it receives power cut instruction No. 43 on the condition that the power on state signals from all central processing units are off. . (For example, a. Change the spike 11 to a NOR gate and input the power-on state signal to it.) Each central processing unit also sends out a local/remote status signal indicating whether it is in the local or remote status, and if one central processing unit is in the local status, the signal from that central processing unit is The power control device may be configured to ignore the power-off instruction and power-on instruction, and turn off and turn on the power to the peripheral device only in accordance with the power-off instruction and on-on instruction from the other central processing unit.

〔Effect of the invention〕

As described in detail above, the present invention is designed to turn off the power to lower-level devices only when all higher-level devices are in a power-off state when a power-off instruction is issued from a certain higher-level device (central processing unit). Because of this, power-off control for lower-level devices can be performed more reliably than in the past.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the concept of power supply control in a computer organization, FIGS. 2 and 3 are block diagrams and signal timing diagrams for explaining an example of a conventional power supply control method, and FIGS. FIG. 5 is a block diagram and signal timing diagram for explaining another example of the conventional power supply control method,
FIG. 6 and FIG. 7 are a block diagram and a signal timing diagram for explaining one embodiment of the power supply control method according to the present invention. 1...Central processing unit, 2...Power control device, 3...
・Peripheral device, 10...Power control unit, 11.14.15
...and gate, 16...or gate, 17...
・Pulse generation circuit, OFS 1, (JFS2...Power cut-off status signal, 0FF1, OF' F2...Power cut-off instruction signal.] □□''. Figure 3 FF Figure 5 OFF

Claims (1)

[Claims] A power source in which a power control device is interposed between a plurality of higher-level devices and lower-level devices shared by the higher-level devices, and the power control device turns on or off the power to the lower-level devices according to instructions from each of the higher-level devices; In the control method, each of the higher-level devices sends a power-off instruction signal to the lower-level device and a power state signal indicating the power state of its own device, and the power control device receives the power-off instruction signal from any of the higher-level devices. 1. A power supply control device characterized in that the power supply control device cuts off the power to the lower order device only when all the power state signals of the upper order device indicate a power cut off state when receiving the power supply control device.