JPS59113629A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59113629A
JPS59113629A JP57223184A JP22318482A JPS59113629A JP S59113629 A JPS59113629 A JP S59113629A JP 57223184 A JP57223184 A JP 57223184A JP 22318482 A JP22318482 A JP 22318482A JP S59113629 A JPS59113629 A JP S59113629A
Authority
JP
Japan
Prior art keywords
stage
semiconductor chip
semiconductor
cracks
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57223184A
Other languages
Japanese (ja)
Inventor
Kiyoshi Kakiya
垣谷　清
Mitsuhiro Oosawa
大澤　満洋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57223184A priority Critical patent/JPS59113629A/en
Publication of JPS59113629A publication Critical patent/JPS59113629A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the cracks, breakages, etc. of a semiconductor chip by forming an irregular section to the surface of a loading member to be die- bonded. CONSTITUTION:The irregular sections are formed to the surface of a semiconductor-chip fitting region of the loading member on which the semiconductor- chip is joined through brazing. The irregular sections such as semispherical projections 13 in height of several microns or more are formed extending over approximately the whole surface of a stage 2. Or columnar projections 14 in height of several microns are formed as checkers. Accordingly, a solder material also intrudes into the valleys of the projections 13 or 14, the thickness of the solder material is thickened only in one parts, a plane-to-plane bonding between the back of the semiconductor chip and the surface of the stage is avoided, and the semiconductor chip is bonded on the stage 2 without generating the cracks, breakages, etc. of the chips.

Description

【発明の詳細な説明】 （１１発明の技術分野 本発明は半導体装置、詳しくはプラスチックＩＣ，セラ
ミックＩＣ等のステージまたはセラミック基体の表面に
凹凸を設け、半導体チップ（ペレットともいう）のクラ
ンク（ひび）、割れ等が防止される半導体装置に関する
。Detailed Description of the Invention (11) Technical Field of the Invention The present invention relates to a semiconductor device, specifically a stage or a ceramic substrate of a plastic IC, a ceramic IC, etc., by providing unevenness on the surface thereof to prevent cranks (cracks) of semiconductor chips (also referred to as pellets). ), relates to a semiconductor device that prevents cracking, etc.

（２）技術の背景 プラスチックＩＣと呼称される半導体装置は、第１図の
断面図に示される構造のもので、同図において、■は！
！積回路が形成された半導体チップ、２は半導体チップ
の搭載部材であるステージ、３は半導体チップ１をステ
ージ２にろう付けして接合するろう材、４は外部との接
続をとる外リードのインナーリード、６は半導体チップ
１の電極バッド１ａとインナーリードとを接続するワイ
ヤ、７は半導体チップ１を封止するプラスチック封止体
をそれぞれ示し、かかる装置はコンピュータ等に多用さ
れるもので、半導体パッケージとも呼称される。(2) Background of the technology A semiconductor device called a plastic IC has a structure shown in the cross-sectional view of FIG. 1. In the same figure, ■!
! A semiconductor chip on which an integrated circuit is formed, 2 a stage which is a mounting member for the semiconductor chip, 3 a brazing material for brazing and joining the semiconductor chip 1 to the stage 2, and 4 an inner part of an outer lead for connection with the outside. A lead, 6 is a wire connecting the electrode pad 1a of the semiconductor chip 1 and the inner lead, and 7 is a plastic sealing body for sealing the semiconductor chip 1. Such devices are often used in computers, etc. Also called a package.

搭載部材、すなわちステージ２は第２図の平面図に示さ
れる構造のもので、同図において、８はステージ２をリ
ードフレームのクレードルに連結するピンチを示し、リ
ードフレームはステージ２の多数個が並んで形成された
ものである。なお第２図および以下の図において、既に
図示した部分と同じものは同一符号を付して表示する。The mounting member, that is, the stage 2, has the structure shown in the plan view of FIG. They are formed side by side. In FIG. 2 and the following figures, the same parts as those already illustrated are designated by the same reference numerals.

従来、半導体チップｌは、金・シリコン共晶付けによっ
てステージに接合された（グイ付けともいう）、すなわ
ち、金ペーストをステージＩ上におき、ステージエを加
熱して金ペーストを熔かし、半導体チップ１を上からス
テージ２に接し′にすりつけながら回し、金ペーストが
半導体装置プ１の裏面全体をぬらずようにし、しかる後
にステージ２、従って金ペーストを冷却させて、半導体
チ・ンプ１をステージ２に接合させる。Conventionally, a semiconductor chip I has been bonded to a stage by gold-silicon eutectic bonding (also called bonding), that is, gold paste is placed on the stage I, the stage I is heated to melt the gold paste, The semiconductor chip 1 is brought into contact with the stage 2 from above and rotated while rubbing it against the stage 2 so that the gold paste does not wet the entire back surface of the semiconductor device chip 1. After that, the stage 2 and therefore the gold paste are cooled and the semiconductor chip 1 is turned. is joined to stage 2.

他方、セラミックＩＣと呼称される半導体装置は第３図
の断面図に示される構成のもので、半導体チップ１は、
セラミック基体９上に接着されたステージ２上に接合さ
れ搭載される。なお同図において、１０は半導体チップ
１を密封するためのキャンプを示す。セラミックＩＣに
おいては、半導体チップ１がステージ２上にではなく、
セラミック基体９に直接搭載されるものもあり、そのと
きはセラミツク基体９自体が半導体チップの搭載部材と
なる。On the other hand, a semiconductor device called a ceramic IC has the configuration shown in the cross-sectional view of FIG.
It is bonded and mounted on a stage 2 bonded onto a ceramic base 9. In the figure, 10 indicates a camp for sealing the semiconductor chip 1. In the ceramic IC, the semiconductor chip 1 is not on the stage 2,
Some are mounted directly on the ceramic base 9, in which case the ceramic base 9 itself becomes the mounting member for the semiconductor chip.

（３）従来技術と問題点 最近、半導体チップは機能の増大に伴って、従来２ｍｍ
〜３ｍｍ口であったものが６ｍｍ〜７ｍｍ口と大型化さ
れる１頃向にある。また、熱放散効率を改善する目的で
、ステージは、従来鉄・ニッケル合金（例えば４２アロ
イ）で作られていたものが、銅合金（例えば９８％銅に
鉄、錫、亜鉛等を加えた合金）が用いられるようになっ
てきた。かがるステージの材料の変化の結果、半導体チ
ップとステージ、およびそれらを接合するろう材の熱膨
張差により、半導体チップにクランク、割れ等が発生ず
る例が経験されるようになった。(3) Conventional technology and problems Recently, with the increase in functionality of semiconductor chips, the conventional 2 mm
What was once a ~3mm opening is about to become larger, with a 6mm~7mm opening. In addition, in order to improve heat dissipation efficiency, stages that were conventionally made of iron/nickel alloy (e.g. 42 alloy) have been replaced with copper alloy (e.g. 98% copper with iron, tin, zinc, etc. added). ) has come into use. As a result of changes in the material of the bending stage, cases have been experienced in which cracks, cracks, etc. occur in the semiconductor chip due to the difference in thermal expansion between the semiconductor chip, the stage, and the brazing material that joins them.

更には、従来の金・シリコン共晶付けにおいても、金・
シリコン共晶の強度が大で、接合する温度も高いため、
半導体チップに大なるストレスを加える。また、金のコ
ストは高騰化する伸開にあり、製造コス１−の面から金
ベースＩ・の使用は必要な場合に限定したい。Furthermore, even in conventional gold/silicon eutectic deposition, gold/silicon eutectic
Because the strength of silicon eutectic is high and the bonding temperature is high,
Adds great stress to semiconductor chips. Furthermore, the cost of gold is on the rise, and from the viewpoint of manufacturing costs, it is desirable to limit the use of gold base I to only when necessary.

上記したクランク、割れ等は、半導体チップの特性を劣
化させるだけでなく、それを不良品にする要素であるが
、それが発生する原因の１つは、プラスチックＩＣまた
はセラミ・ツクＩＣに用いられる諸材料の性質の差によ
る。下記の表は、これらの半導体装置に用いられる主な
材料の線膨張計数（１／℃）および熱伝導率（ｃａｌ　
／　ｃｍ−ｓｅｃ　・”ｃ　）を示すものであり、この
表において、コバール、Ｆｅ−Ｎｉ合金、セラミックは
ステージを構成する材料（セラミンクは場合によっては
ステージに代る）、金、銀、半田、銀ペーストはろう材
である。The above-mentioned cracks, cracks, etc. not only deteriorate the characteristics of semiconductor chips, but also cause them to become defective products.One of the reasons why they occur is that they are used in plastic ICs or ceramic ICs. This is due to differences in the properties of various materials. The table below shows the linear expansion coefficient (1/℃) and thermal conductivity (cal) of the main materials used in these semiconductor devices.
/ cm-sec ・"c), and in this table, Kovar, Fe-Ni alloy, and ceramic are the materials that make up the stage (ceramic may replace the stage in some cases), gold, silver, solder, Silver paste is a brazing material.

品名　　　　線膨張係数　　　　　　熱伝導率（１／”
Ｃ）　　　　　（ｃａｌ／ｃｍ・ｓｅｃ”Ｃ）シリコン
　　　３．５９ｘ　１０−６０．３０コバール　　　４
．５４〜５．０８ｘ　１０−６０．０４Ｆｅ−Ｎｉ合金
　　４．５〜５．８　ｘ　１０””　　　　０．０３２
金　　　　　１４．２Ｘ　１０−６　　　　　　　　　
０．７１銀　　　　１９．７Ｘ　１０−６　　　　　　
１．０２はんだ　　　　２Ｂ、７Ｘ　１０−６　　　　
　　０．０８５銀ペースト　　２５．５ｘ　１０−６０
．００６セラミソク　　７　Ｘ　１０−６ クランク、割れ等はろう材のぬれ具合によっても影響を
受番ノる。第４図は第１図の半導体チップ１の裏面のろ
う材のぬれを示すための図で、図に白地の部分１１はぬ
れていない部分、砂地を付した部分１２がぬれた部分で
ある。本願発明者の実験によると、同図の（ａｌ、ｆｂ
）およびｔｅｌの状態ではクラック、割れ等の危険性が
ないのであるが、それ以外の＋ｄ）、（ｅ）、（ｆ）、
＋ｇ）およびｆｈ）の状態ではその危険性が高いことが
確認された。かかるぬれの悪さの原因は、前記した半導
体チップの大型化も重要な原因であるが、半導体チップ
の裏面の酸化膜（ＳｉＯｚ膜）と、チップ（またはセラ
ミック基体）の接合表面とがたがいに平坦であることも
原因となっている。Product name Linear expansion coefficient Thermal conductivity (1/”
C) (cal/cm・sec”C) Silicon 3.59x 10-60.30 Kovar 4
．． 54~5.08x 10-60.04Fe-Ni alloy 4.5~5.8 x 10"" 0.032
Gold 14.2X 10-6
0.71 silver 19.7X 10-6
1.02 solder 2B, 7X 10-6
0.085 silver paste 25.5x 10-60
．． 006 Ceramisoku 7 X 10-6 Cracks, cracks, etc. are also affected by the wetness of the brazing filler metal. FIG. 4 is a diagram showing the wetting of the brazing material on the back surface of the semiconductor chip 1 shown in FIG. 1. In the figure, the white area 11 is the unwetted area, and the sandy area 12 is the wetted area. According to the inventor's experiments, (al, fb
) and tel, there is no risk of cracking, cracking, etc., but in other cases +d), (e), (f),
It was confirmed that the risk is high in the conditions +g) and fh). The aforementioned increase in the size of the semiconductor chip is an important cause of such poor wetting, but the oxide film (SiOz film) on the back surface of the semiconductor chip and the bonding surface of the chip (or ceramic substrate) are flat. This is also a cause.

（４）発明の目的 本発明は上記従来の問題に鑑み、プラスチックＩＣ、セ
ラミックＩＣ等の半導体装置において、半導体チップが
大型化し、ステージとろう材の材料が多岐にわたる場合
においても、半導体チップが、それのクランク、割れ等
を発生ずることなしに、搭載部材、すなわちステージま
たはセラミック基体上に接合された半導体装置の提供を
目的とする。(4) Purpose of the Invention The present invention has been made in view of the above-mentioned conventional problems, and in semiconductor devices such as plastic ICs and ceramic ICs, even when the semiconductor chips become larger and the materials of the stage and the brazing material are diverse, the semiconductor chips The object of the present invention is to provide a semiconductor device that can be bonded onto a mounting member, that is, a stage or a ceramic substrate, without causing cranking, cracking, or the like.

（５）発明の構成 そしてこの目的は本発明によれば、半導体チップがろう
付けによって接合される搭載部祠の半導体チップ数例は
領域表面に凹凸を設けてなることを特徴とする半導体装
置を提供することによって達成される。(5) Structure and object of the invention According to the present invention, there is provided a semiconductor device characterized in that several examples of the semiconductor chips in the mounting area where the semiconductor chips are joined by brazing are provided with unevenness on the surface of the area. This is achieved by providing

（６）発明の実施例 以下本発明実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

本願発明者は、上記したクランク、割れ等を防止するに
は、半導体チップとステージ（またはセラミック基体）
との膨張差をろう材で緩和させ、このろう材の厚みを可
能なかぎり大にすると同時に、ろう材が半導体チップ裏
面に具合よく、すなわち第４図ｔａ＋、（ｂｌおよび（
Ｃ１に示される如くにぬれるようにする必要のあること
を認識した。そのためには、例をステージにとると、ス
テージ面に凹凸を設け、ろう祠の厚さを、１部分のみに
ついて（スポット的）ではあるが大にすること、および
それによって半導体裏面と接合するステージ表面を平坦
でなくすることを考えついた。The inventor of the present application believes that in order to prevent the above-mentioned cracks, cracks, etc., the semiconductor chip and stage (or ceramic substrate)
At the same time, the thickness of the brazing material is made as large as possible, and at the same time, the brazing material is placed on the back surface of the semiconductor chip.
It was recognized that it was necessary to make it wet as shown in C1. For this purpose, taking the stage as an example, it is necessary to create unevenness on the stage surface, increase the thickness of the waxing hole only in one part (spotwise), and thereby make the stage bonded to the back side of the semiconductor. I came up with the idea of making the surface not flat.

かかるステージの第１実施例は、第５図の［ａｌと（ｂ
ｌにそれぞれ平面図および断面図で示され、この実施例
においては、ステージ２のほぼ全面にわたって、数ミク
ロン以上の高さの半球状突起１３を形成する。A first embodiment of such a stage is shown in FIG.
In this embodiment, a hemispherical protrusion 13 having a height of several microns or more is formed over almost the entire surface of the stage 2.

本発明のステージの第２実施例においては、第６図の（
ａ）平面図と（ｂ）断面図に示される如く、基盤の目の
如くに第１実施例同様数ミクロン以上の高さの柱形の突
起１４を形成する。In the second embodiment of the stage of the present invention, (
As shown in a) plan view and (b) sectional view, columnar protrusions 14 with a height of several microns or more are formed like the eyes of the base, similar to the first embodiment.

−いずれの実施例においても、ろう材は突起１３または
１４の谷間にも入り込み、そこでろう材の厚さは一部分
のみではあるが確かに厚くなっている。- In both embodiments, the filler metal also penetrates into the valleys of the protrusions 13 or 14, where the thickness of the filler metal increases, albeit only partially.

また、かかる突起により、従来の互いに平坦な半導体チ
ップの裏面とステージ表面との平面対平面接合は確実に
回避される。第７図は、第１図のプラスチックＩＧのス
テージ２を第５図に示す如くに形成した場合の同ステー
ジを半導体チップの接合状態を示す断面図で、前記した
ことが十分明確に示されている。Moreover, such a protrusion reliably avoids the conventional plane-to-plane bonding between the back surface of the semiconductor chip and the surface of the stage, which are mutually flat. FIG. 7 is a cross-sectional view of the stage 2 of the plastic IG shown in FIG. 1 when it is formed as shown in FIG. 5, showing the bonding state of the semiconductor chips, and the above-mentioned matters are clearly shown. There is.

セラミック基体９についても、それに直接半導体チップ
が接合されるとき゛、ずなわちセラミック基体９が搭載
部材であるときは、セラミック基体９の接合表面を第５
図または第６図に示す如く形成する。Regarding the ceramic substrate 9, when a semiconductor chip is directly bonded to it, that is, when the ceramic substrate 9 is a mounting member, the bonding surface of the ceramic substrate 9 is
It is formed as shown in FIG.

ステージに第５図または第６図の構造をもたせるには、
リードフレーム作成のとき、スタンピング（打抜き）に
よって突起１３または１４を形成する。セラミック基体
の場合は、それの成形において、型（ダイ）に所望の凹
凸をつけておくとよい。To make the stage have the structure shown in Figure 5 or 6,
When producing the lead frame, the projections 13 or 14 are formed by stamping. In the case of a ceramic substrate, it is preferable to form the desired unevenness on the mold (die) during molding.

いずれにしても、図示の凹凸は、なんら余分の工程を用
いることなく容易に形成可能である。In any case, the illustrated unevenness can be easily formed without using any extra steps.

（７）発明の効果 以上詳細に説明した如く、本発明にかかる半導体装置に
おいては、半導体チップがダイ付け（接合）される搭載
部材、すなわちステージまたはセラミック基体の表面に
凹凸を設し」ることにより、従来経験された半導体チッ
プのクランク、割れ等が防止され、本発明の半導体装置
は、半導体チップが大型化され、またステージ、ろう材
の材料が多岐にわたっても、確実にクラック、割れ等を
防止することができ、更には前記のステージまたはセラ
ミック基体の凹凸表面は、特別の工程を要することなく
形成可能であるので、半導体装置製造歩留りの向上に効
果大である。なお、凹凸の形状は上記に説明した形状に
限定されるものではない。(7) Effects of the Invention As explained in detail above, in the semiconductor device according to the present invention, unevenness is provided on the surface of the mounting member to which the semiconductor chip is die-attached (bonded), that is, the stage or the ceramic substrate. This prevents cracks, cracks, etc. of semiconductor chips that have been experienced in the past, and the semiconductor device of the present invention reliably prevents cracks, cracks, etc. even when semiconductor chips become larger and materials for stages and brazing filler metals vary. Furthermore, the uneven surface of the stage or ceramic substrate can be formed without requiring any special process, which is highly effective in improving the manufacturing yield of semiconductor devices. Note that the shape of the unevenness is not limited to the shape described above.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はプラスチックＩＣの断面図、第２図は第１図の
プラスチックｌＣのｉテージの平面図・第３図はセラミ
ックＩＣの断面図、第４図は第１図の半導体チップの裏
面におけるろう材のぬれ状態を示す図、第５図と第６図
は本発明の第１実施例と第２実施例を示す図で、それぞ
れの（ａｌは平面図、ｌｂｌは断面図、第７図は本発明
の第１実施例の接合状態を示す半導体チップとステージ
の断面図である。 ■−半導体チツブ、１ａ−電極パソド、２−ステージ、
３−ろう材、４−インナーリード、５＝−外リード、６
−ワイヤ、７−プラスチック封止体、８・・−ピンチ、
９−セラミック基体、１０−キャップ、１１−半導体チ
ップ裏面の”ろう材のぬれていない部分、１２−・半導
体チップ裏面のろう材のぬれた部分、１３−・球状突起
、１４−柱状突起 第１図 第２図　　　　　　　　第３図 第４図 （ａ）　　　　（ｂ）　　　　　（ｃ）　　　　　（ｄ
）（ｅ）　　　　　（ｆ）　　　　　（ｇ）　　　　　
（ｈ）第５図　　　　第６１゛４Figure 1 is a cross-sectional view of the plastic IC, Figure 2 is a plan view of the i-stage of the plastic IC in Figure 1, Figure 3 is a cross-sectional view of the ceramic IC, and Figure 4 is the back side of the semiconductor chip in Figure 1. Figures 5 and 6 are diagrams showing the wet state of the brazing filler metal, and Figures 5 and 6 are diagrams showing the first and second embodiments of the present invention. 1 is a sectional view of a semiconductor chip and a stage showing the bonded state of the first embodiment of the present invention. ■-semiconductor chip, 1a-electrode pad, 2-stage,
3-brazing metal, 4-inner lead, 5=-outer lead, 6
- wire, 7 - plastic sealing body, 8... - pinch,
9-ceramic base, 10-cap, 11-unwet part of the brazing material on the back side of the semiconductor chip, 12--wet part of the brazing material on the back side of the semiconductor chip, 13--spherical protrusion, 14-first columnar protrusion Figure 2 Figure 3 Figure 4 (a) (b) (c) (d
) (e) (f) (g)
(h) Figure 5 Figure 61゛4

Claims (1)

【特許請求の範囲】[Claims] 半導体チップがろう付けによって接合される搭載部材の
半導体チップ取付は領域表面に凹凸を設けてなることを
特徴とする半導体装置。1. A semiconductor device, wherein a semiconductor chip is attached to a mounting member to which the semiconductor chip is bonded by brazing by providing unevenness on the surface of the mounting area.
JP57223184A 1982-12-20 1982-12-20 Semiconductor device Pending JPS59113629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57223184A JPS59113629A (en) 1982-12-20 1982-12-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57223184A JPS59113629A (en) 1982-12-20 1982-12-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59113629A true JPS59113629A (en) 1984-06-30

Family

ID=16794116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57223184A Pending JPS59113629A (en) 1982-12-20 1982-12-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59113629A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61196545A (en) * 1985-02-26 1986-08-30 Rohm Co Ltd Bonding for pellet
US5242862A (en) * 1990-02-14 1993-09-07 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54133072A (en) * 1978-04-06 1979-10-16 Nec Corp Semiconductor device
JPS5525391B2 (en) * 1972-12-27 1980-07-05

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525391B2 (en) * 1972-12-27 1980-07-05
JPS54133072A (en) * 1978-04-06 1979-10-16 Nec Corp Semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61196545A (en) * 1985-02-26 1986-08-30 Rohm Co Ltd Bonding for pellet
JPH0578936B2 (en) * 1985-02-26 1993-10-29 Rohm Kk
US5242862A (en) * 1990-02-14 1993-09-07 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same
US5663096A (en) * 1990-02-14 1997-09-02 Nippondenso Co., Ltd. Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance
US5689130A (en) * 1990-02-14 1997-11-18 Nippondenso Co., Ltd. Vertical semiconductor device with ground surface providing a reduced ON resistance
US5994187A (en) * 1990-02-14 1999-11-30 Nippondenso Co., Ltd. Method of manufacturing a vertical semiconductor device
US6498366B1 (en) 1990-02-14 2002-12-24 Denso Corporation Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode
US6649478B2 (en) 1990-02-14 2003-11-18 Denso Corporation Semiconductor device and method of manufacturing same
US6903417B2 (en) 1990-02-14 2005-06-07 Denso Corporation Power semiconductor device
US6949434B2 (en) 1990-02-14 2005-09-27 Denso Corporation Method of manufacturing a vertical semiconductor device
US7064033B2 (en) 1990-02-14 2006-06-20 Denso Corporation Semiconductor device and method of manufacturing same

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