JPH05235228A - Method of manufacturing electronic component - Google Patents

Method of manufacturing electronic component

Info

Publication number
JPH05235228A
JPH05235228A JP3061282A JP6128291A JPH05235228A JP H05235228 A JPH05235228 A JP H05235228A JP 3061282 A JP3061282 A JP 3061282A JP 6128291 A JP6128291 A JP 6128291A JP H05235228 A JPH05235228 A JP H05235228A
Authority
JP
Japan
Prior art keywords
annular groove
scrub
region
chip
support plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3061282A
Other languages
Japanese (ja)
Other versions
JP2857648B2 (en
Inventor
Kazuyuki Tamura
和之 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP3061282A priority Critical patent/JP2857648B2/en
Publication of JPH05235228A publication Critical patent/JPH05235228A/en
Application granted granted Critical
Publication of JP2857648B2 publication Critical patent/JP2857648B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H01L2224/75303—Shape of the pressing surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051—Forming additional members, e.g. dam structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent the unnecessary flow of solder at soldering a semiconductor chip on a supporting plate. CONSTITUTION:A metallic supporting plate 2 having at least first and second annular grooves 18, 19 are prepared. In a region enclosed by the first annular groove 18 of this metallic supporting plate, a semiconductor chip 24 is secured with solder 22 accompanying with scrub. An area of a scrub region 21 is set less than that of a region enclosed by a first annular groove 18. A resin seal body coating a supporting plate 12 to which the semiconductor chip 24 is secured is provided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はダイオード、トランジス
タ、ＩＣ等の樹脂封止型電子部品の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing resin-sealed electronic parts such as diodes, transistors and ICs.

【０００２】[0002]

【従来の技術及び発明が解決しようとする課題】半導体
素子をこの支持板と共に樹脂封止体で封止した樹脂封止
型半導体装置は周知である。この種の半導体装置におい
て、樹脂封止体と支持板の界面を通じて半導体素子の載
置された領域に水分等の不純物（異物）が侵入すると、
半導体装置の特性が低下する。そこで、本願発明者は、
半導体素子の載置された領域を囲む溝を支持板に設ける
試みをした。これにより、不純物の侵入を溝によって抑
制することができ、半導体装置の特性低下をそれなりに
防止することができた。しかしながら、今日、半導体装
置の高機能化等のためにチップ（半導体素子）の大型化
が進んでいる。このため、チップを支持板に固着する半
田が溝に流れ込むことがあり、溝の不純物侵入防止効果
が低減することがあった。2. Description of the Related Art A resin-encapsulated semiconductor device in which a semiconductor element is encapsulated with a resin encapsulant together with this support plate is well known. In this type of semiconductor device, when impurities (foreign matter) such as moisture enter the region where the semiconductor element is mounted through the interface between the resin sealing body and the support plate,
The characteristics of the semiconductor device are degraded. Therefore, the inventor of the present application
Attempts have been made to provide a groove in the support plate that surrounds the mounting area of the semiconductor element. As a result, the intrusion of impurities can be suppressed by the groove, and the deterioration of the characteristics of the semiconductor device can be prevented to some extent. However, today, the size of chips (semiconductor elements) is increasing due to higher functionality of semiconductor devices. Therefore, the solder that fixes the chip to the support plate may flow into the groove, and the effect of preventing impurities from entering the groove may be reduced.

【０００３】そこで、本発明はろう材の不要な流れを防
ぐことができる電子部品の製造方法を提供することを目
的とする。Therefore, an object of the present invention is to provide a method of manufacturing an electronic component which can prevent unnecessary flow of a brazing material.

【０００４】[0004]

【課題を解決するための手段】上記目的を達成するため
の本発明は、第１の環状溝と該第１の環状溝を包囲する
第２の環状溝とを有し、前記第１の環状溝で包囲された
領域には電子素子をスクラブしてろう接するためのスク
ラブ領域を有し、前記第１の環状溝で包囲された領域は
前記スクラブ領域よりも大きい面積を有している導電性
支持板を用意する工程と、前記スクラブ領域にろう材を
供給し、前記ろう材の上に前記電子素子を載置し、前記
スクラブ領域内において前記電子素子を前記ろう材を介
してスクラブすることによって前記電子素子を前記スク
ラブ領域内にろう付けする工程と、前記電子素子と前記
第１の環状溝と前記第２の環状溝を含むように前記支持
板を被覆する樹脂封止体を設ける工程とを有することを
特徴とする樹脂封止型電子部品の製造方法に係わるもの
である。The present invention for achieving the above object comprises a first annular groove and a second annular groove surrounding the first annular groove, and the first annular groove is provided. The region surrounded by the groove has a scrub region for scrubbing and brazing the electronic device, and the region surrounded by the first annular groove has a larger area than the scrub region. Preparing a support plate, supplying a brazing material to the scrub region, placing the electronic element on the brazing material, and scrubbing the electronic element in the scrub region via the brazing material Brazing the electronic element into the scrub region by means of: and providing a resin encapsulant covering the support plate so as to include the electronic element, the first annular groove and the second annular groove. Resin seal characterized by having Those related to the manufacturing method of the type electronic component.

【０００５】[0005]

【作用】本発明によれば、電子素子が支持板の第１の環
状溝の内側に配設されたスクラブ領域内にろう付けされ
る。スクラブ領域は第１の環状溝で包囲された領域より
も小さく設定されており、電子素子はこのスクラブ領域
内でスクラブ運動を伴なってろう付けされる。したがっ
て、ろう材が第１の環状溝よりも外側に流れ出すことが
有効に抑制される。このため、第１の環状溝の外側に配
設された第２の環状溝が異物侵入防止用の溝として有効
に作用する。According to the present invention, the electronic element is brazed into the scrub region located inside the first annular groove of the support plate. The scrubbing area is set smaller than the area surrounded by the first annular groove, and the electronic element is brazed in this scrubbing area with a scrubbing movement. Therefore, the brazing material is effectively suppressed from flowing out of the first annular groove. Therefore, the second annular groove arranged outside the first annular groove effectively acts as a foreign matter intrusion preventing groove.

【０００６】[0006]

【実施例】次に、図１〜図４を参照して本発明の一実施
例に係わる樹脂封止型半導体装置の製造方法を説明す
る。EXAMPLE A method of manufacturing a resin-sealed semiconductor device according to an example of the present invention will be described below with reference to FIGS.

【０００７】まず、図２に示すリードフレーム１１を用
意する。このリードフレーム１１は放熱板を兼ねる比較
的厚い金属製支持板１２と、この支持板１２の一方の端
部側に配置された比較的薄い板状外部リード１３と、支
持板１２の他方の端部側に配置された比較的薄い板状支
持リード１４と、外部リード１３及び支持リード１４を
連結する比較的薄い細条１５、１６、１７から構成され
ている。実際のリードフレームでは、細条１５、１６、
１７の延びる方向（横方向）に複数の支持板１２が並設
されて全体として梯子形状となっている。しかしなが
ら、図２では図面を簡略化して支持板１２を１個のみ示
す。First, the lead frame 11 shown in FIG. 2 is prepared. The lead frame 11 includes a relatively thick metal support plate 12 that also serves as a heat dissipation plate, a relatively thin plate-shaped outer lead 13 arranged on one end side of the support plate 12, and the other end of the support plate 12. It is composed of a comparatively thin plate-like support lead 14 arranged on the side of the section and comparatively thin strips 15, 16 and 17 connecting the external lead 13 and the support lead 14. In the actual lead frame, strips 15, 16,
A plurality of support plates 12 are juxtaposed in the extending direction (lateral direction) of 17 to form a ladder shape as a whole. However, in FIG. 2, only one support plate 12 is shown to simplify the drawing.

【０００８】支持板１２の一方の主面の中央側には、内
側から順番に第１の環状溝１８と第２の環状溝１９と第
３の環状溝２０が互いに離間して配設されている。第１
の環状溝１８の内側にはチップをスクラブ（こすりつ
け）運動を伴なって固着するためのスクラブ領域（チッ
プ載置予定領域）２１が第１の環状溝１８から離間した
位置に配設されている。第１の環状溝１８で包囲された
領域の面積はスクラブ領域２１の面積よりも大きい。即
ち第１の環状溝１８の一辺の長さはチップのスクラブ領
域２１の一辺の長さよりも大きく設計されている。第
１、第２及び第３の環状溝１８、１９、２０はリードフ
レーム１１を形成するための一連のプレス加工において
同時に形成したものである。A first annular groove 18, a second annular groove 19 and a third annular groove 20 are arranged in this order from the inside on the center side of one main surface of the support plate 12 so as to be spaced apart from each other. There is. First
A scrub region (chip mounting area) 21 for fixing the chip with a scrub (rubbing) motion is disposed inside the annular groove 18 at a position separated from the first annular groove 18. .. The area of the region surrounded by the first annular groove 18 is larger than the area of the scrub region 21. That is, the length of one side of the first annular groove 18 is designed to be larger than the length of one side of the scrub region 21 of the chip. The first, second and third annular grooves 18, 19 and 20 are formed simultaneously in a series of press workings for forming the lead frame 11.

【０００９】次に、支持板１２にチップを半田付けする
ために、支持板１２のスクラブ領域２１にろう材として
の半田２２を加熱溶融状態且つ膜状に広げる。続いて、
図１に示すチップ吸着保持体（以下、コレットと称す
る）２３を用意して、固着すべき電子素子としての半導
体チップ２４をコレット２３の空間に対応する壁面２５
に吸着させる。続いて、図示のようにスクラブ領域２１
のほぼ中央位置において半田２２の上にチップ２４を押
し付けた後、矢印２６で示す左右方向にチップ２４をコ
レット２３と共に直線往復運動（スクラブ運動）させて
チップ２４を半田２２で固着する。チップ２４をスクラ
ブ領域２１の幅即ちコレット２３を第１の環状溝１８の
一方の辺側に移動させたときのチップ２４の他方の側縁
の位置Ａとコレット２３を第１の環状溝１８の他方の辺
側に移動させたときのチップ２４の他方の側縁の位置Ｂ
との間隔Ｌ１は、第１の環状溝１８の一辺の長さＬ2 よ
りも小さくなっている。スクラブ領域２１の外側に流れ
た半田２２は第１の環状溝１８に収容され、半田２２が
第１の環状溝１８よりも外側に広がることが阻止され
る。Next, in order to solder the chip to the supporting plate 12, the solder 22 as a brazing material is spread in a film state in a scrub region 21 of the supporting plate 12 in a heating and melting state. continue,
A chip suction holder (hereinafter referred to as collet) 23 shown in FIG.
Adsorb to. Then, as shown in FIG.
After the chip 24 is pressed onto the solder 22 at approximately the center position of the chip 24, the chip 24 is linearly reciprocated (scrubbed) together with the collet 23 in the left-right direction indicated by the arrow 26 to fix the chip 24 with the solder 22. When the tip 24 is moved to the width of the scrub region 21, that is, the collet 23 is moved to one side of the first annular groove 18, the position A of the other side edge of the tip 24 and the collet 23 are moved to the first annular groove 18. Position B of the other side edge of the chip 24 when moved to the other side
The distance L1 between the first and second annular grooves 18 is smaller than the length L2 of one side of the first annular groove 18. The solder 22 that has flowed to the outside of the scrub region 21 is contained in the first annular groove 18, and the solder 22 is prevented from spreading outside the first annular groove 18.

【００１０】図３のように、チップ２４が半田２２を介
してスクラブ領域２１内のチップ載置領域（中央領域）
に固着されたら、周知のワイヤボンディング法によって
チップ２４と外部リード１３との間にリード細線２７を
図２に示すように接続する。続いて、シリコン樹脂等か
ら成る保護樹脂２８をチップ２４の上面に滴下して、図
３のようにチップ２４とリード細線２７のチップ２４へ
の接続部分側を被覆する。保護樹脂２８の一部は第１の
環状溝１８よりも外側まで広がるが、第２の環状溝１９
が保護樹脂２８の流れ留めとして機能するから、保護樹
脂２８は第２の環状溝１９よりも外側には広がらない。As shown in FIG. 3, the chip 24 has a chip mounting region (central region) in the scrub region 21 via the solder 22.
Once fixed, the lead wire 27 is connected between the chip 24 and the external lead 13 by a well-known wire bonding method as shown in FIG. Subsequently, a protective resin 28 made of silicon resin or the like is dropped on the upper surface of the chip 24 to cover the connecting portion side of the chip 24 and the lead thin wire 27 to the chip 24 as shown in FIG. Although part of the protective resin 28 extends to the outside of the first annular groove 18, the second annular groove 19
Serves as a flow stop for the protective resin 28, so that the protective resin 28 does not spread outside the second annular groove 19.

【００１１】次に、リードフレーム１１とチップ２４と
リード細線２７から成る組立体を成形用型（図示せず）
に配置して、周知のトランスファモールド法によって、
図２で破線で示すように支持板１２の全面と外部リード
１３及び支持リード１４の一部を被覆する樹脂封止体２
９を形成する。最後に、細条１５、１６、１７と支持リ
ード１４を除去することによって、図４に示す樹脂封止
型半導体装置を完成させる。なお、支持リード１４の引
抜き破断によって、樹脂封止体２９に孔３０が生じる
が、極めて小さいのでほとんど問題にならない。この孔
３０は必要に応じて樹脂で埋められる。Next, an assembly consisting of the lead frame 11, the chip 24 and the lead wire 27 is formed into a molding die (not shown).
By the well-known transfer mold method,
As shown by a broken line in FIG. 2, a resin sealing body 2 that covers the entire surface of the support plate 12 and a part of the external leads 13 and the support leads 14.
9 is formed. Finally, the strips 15, 16, 17 and the support leads 14 are removed to complete the resin-sealed semiconductor device shown in FIG. It should be noted that the holes 30 are formed in the resin sealing body 29 due to the pull-out breakage of the support leads 14, but since it is extremely small, there is almost no problem. This hole 30 is filled with resin as needed.

【００１２】本実施例では、チップ２４が第１の環状溝
１８の内側に半田付けされ且つスクラブ領域の幅Ｌ1 が
第１の環状溝１８の一辺の長さＬ2 よりも小さく設定さ
れている。したがって、チップ２４を支持板１２に固着
するための半田２２の流れ出しが有効に防止される。In the present embodiment, the chip 24 is soldered inside the first annular groove 18 and the width L1 of the scrub region is set to be smaller than the length L2 of one side of the first annular groove 18. Therefore, the solder 22 for fixing the chip 24 to the support plate 12 is effectively prevented from flowing out.

【００１３】また、保護樹脂２８の外側への流れ出しも
第２の環状溝１９によって留められている。結果とし
て、異物侵入防止用の第３の環状溝２０に半田２２や保
護樹脂２８が入り込むことが防止され、第３の環状溝２
０による異物侵入防止効果が強力に得られる。したがっ
て、樹脂封止型半導体装置の長期使用による特性低下を
許容レベル以下に収めることができる。The outward flow of the protective resin 28 is also stopped by the second annular groove 19. As a result, the solder 22 and the protective resin 28 are prevented from entering the third annular groove 20 for preventing foreign matter intrusion, and the third annular groove 2 is prevented.
The effect of preventing foreign matter intrusion by 0 is strongly obtained. Therefore, the characteristic deterioration due to the long-term use of the resin-encapsulated semiconductor device can be kept within the allowable level.

【００１４】[0014]

【変形例】本発明は上述の実施例に限定されるものでは
なく、例えば次の変形が可能なものである。MODIFICATION The present invention is not limited to the above-mentioned embodiments, and the following modifications are possible.

【００１５】スクラブの運動方向は実施例に限られな
い。例えば、チップ２４の中心点を軸として円運動させ
てもよい。この場合、第１の環状溝１８で包囲された面
積は、この円運動によってチップ２４の端部で描かれる
円の面積よりも大きくし、且つスクラブ領域２１を第１
の環状溝１８から離間させた中央側に配設する。The movement direction of the scrub is not limited to the embodiment. For example, circular movement may be performed with the center point of the tip 24 as an axis. In this case, the area surrounded by the first annular groove 18 is made larger than the area of the circle drawn at the end portion of the tip 24 by this circular movement, and the scrub region 21 is made into the first area.
It is arranged on the center side separated from the annular groove 18.

【００１６】第１の環状溝１８及び第２の環状溝２０の
断面形状はＶ字形状でなくても良い。例えば、第１の環
状溝１８を図５のように２段階の凹部で形成し、この境
界に突出部を設け、半田の流れ留め効果を増大させても
よい。The sectional shapes of the first annular groove 18 and the second annular groove 20 do not have to be V-shaped. For example, the first annular groove 18 may be formed as a two-step concave portion as shown in FIG. 5, and a protruding portion may be provided at this boundary to increase the solder flow stopping effect.

【００１７】第１、第２及び第３の環状溝１８、１９、
２０を完全に閉じた環状溝にせずに、仮想環状線に沿っ
て断続的に形成しても異物侵入防止の効果はそれなりに
得られる。したがって、第１、第２及び第３の環状溝１
８、１９、２０は実質的に環状であればよい。また、第
２及び第３の環状溝１９、２０のいずれか一方を省くこ
とができる。The first, second and third annular grooves 18, 19,
Even if 20 is not formed as a completely closed annular groove but is formed intermittently along the virtual annular line, the effect of preventing foreign matter intrusion can be obtained to some extent. Therefore, the first, second and third annular grooves 1
8, 19, 20 may be substantially annular. Further, either one of the second and third annular grooves 19 and 20 can be omitted.

【００１８】[0018]

【発明の効果】本発明によって水分等の異物の侵入を防
止でき、長期間にわたって特性変動の生じない信頼性の
高い電子部品を提供することができる。Industrial Applicability According to the present invention, it is possible to provide a highly reliable electronic component which can prevent foreign matter such as moisture from entering and which does not cause characteristic fluctuations over a long period of time.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例に係わる樹脂封止型半導体装置
の製造方法を図２のＡ−Ａ線に対応する部分で示す断面
図である。FIG. 1 is a cross-sectional view showing a method of manufacturing a resin-sealed semiconductor device according to an embodiment of the present invention at a portion corresponding to line AA in FIG.

【図２】実施例のリードフレームを示す平面図である。FIG. 2 is a plan view showing a lead frame of an example.

【図３】支持板上にチップを半田付けし、保護樹脂を設
けた状態を示す断面図である。FIG. 3 is a cross-sectional view showing a state in which a chip is soldered on a support plate and a protective resin is provided.

【図４】完成した半導体装置を示す断面図である。FIG. 4 is a sectional view showing a completed semiconductor device.

【図５】変形例の支持板を示す平面図である。FIG. 5 is a plan view showing a support plate of a modified example.

【符号の説明】[Explanation of symbols]

１１ リードフレーム １２ 支持板 １３ 外部リード １８ 第１の環状溝 １９ 第２の環状溝 ２０ 第３の環状溝 ２４ チップ ２２ 半田 11 lead frame 12 support plate 13 external lead 18 first annular groove 19 second annular groove 20 third annular groove 24 chip 22 solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 第１の環状溝と該第１の環状溝を包囲す
る第２の環状溝とを有し、前記第１の環状溝で包囲され
た領域には電子素子をスクラブしてろう接するためのス
クラブ領域を有し、前記第１の環状溝で包囲された領域
は前記スクラブ領域よりも大きい面積を有している導電
性支持板を用意する工程と、 前記スクラブ領域にろう材を供給し、前記ろう材の上に
前記電子素子を載置し、前記スクラブ領域内において前
記電子素子を前記ろう材を介してスクラブすることによ
って前記電子素子を前記スクラブ領域内にろう付けする
工程と、 前記電子素子と前記第１の環状溝と前記第２の環状溝を
含むように前記支持板を被覆する樹脂封止体を設ける工
程とを有することを特徴とする樹脂封止型電子部品の製
造方法。1. A first annular groove and a second annular groove that surrounds the first annular groove, and a region surrounded by the first annular groove is to be scrubbed with an electronic device. Preparing a conductive support plate having a scrub region for contact, the region surrounded by the first annular groove having a larger area than the scrub region; and brazing material in the scrub region. Supplying, placing the electronic element on the brazing material, and brazing the electronic element in the scrub area by scrubbing the electronic element in the scrub area through the brazing material; A step of providing a resin sealing body that covers the support plate so as to include the electronic element, the first annular groove, and the second annular groove. Production method.
JP3061282A 1991-02-28 1991-02-28 Electronic component manufacturing method Expired - Fee Related JP2857648B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3061282A JP2857648B2 (en) 1991-02-28 1991-02-28 Electronic component manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3061282A JP2857648B2 (en) 1991-02-28 1991-02-28 Electronic component manufacturing method

Publications (2)

Publication Number Publication Date
JPH05235228A true JPH05235228A (en) 1993-09-10
JP2857648B2 JP2857648B2 (en) 1999-02-17

Family

ID=13166692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3061282A Expired - Fee Related JP2857648B2 (en) 1991-02-28 1991-02-28 Electronic component manufacturing method

Country Status (1)

Country Link
JP (1) JP2857648B2 (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06163773A (en) * 1992-11-19 1994-06-10 Goto Seisakusho:Kk Lead frame for semiconductor device and its manufacture
US6753596B1 (en) 2002-12-06 2004-06-22 Mitsubishi Denki Kabushiki Kaisha Resin-sealed semiconductor device
DE102004046699A1 (en) * 2004-09-24 2006-04-13 Infineon Technologies Ag Contact surfaces e.g. cooling unit, connecting device, has contact surfaces connected by solidifying liquid e.g. melted solder, such that section of one of two surface edges exhibits structuring in area of edges
JP2007165714A (en) * 2005-12-15 2007-06-28 Renesas Technology Corp Semiconductor device
JP2008053478A (en) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd Lead frame, package component, manufacturing method thereof, and semiconductor device
JP2011077286A (en) * 2009-09-30 2011-04-14 Shindengen Electric Mfg Co Ltd Semiconductor package and method for manufacturing the same
JP2017510991A (en) * 2014-03-26 2017-04-13 ヘレウス ドイチェラント ゲーエムベーハー ウント カンパニー カーゲー Support and / or clip for semiconductor element, semiconductor component, and manufacturing method
JP2018029201A (en) * 2017-10-13 2018-02-22 ローム株式会社 Semiconductor device
JP2018067613A (en) * 2016-10-19 2018-04-26 三菱電機株式会社 Die pad, semiconductor device, and semiconductor device manufacturing method
CN109623071A (en) * 2017-10-06 2019-04-16 肖特股份有限公司 Matrix and its manufacturing method and purposes with soldering grounding pin
JP2019062245A (en) * 2019-01-29 2019-04-18 ローム株式会社 Semiconductor device
US10777542B2 (en) 2014-03-04 2020-09-15 Rohm Co., Ltd. Power semiconductor module for an inverter circuit and method of manufacturing the same

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06163773A (en) * 1992-11-19 1994-06-10 Goto Seisakusho:Kk Lead frame for semiconductor device and its manufacture
DE10335622B4 (en) * 2002-12-06 2009-06-04 Mitsubishi Denki K.K. Resin-sealed semiconductor device
US6753596B1 (en) 2002-12-06 2004-06-22 Mitsubishi Denki Kabushiki Kaisha Resin-sealed semiconductor device
CN1331224C (en) * 2002-12-06 2007-08-08 三菱电机株式会社 Resin packaging semiconductor device
DE102004046699A1 (en) * 2004-09-24 2006-04-13 Infineon Technologies Ag Contact surfaces e.g. cooling unit, connecting device, has contact surfaces connected by solidifying liquid e.g. melted solder, such that section of one of two surface edges exhibits structuring in area of edges
JP2007165714A (en) * 2005-12-15 2007-06-28 Renesas Technology Corp Semiconductor device
JP2008053478A (en) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd Lead frame, package component, manufacturing method thereof, and semiconductor device
JP2011077286A (en) * 2009-09-30 2011-04-14 Shindengen Electric Mfg Co Ltd Semiconductor package and method for manufacturing the same
US10777542B2 (en) 2014-03-04 2020-09-15 Rohm Co., Ltd. Power semiconductor module for an inverter circuit and method of manufacturing the same
JP2017510991A (en) * 2014-03-26 2017-04-13 ヘレウス ドイチェラント ゲーエムベーハー ウント カンパニー カーゲー Support and / or clip for semiconductor element, semiconductor component, and manufacturing method
JP2018067613A (en) * 2016-10-19 2018-04-26 三菱電機株式会社 Die pad, semiconductor device, and semiconductor device manufacturing method
CN109623071A (en) * 2017-10-06 2019-04-16 肖特股份有限公司 Matrix and its manufacturing method and purposes with soldering grounding pin
US11205610B2 (en) 2017-10-06 2021-12-21 Schott Ag Base body with soldered-on ground pin, method for its production and uses thereof
JP2018029201A (en) * 2017-10-13 2018-02-22 ローム株式会社 Semiconductor device
JP2019062245A (en) * 2019-01-29 2019-04-18 ローム株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2857648B2 (en) 1999-02-17

Similar Documents

Publication Publication Date Title
US5637913A (en) Leadframe semiconductor integrated circuit device using the same and method of and process for fabricating the two
KR0134902B1 (en) Moisture relief for chip carriers
US6437429B1 (en) Semiconductor package with metal pads
US20050146057A1 (en) Micro lead frame package having transparent encapsulant
JPH08116016A (en) Lead frame and semiconductor device
JP2857648B2 (en) Electronic component manufacturing method
US6501160B1 (en) Semiconductor device and a method of manufacturing the same and a mount structure
US20020105072A1 (en) Integrated circuit package configuration having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body
US20020182773A1 (en) Method for bonding inner leads of leadframe to substrate
JP2861417B2 (en) Method for manufacturing resin-encapsulated electronic component
KR100237912B1 (en) Packaged semiconductor, semiconductor device made therewith and method for making same
KR100373891B1 (en) Semiconductor device and method of its fabrication
KR100333386B1 (en) chip scale package
JPS63293963A (en) Resin-sealed semiconductor device
KR100308899B1 (en) semiconductor package and method for fabricating the same
KR100252862B1 (en) Semiconductor package and method for fabricating the same
KR100244254B1 (en) Lead frame and semiconductor package with such lead frame
JPH09129812A (en) Semiconductor device
KR100460072B1 (en) Semiconductor Package
KR100244502B1 (en) Chip size package
JP2552885Y2 (en) Insulator-coated electronic components
KR0141945B1 (en) Semiconductor package and leadframe with heat sink
KR100370480B1 (en) Lead frame for semiconductor package
KR100206886B1 (en) Culumn type package
KR200316720Y1 (en) Ball grid array package

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees