JPS59112636A - Resin-sealed semiconductor device and manufacture thereof - Google Patents

Resin-sealed semiconductor device and manufacture thereof

Info

Publication number
JPS59112636A
JPS59112636A JP22210482A JP22210482A JPS59112636A JP S59112636 A JPS59112636 A JP S59112636A JP 22210482 A JP22210482 A JP 22210482A JP 22210482 A JP22210482 A JP 22210482A JP S59112636 A JPS59112636 A JP S59112636A
Authority
JP
Japan
Prior art keywords
resin
substrate
frame
semiconductor device
fluorine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22210482A
Other languages
Japanese (ja)
Inventor
Seietsu Tanaka
田中 誠悦
Katsumi Onari
大成 克己
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP22210482A priority Critical patent/JPS59112636A/en
Publication of JPS59112636A publication Critical patent/JPS59112636A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the quality of a resin-sealed semiconductor device by coating by a spraying method fluorine polymer in the prescribed frame shape on the surface of a substrate to be associated of an IC element and completely preventing the flowout of the sealing resin. CONSTITUTION:Fluorine polymer which is diluted with organic solvent is injected from a nozzle 10 through a metal mask 11 on a substrate 1, on which the prescribed circuit pattern is formed to form a frame of hollow rectangular shape. Solvent is evaporated at ambient temperature. The polymer density is 2% or less, the thickness of the frame is 1mum or less, and the flowout of the sealing resin 5 and the collapse of the shape can yet be prevented by utilizing the surface tension effect of the fluorine. Then, an IC element 2 is secured with adhesive 7, and wired via wirings 4. The substrate 1 is maintained at approx. 200 deg.C on a hot plate, and epoxy resin is placed on the wirings of the element. Then, the resin is liquefied to spread to become almost thicknessless in shape, stopped at the inner edge of the polymer 9, and not flowed out, thereby reducing the manufacturing cost.

Description

【発明の詳細な説明】 (技術分野) 本発明はトランスファー成形によらないペレット状又は
液状樹脂を用いてシールする樹脂シール型半導体装置及
びその製造方法に関し、詳しくはIC素子の組立基板に
おける封止樹脂の流れ出し防止手段に関するものである
Detailed Description of the Invention (Technical Field) The present invention relates to a resin-sealed semiconductor device that is sealed using a pellet or liquid resin that does not require transfer molding, and a method for manufacturing the same. This invention relates to means for preventing resin from flowing out.

(従来技術) 近年、IC素子が高集積化され、広い分野で使用される
ようになってからIC素子の組立、パッケージの形状も
多種にわたり、特に合成樹脂基板への組立てが盛んにな
りつつあるが、これはやはり市場のニーズとして混成I
C素子、時計玩具等の要求が増大している為と考えられ
、それだけにIC素子などの半導体装置の組立てに係る
コスト・ダウンの要望は根強い。
(Prior art) In recent years, as IC elements have become highly integrated and used in a wide range of fields, IC element assembly and package shapes have become diverse, and assembly on synthetic resin substrates has become particularly popular. However, this is still a hybrid I as a market need.
This is thought to be due to the increasing demand for C elements, watch toys, etc., and for this reason, there is a deep-rooted desire to reduce the cost of assembling semiconductor devices such as IC elements.

従来、この種の半導体装置としては、第1図に示す如き
ものがあった。すなわち、COB (チップ・オン・ボ
ード)などIC素子の組立基板において、樹脂によるシ
ール時にこの樹脂が流れ出さないようにする為、長方形
状の枠を設けて、これを流出防止用ダムとして使用する
ように構成されたものがあった。第1図(a)に示す如
く、1はガラ”ス、エポキシ(セームスリー、エファー
ルフオなト)等の合、成樹脂基板1で、これに後述のI
C素子3の組立が出来るように、回路配線2がメッキ技
術によりAuメッキ等でパターンニングされている。
Conventionally, there has been a semiconductor device of this type as shown in FIG. In other words, in order to prevent the resin from flowing out when sealing with resin on the assembly board of IC elements such as COB (chip on board), a rectangular frame is provided and used as a dam to prevent the resin from flowing out. There was something configured like this. As shown in FIG. 1(a), reference numeral 1 denotes a synthetic resin substrate 1 made of glass, epoxy, etc.
In order to be able to assemble the C element 3, the circuit wiring 2 is patterned with Au plating or the like using a plating technique.

第1図(I))は上述の第1図(a)に示す基板1上に
パターンニングされた回路配線2に基づいて組立てられ
た半導体装置を示す第1図(a)のX−X線側断面組立
図であって、図中、3はIC素子、4は上記基板1及び
IC素子2を接続する金又はアルミ線、5は上記基板1
上の所定位置に上記IC素子2をシールするシール用樹
脂部、6は上記シール用樹脂部5の流出防止用ダムとし
ての中空長方形状枠で、紙フェノール等の材料で形成さ
れる。7は上記IC素子2を上記基板1に貼着する接着
剤、8は上記枠7を上記基“板1に貼着する接着剤であ
る。
FIG. 1(I)) shows a semiconductor device assembled based on the circuit wiring 2 patterned on the substrate 1 shown in FIG. 1(a) above, taken along line X-X in FIG. 1(a). This is a side sectional assembly view, in which 3 is an IC element, 4 is a gold or aluminum wire connecting the substrate 1 and the IC element 2, and 5 is the substrate 1.
A sealing resin part 6 for sealing the IC element 2 at a predetermined position on the top is a hollow rectangular frame serving as a dam for preventing the sealing resin part 5 from flowing out, and is made of a material such as paper phenol. Reference numeral 7 indicates an adhesive for bonding the IC element 2 to the substrate 1, and reference numeral 8 indicates an adhesive for bonding the frame 7 to the substrate 1.

以上の構成を備えたものにおいて、基板1にIC素子2
をグイスボンデイングする工程の前後、又はワイヤーボ
ンディングする工程の後で、シール用樹脂部5が規定の
面積ではみ出さないようにするため長方形状の枠6を紙
フェノール等の材料で作り、これを接着剤8で基板1へ
貼着し、乾燥した後にシール用樹脂で成形し、この枠6
で流出防止用のダムとし、上記樹脂部5の流れ出しを防
止するようにしていた。そして、この後にキュアを行い
、捺印し、電気的特性試験などを行い製品としていた。
In a device having the above configuration, an IC element 2 is mounted on a substrate 1.
A rectangular frame 6 is made of a material such as paper phenol in order to prevent the sealing resin part 5 from protruding over a specified area before and after the step of wire bonding or after the step of wire bonding. is pasted on the substrate 1 with adhesive 8, and after drying is molded with sealing resin, this frame 6
A dam was used to prevent the resin portion 5 from flowing out. After this, it was cured, stamped, and tested for electrical characteristics before being made into a product.

以上の如く中空長方形状枠6を使用すること力・ら、従
来装置及びその製造方法には次の如き欠点が有った。
In addition to the use of the hollow rectangular frame 6 as described above, the conventional device and its manufacturing method have the following drawbacks.

(1)枠6は、例えば紙フェノールの板をプレスで打ち
抜いて作製するので枠6に係る材料費、加工費がそれだ
け割高となったこと。
(1) Since the frame 6 is manufactured by punching out, for example, a paper phenol board with a press, the material and processing costs associated with the frame 6 are correspondingly higher.

(2)枠6を基板1に接着するときは、該枠6の何箇所
かに接着剤8を塗布して接着し、次いで硬イヒのために
乾燥を行うので該接着剤8に係る加工費が割高となった
こと。
(2) When adhering the frame 6 to the substrate 1, the adhesive 8 is applied to several places on the frame 6 and then dried to harden it, so the processing cost related to the adhesive 8 became relatively expensive.

(3)枠6に接着剤8を塗布しても、基板1と枠6の間
にどうしても隙曲が出来て全面にうまく接着できないた
め、ベレット、液状樹脂を流じ込んでも枠6外へ洩れ出
すことが有り、これが外観不良のみならず他の配線パタ
ーンに達して接触不良を起こす恐れがあったこと。
(3) Even if the adhesive 8 is applied to the frame 6, there will inevitably be gaps between the substrate 1 and the frame 6, and the entire surface will not be properly bonded, so even if a pellet or liquid resin is poured, it will leak outside the frame 6. There was a risk that this would not only cause poor appearance, but also reach other wiring patterns and cause poor contact.

(4)自動化の行われにくい形状がらして構成上接着剤
塗り用、枠付は用の機構を具備する必要が有り、又機種
交換時にヘッドの交換再調整を行うので、それだけ設備
費が高価なものとなったこと。
(4) Due to its shape, which is difficult to automate, it is necessary to have a mechanism for applying adhesive and for attaching a frame, and the head must be replaced and readjusted when changing the model, which increases equipment costs. That it became something.

上記の如き欠点が歩留りに影響するため、総じてコスト
高の原因となり、また品質低下の原因となるという大き
な欠点となっていた。
Since the above-mentioned defects affect the yield, they are a major drawback in that they cause overall cost increase and quality deterioration.

(発明の目的) 本発明は上記欠点を解消するためになされたもので、I
C素子の組立基板表面にフッソ系ポリマーをスプレーの
方法で所定の枠状に塗布させる構成により、シール用樹
脂の流れ出しを完全に防止して品質向上を実現すると共
に、簡単な製造方法の改良で顕著な製造コストダウンを
図ることが出来る樹脂シール型半導体装置及びその製造
方法を提供することを目的とするものである。
(Object of the invention) The present invention has been made in order to eliminate the above-mentioned drawbacks, and is
By spraying fluorine-based polymer onto the surface of the C-element assembly board in a predetermined frame shape, it is possible to completely prevent the sealing resin from flowing out and improve quality, while also making it possible to improve the manufacturing method easily. It is an object of the present invention to provide a resin-sealed semiconductor device and a method for manufacturing the same, which can significantly reduce manufacturing costs.

(実施例) 以下、本発明の一実施例を図面を参照しながら説明する
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第2図は本発明の一実施例による樹脂シール型半導体装
置を示すもので、第2図は第1図(]))相当図であり
、図中、第1図と同一符号は同一部分、又は相当部分を
示し、その詳細な説明を省く。
FIG. 2 shows a resin-sealed semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram corresponding to FIG. Otherwise, a corresponding portion will be shown and detailed explanation thereof will be omitted.

図において、9は上記基板1上に形成芒れシール用樹脂
部5の流出防止用として機能するフッソ系ポリマーの長
方形枠状塗布部で、その塗布された厚みは1μm以下程
度のものである。
In the figure, reference numeral 9 denotes a rectangular frame-shaped coated part of a fluorocarbon polymer which functions to prevent the awn sealing resin part 5 formed on the substrate 1 from flowing out, and the coated thickness thereof is about 1 μm or less.

以上の構成を備えた本発明の一実施例において、フッソ
系ポリマーの長方形枠状塗布部9はごく僅かの塗布量で
、フッソの表面張力効果をう1〈利用した構成により、
シール用樹脂部5の流れ出しや形くずれを完全に防止で
き、該樹脂部ψC素子3を完全に接着しシールすること
が出来る。
In one embodiment of the present invention having the above configuration, the rectangular frame-shaped coating portion 9 of the fluorinated polymer can be coated in a very small amount, and the surface tension effect of the fluorinated polymer can be further utilized.
It is possible to completely prevent the sealing resin part 5 from flowing out or deforming, and the resin part ψC element 3 can be completely bonded and sealed.

次に、本発明の一実施例による上記半導体装置の製造方
法について説明する。
Next, a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described.

第3図は本発明の一実施例によるフッソ系ポリマーのス
フ0レ一式塗布方法を示すものであって、10Uフツン
系ポリマー希釈液を上記基板1上の長方形枠状塗布部9
にスプレーするスプレー用ノズル11は長方形状枠を中
空にして上記基板1上の塗布部9と上記ノズル10との
垂直方向中間部の所定位置にセットされるスプレー用メ
タルマスクである。
FIG. 3 shows a method for coating a fluorine-based polymer with a fluorine-based polymer diluted solution according to an embodiment of the present invention.
The spray nozzle 11 for spraying is a metal mask for spraying, which has a hollow rectangular frame and is set at a predetermined position vertically midway between the application section 9 and the nozzle 10 on the substrate 1.

以上の構成を備えたものにおいて、所定の回路パターン
を形成しておいた基板lにスプレー用メタルマスク11
を介して、スプレー用ノズル10からフッソ系ポリマー
(例えば商品名でF’C−721フロラード)を有機溶
剤(商品名でFC−77フロリナート)で希釈し、これ
をスプレーして中空長方形状に塗布する。この有機溶剤
は常温で蒸発するので、特に乾燥は必要としない。又、
フッソ系ポリマーの濃度は2%以下なので、塗布される
厚みも1μm以下であるが、これでも十分上記シール用
樹脂部5の流れ止め機能を果たすことが可能である。塗
布後、IC素子2ダイスを接着前の接着剤7である導電
性ペースト又は絶縁性樹脂を用すて上記基板1上の所定
位置にダイスボンデングを行った後、硬化全目的に乾燥
を行う。次に、金線又はアルミ線4をワイヤーボンダー
で張り、シール工程に入る。シール工程では、葦ず基板
1をホットプレート上で200℃近くに加熱させておき
、シール材エポキシ樹脂iBステージ化させたベレット
(本出願人はこれ−iEペレットと呼んでいる)を素子
配線上に置くと、これは数秒後に溶融し、液状になって
広がり、最終的に第2図に示す如く、殆んど厚みのない
形状で塗布したフッソ系ポリマー9の内側エッヂで正寸
る。これはフッソ系ポリマーのもつ廃水性特性で樹脂を
はじく性質があるためである。このようにシールされた
基板lはシール用樹脂部5の完全なキュアを目的として
乾燥され、捺印をし、電気的特性をテスティングして完
成品となる。
In the device having the above configuration, a metal mask 11 for spraying is applied to a substrate l on which a predetermined circuit pattern has been formed.
A fluorine-based polymer (for example, F'C-721 Fluorado under the trade name) is diluted with an organic solvent (FC-77 Fluorinert under the trade name) from the spray nozzle 10 through the spray nozzle 10, and this is sprayed to apply it in a hollow rectangular shape. do. Since this organic solvent evaporates at room temperature, no particular drying is required. or,
Since the concentration of the fluorine-based polymer is 2% or less, the applied thickness is also 1 μm or less, which is sufficient to prevent the sealing resin portion 5 from flowing. After coating, the IC element 2 dice are bonded to a predetermined position on the substrate 1 using the conductive paste or insulating resin that is the adhesive 7 before bonding, and then dried for the purpose of curing. . Next, a gold wire or aluminum wire 4 is stretched with a wire bonder, and a sealing process begins. In the sealing process, the reed substrate 1 is heated to nearly 200°C on a hot plate, and a pellet made of sealing material epoxy resin iB stage (which the applicant calls an iE pellet) is placed on the element wiring. After a few seconds, it melts, turns into a liquid, spreads out, and finally reaches the correct size at the inner edge of the fluorine-based polymer 9, which has been applied in a shape with almost no thickness, as shown in FIG. This is because fluorine-based polymers have wastewater properties that repel resins. The thus sealed substrate 1 is dried for the purpose of completely curing the sealing resin portion 5, stamped, and tested for electrical characteristics to become a completed product.

なお、上記実施例では、スプレー力式による塗布材とし
てフッソ系ポリマーを用いたが、本出願人がこのフッソ
系ポリマーの材料に到達する迄、シリコーン、或いはソ
ルダー、レジストなど数多くの樹脂を検討した結果いず
れも流れ出し“を食い止めることは出来ず、逐にこのフ
ッソ系ポリマーで本、目的を達成させることが出来たの
である。
In the above example, a fluorine-based polymer was used as a coating material using a spray force method, but the applicant investigated many resins such as silicone, solder, and resist before arriving at this fluorine-based polymer material. As a result, they were unable to stop the "flowing out" and were eventually able to achieve their goal using this fluorine-based polymer.

以上の如く、本発明の一実施例による半導体装置の製造
方法によれば、次のような優れた実用的効果と共に犬な
る経済的効果が得られる。
As described above, according to the method of manufacturing a semiconductor device according to an embodiment of the present invention, the following excellent practical effects and significant economic effects can be obtained.

(1)材料費を安価に出来る。(1) Material costs can be reduced.

2Xのフッソ系ポリマー溶液をさらに2倍から7倍程度
に稀釈して用いるので安価となる。本出願人の計算では
フェノール製枠に比較して材料源(dfiだけで115
〜1/10のコストになる。
Since the 2X fluorine polymer solution is further diluted to about 2 to 7 times, it is inexpensive. Applicant's calculations show that the material source (dfi alone) is 115% compared to the phenolic frame.
~1/10 the cost.

・(2)加工費を安価に出来る。・(2) Processing costs can be reduced.

従来の方法では流出防止用粋の何箇所かに接着剤を塗布
しなければならないが、本実施例ではスプレーで瞬時に
塗布するので、その必要がない。
In the conventional method, it is necessary to apply adhesive to several places on the leakage prevention tip, but in this embodiment, it is applied instantly by spraying, so there is no need for this.

(3)フッソ系ポリマー稀釈液は中空長方形状に塗布さ
れるので、シール用樹脂部5の外部への流れ出しが全く
無く、品質、掛留りが極めて高い。
(3) Since the diluted fluorine polymer solution is applied in a hollow rectangular shape, there is no flow out to the outside of the sealing resin part 5, and the quality and retention are extremely high.

(4)スプレーのみで、しかも1μmの厚みで樹脂止め
の効果があるので自動化が極めてやり易い条件を備えて
いる。
(4) Since the resin is effective only by spraying and has a thickness of 1 μm, it is extremely easy to automate.

(5)使用している溶剤が常温でも揮発するので、乾燥
の必要が無い。従って、この硬化乾燥は基板がゝソリ〃
を生じるような製品には特に優れた効果を与えることが
出来る。
(5) Since the solvent used evaporates even at room temperature, there is no need for drying. Therefore, during this curing and drying process, the substrate is warped.
Especially excellent effects can be given to products that produce .

なお、上記実施例ではIC素子単体のCOB (チップ
・オン・ボード)について説明したが、本発明によって
得られる効果は複数個塔載の回路基板に特に有効である
。すなわち、ICチップは1個、2個、3個と増えるに
従い枠付けに工数がががり、又自動化がしにくい。しか
し、本発明によれば1枚のマスクで1回でスプレーし塗
布できるので自動化し易く、又実装7感度を上げる場合
もマスクの形状変更で中空丸状、中空三角状にもシール
出来るので、隣接する回路又は部品に邪魔にならないよ
うな構成の設計も可能となる。他にレジンシールの必要
なLED 、サイリスク、トランジスタ、りイオード、
混成集積回路等の電子部品にも即応用可能であることか
らその用途は極めて広い。
In the above embodiment, a COB (chip on board) with a single IC element was described, but the effects obtained by the present invention are particularly effective for a circuit board having a plurality of IC elements mounted thereon. That is, as the number of IC chips increases from one to two to three, the number of man-hours required for framing increases, and it is difficult to automate the process. However, according to the present invention, it can be sprayed and applied in one go with one mask, making it easy to automate.Also, when increasing the mounting sensitivity, the shape of the mask can be changed to seal in a hollow round shape or a hollow triangular shape. It is also possible to design a configuration that does not interfere with adjacent circuits or components. Other LEDs that require resin seals, such as Cyrisk, transistors, and diodes,
Since it can be immediately applied to electronic components such as hybrid integrated circuits, its uses are extremely wide.

(発明の効果) 以上説明した通り、本発明によれはIC’素子の組立基
板表面に一フッソ系ポリマーをスプレーの方法で、所定
の枠状に塗布させる構成により、シール用樹脂の流れ出
しを完全に防止して品質向上を実現すると共に、簡単な
製造方法の改良で顕著な製造コストダウンを図ることが
出来るという犬なる実用的効果を奏する。
(Effects of the Invention) As explained above, according to the present invention, the flow-out of the sealing resin is completely prevented by applying the monofluorinated polymer in a predetermined frame shape to the surface of the IC' element assembly board by spraying. This has practical effects in that it is possible to improve quality by preventing problems, and to significantly reduce manufacturing costs by simply improving the manufacturing method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は従来の樹脂シール型半導体装置において
、各回路配線が基板にパターニングされたものの平面図
、第1図(b)は組立て後の従来装置を示す第1図のX
−X線側断面図、第2図は本発明の一実施例による樹脂
シール型半導体装置を示す第1図(b)相当図、第3図
は本発明の一実施例による上記半導体装置の製造方法を
示す工程説明図である。 1・・・合成樹脂基板、3・・・IC素子、4・・・金
又はアルミ線、5・・・シール用樹脂部、7・・・ダイ
スボンティング用接着剤、9・・・中空長方形状塗布部
、10・・・スプレー用ノズル、11・・・スプレー用
メタルマスク。 手続補正書 昭和58年丁θ月?、5日 特許庁長官若杉和夫 殿 1、事件の表示 昭和57年−特  許 願第222104   号2、
発明の名称 樹脂シール型半導体装置及びその製造方法3、補正をす
る者 事件との関係    特  許 出願人(029)沖電
気工業株式会社 4゜代理人 5、補正命令の日付  昭和  年  月  日(自発
)6、補正の対象 明細書の発明の詳細な説明の欄 7、補正の内容 別紙の通り 7、 補正の内容 1)明細書3頁13行、同頁14行および15行、同頁
18行、4頁1行および2行、8頁2行各々rIc素子
2」會rIC素子3」と訂正する。 2)同7頁6行および7行「ノズル」ケ「マスクJと訂
正する。 3)同8頁15行「廃水性」?「排水性」と訂正する。 IC
Fig. 1(a) is a plan view of a conventional resin-sealed semiconductor device in which each circuit wiring is patterned on a substrate, and Fig. 1(b) shows the conventional device after assembly.
- An X-ray side sectional view, FIG. 2 is a view corresponding to FIG. 1(b) showing a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 3 is a manufacturing of the above-mentioned semiconductor device according to an embodiment of the present invention. It is a process explanatory diagram showing a method. DESCRIPTION OF SYMBOLS 1... Synthetic resin substrate, 3... IC element, 4... Gold or aluminum wire, 5... Resin part for sealing, 7... Adhesive for die bonding, 9... Hollow rectangle 10... Spray nozzle, 11... Spray metal mask. Procedural amendment written in December 1980? , 5th, Kazuo Wakasugi, Commissioner of the Patent Office, 1, Indication of the case, 1981 - Patent Application No. 222104, 2,
Name of the invention: Resin-sealed semiconductor device and its manufacturing method 3; Relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4゜Representative 5; Date of amendment order Showa year, month, day (voluntary) ) 6. Column 7 for detailed explanation of the invention in the specification to be amended, Contents of the amendment as shown in attached sheet 7, Contents of the amendment 1) Specification, page 3, line 13, page 3, lines 14 and 15, page 18, line 1) , page 4, lines 1 and 2, and page 8, line 2, each corrected to read ``rIC element 2'' and ``rIC element 3''. 2) On page 7, lines 6 and 7, "Nozzle" is corrected to "Mask J." 3) On page 8, line 15, "Wastewater"? Corrected to "drainage". IC

Claims (2)

【特許請求の範囲】[Claims] (1)合成樹脂基板と、上記基板上に組立てられる■・
C素子と、上記IC素子を上記基板にシールするための
ベレット状又は液状樹脂部とを有する樹脂シール型半導
体装置において、上記基板上にフッソ系ポリマーのスプ
レーで所定形状枠に上記樹脂部の樹脂流れ出し防止手段
を形成したことを特徴とする樹脂シール型半導体装置。
(1) Synthetic resin substrate and ■ assembled on the above substrate
In a resin-sealed semiconductor device having a C element and a pellet-shaped or liquid resin part for sealing the IC element to the substrate, the resin of the resin part is sprayed onto the substrate in a predetermined shape by spraying a fluorine-based polymer. A resin-sealed semiconductor device characterized by forming a flow-out prevention means.
(2)ペレット状又は液状樹脂を用いてシールする樹脂
シール型半導体装置の製造方法において、フッソ系ポ゛
リマーを有機溶剤に混合溶解させ、これを所定のパター
ン枠を有するメタルマスクを介してスプレー、又は印刷
又はスタンピングにょす■c基板に上記パターン枠状に
付着塗布させた後、ベレット状樹脂又は液状樹脂を封止
剤として流込みを行い、上記フッソ系ポリマーの枠状付
着部で樹脂止めを行うようにしたことを特徴とする樹脂
シール型半導体装酷の製造方法。
(2) In a method for manufacturing a resin-sealed semiconductor device that uses pellet-like or liquid resin for sealing, a fluorine-based polymer is mixed and dissolved in an organic solvent, and this is sprayed through a metal mask having a predetermined pattern frame. , or by printing or stamping. After applying the above pattern on the substrate in the form of a frame, pour a pellet-like resin or liquid resin as a sealant, and seal the resin at the frame-like attachment part of the fluorine-based polymer. A method for manufacturing a resin-sealed semiconductor device, characterized by performing the following steps.
JP22210482A 1982-12-20 1982-12-20 Resin-sealed semiconductor device and manufacture thereof Pending JPS59112636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22210482A JPS59112636A (en) 1982-12-20 1982-12-20 Resin-sealed semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22210482A JPS59112636A (en) 1982-12-20 1982-12-20 Resin-sealed semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS59112636A true JPS59112636A (en) 1984-06-29

Family

ID=16777197

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22210482A Pending JPS59112636A (en) 1982-12-20 1982-12-20 Resin-sealed semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS59112636A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014216604A (en) * 2013-04-30 2014-11-17 シャープ株式会社 Manufacturing method of resin sealing object

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014216604A (en) * 2013-04-30 2014-11-17 シャープ株式会社 Manufacturing method of resin sealing object

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