JPS59108358A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59108358A
JPS59108358A JP21900582A JP21900582A JPS59108358A JP S59108358 A JPS59108358 A JP S59108358A JP 21900582 A JP21900582 A JP 21900582A JP 21900582 A JP21900582 A JP 21900582A JP S59108358 A JPS59108358 A JP S59108358A
Authority
JP
Japan
Prior art keywords
film
gate electrode
metal silicide
gate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21900582A
Other languages
Japanese (ja)
Other versions
JPH0157507B2 (en
Inventor
Shigeo Kashiwagi
柏木 茂雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21900582A priority Critical patent/JPS59108358A/en
Publication of JPS59108358A publication Critical patent/JPS59108358A/en
Publication of JPH0157507B2 publication Critical patent/JPH0157507B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Abstract

PURPOSE:To prevent metal atoms in a metal silicide film from diffusion into a gate SiO2 film in a heat treatment process necessary for formation of a semiconductor device after formation of a gate electrode by a method wherein the gate electrode is constructed of the nitrogen compound of a metal silicide. CONSTITUTION:The ions of P or As atoms of N type impurity atoms are implanted to a P type Si substrate 2 demarcated by element isolating SiO2 films 1 to form a source region 3 and a drain region 4. A gate electrode 6 patterned in the prescribed shape and consisting of the compound film of a metal silicide such as MoSi2 and nitrogen is formed on the Si substrate 2 interposing a gate insulating SiO2 film 5 between them. As the metal silicide, in addition to MoSi2, WSi2 and TaSi2 are also favorable. When the gate electrode is formed in such a way, transference of metal elements such as Mo, W, Ta constructing the metal silicide film according to nitrogen can be controlled even by a heat treatment after formation of the gate electrode, and accordingly diffusion in the gate oxide film can be checked.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明はMIS型牛型体導体装置良に関するものである
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an MIS type bovine conductor device.

(b)  技術の背景 電子機器に用いられるMIS型IO,MIS型LSI等
のMIS型半導体装置は高速に動作することが要求され
ており、そのため〜(Is型ドブンジスタのゲート電極
として、−低抵抗の高いポリシリコン電極に代って電気
抵抗の低いモリブデンシリサイド(MoSi2)やタン
グステンシリサイド(WSi2)のような高融点の金属
シリサイド電極が用いられるようになってきている。
(b) Background of the technology MIS type semiconductor devices such as MIS type IO and MIS type LSI used in electronic equipment are required to operate at high speed. Metal silicide electrodes with high melting points, such as molybdenum silicide (MoSi2) and tungsten silicide (WSi2), which have low electrical resistance, are being used instead of polysilicon electrodes with high resistance.

(C)  従来技術と間頭点 ところでこのような金属シリサイド膜をMIS型半導体
装置のゲート電極として使用した場合、前記ゲート電極
を形成後該ゲート電極をマスクとしてソース領域および
ドレイン領域形成用不純物をシリコン(Si)基板にイ
オン注入後、基板を熱処理する工程や、ゲート醸極、ソ
ース領域、ドレイン領域形成後基板上に燐硅酸ガラス(
PSG)膜を形成後、熱処理する工程がある。このよう
な熱処理工程で金属シリサイドのゲート電極計のゲート
8i(h膜中に、金属シリサイド膜中のモリブデン(M
o)やタングステン(W)等の金属が拡散する現象が生
じ、このためゲー)Sin2膜の耐圧が劣化し、したが
って形成されるMIS型半導体装社の特性が悪くなると
いった不都合を生じる。
(C) Comparison with the prior art By the way, when such a metal silicide film is used as a gate electrode of an MIS type semiconductor device, after forming the gate electrode, impurities for forming a source region and a drain region are added using the gate electrode as a mask. After ion implantation into a silicon (Si) substrate, there is a step of heat-treating the substrate, and after forming the gate electrode, source region, and drain region, phosphosilicate glass (
After forming the PSG film, there is a step of heat treatment. In such a heat treatment process, molybdenum (M
A phenomenon occurs in which metals such as O) and tungsten (W) are diffused, and this causes problems such as deterioration of the withstand voltage of the Ga)Sin2 film and, therefore, deterioration of the characteristics of the formed MIS type semiconductor device.

(d)  発明の目的 本発明はと述した問題点を除去し、金属シリサイド膜を
用いてMTS型半導体装置のゲート電極を形成した場合
、ゲート電極形成後の装置形成に必要な熱処理工程で、
金属シリサイド膜中の金属原子が、ゲー)8i02膜中
へ拡散しないような半導体装置の提供を目的とするもの
である。
(d) Purpose of the Invention The present invention eliminates the above-mentioned problems, and when a gate electrode of an MTS type semiconductor device is formed using a metal silicide film, in a heat treatment step necessary for device formation after forming the gate electrode,
The object of the present invention is to provide a semiconductor device in which metal atoms in a metal silicide film do not diffuse into the Ga)8i02 film.

(e)  発明の構成 かかる目的を達成するための本発明の半導体装置は、ソ
ース領域、ドレイン領域、ゲート絶縁膜及びゲート電極
を具備するM i S型半導体装置の前記ゲート1jL
極が金属シリサイドの窒素化合物から成ることを特徴と
するものである。更に前記ゲート1!極が金属シリサイ
ドの窒素化合物膜及び金にシリサイド膜を順次積層して
形成されていることを特徴とするものである。
(e) Structure of the Invention A semiconductor device of the present invention for achieving the above object is a semiconductor device of the M i S type semiconductor device comprising a source region, a drain region, a gate insulating film, and a gate electrode.
It is characterized in that the electrode is made of a nitrogen compound of metal silicide. Furthermore, the gate 1! It is characterized in that the electrode is formed by sequentially laminating a nitrogen compound film of metal silicide and a silicide film on gold.

(f)  発明の実施例 以下図面を用いながら不発明の一実施例につき詳細に説
明する。
(f) Embodiment of the Invention An embodiment of the invention will be described in detail below with reference to the drawings.

第1図は本発明の半導体装置の構造を示す断面図で、第
2図は該装置を形成するための装置aの概略図である。
FIG. 1 is a sectional view showing the structure of a semiconductor device of the present invention, and FIG. 2 is a schematic diagram of an apparatus a for forming the device.

図示する様に本発明の半導体装置は素子間分離用8i0
2膜1で画定されたP型のS+基板2にN型の不純物原
子である燐(P)または砒素(As)原子がイオン注入
されてソース領域8およびドレイン領域4が形成されて
いる。そして該81基板4上にゲート用5iQ2膜5を
介して所定の形状にパターニングされたMo8i2のよ
うな金属シリサイドと窒素の化合物膜よりなるゲート電
極6が形成されている。この金属シリサイドとしてはM
o8i2の他にws I2やタンタルシリサイド(’I
’aSi2)であっても良い。このように鷲属シリサイ
ドと窒素との化合物膜によりゲート電極を形成すれば、
該ゲート電極を形成後の熱処理によっても金属シリ基 サイド膜を横路するMO,W、Taのような金属元素が
窒素によって移動するのが抑制され従ってゲート酸化膜
中に拡散するのを防止することができ、ゲート酸化膜の
耐圧劣化を生じない高耐圧のMIS型半導体装置を形成
することができる。
As shown in the figure, the semiconductor device of the present invention has an 8i0
A source region 8 and a drain region 4 are formed by ion-implanting phosphorus (P) or arsenic (As) atoms, which are N-type impurity atoms, into a P-type S+ substrate 2 defined by two films 1. A gate electrode 6 made of a compound film of metal silicide such as Mo8i2 and nitrogen is formed on the 81 substrate 4 through a 5iQ2 film 5 for gate use, which is patterned into a predetermined shape. As this metal silicide, M
In addition to o8i2, ws I2 and tantalum silicide ('I
'aSi2). If the gate electrode is formed from a compound film of silicide and nitrogen in this way,
The heat treatment after forming the gate electrode also suppresses the movement of metal elements such as MO, W, and Ta that cross the metal silicide-based side film due to nitrogen, thereby preventing them from diffusing into the gate oxide film. This makes it possible to form a high breakdown voltage MIS type semiconductor device that does not cause deterioration of the breakdown voltage of the gate oxide film.

またこの他の実施例として前記ゲート電極の電気抵抗を
低下させるために、ゲート電極の下の部分を金属シリサ
イド膜の窒素化合物膜で形成して、金属シリサイド膜中
の金属原子がゲート酸化膜中に拡散するのを防止し、ゲ
ート電極の上の部分を金属シリサイド膜で形成した二層
構造のゲート電極としても良い。
In another embodiment, in order to reduce the electrical resistance of the gate electrode, the lower part of the gate electrode is formed with a nitrogen compound film of the metal silicide film, so that the metal atoms in the metal silicide film are absorbed into the gate oxide film. The gate electrode may have a two-layer structure in which the upper part of the gate electrode is formed of a metal silicide film.

このような半導体装置を形成するには、第1図に示すよ
うにP型のB+基板1上に素子間分離用の8i(h膜2
を基板を熱酸化することによや形成する。次いでゲート
用5102膜を基板の熱酸化法により形成した後、該基
板2を第2図に示すスパッタ装置の容器11中の基板設
置台り上に設置する。
To form such a semiconductor device, as shown in FIG. 1, an 8i (h film 2
is formed by thermally oxidizing the substrate. Next, after a gate 5102 film is formed by thermal oxidation of the substrate, the substrate 2 is placed on a substrate mounting stand in a container 11 of a sputtering apparatus shown in FIG.

次いで該容器]1内を10  Torr程度に排気孔詔
より排気したのち、ガス導入孔14より5〜6容量%の
窒素ガスが添加されているアルゴン(Ar)ガスを導入
する。その後基板設置台12をアース電位としMOター
ゲット15および81ターゲツト16に負の高電圧を印
加してArガスをイオン化し、該Arガスをスパッタ用
ガスとしてターゲットをスパッタして基板上にMo5i
zの窒素化合物膜を形成する。
Next, the inside of the container [1] is evacuated to about 10 Torr through the exhaust hole, and then argon (Ar) gas to which 5 to 6% by volume of nitrogen gas is added is introduced through the gas introduction hole 14. Thereafter, the substrate mounting table 12 is set to ground potential, and a negative high voltage is applied to the MO target 15 and 81 target 16 to ionize the Ar gas, and the target is sputtered using the Ar gas as a sputtering gas to deposit Mo5i on the substrate.
A nitrogen compound film of z is formed.

次に該基板上にホトレジスト膜を塗布したのち、該レジ
スト膜を写真蝕刻法およびプラズマエツチング法により
所定のパターンに形成する0次に該パターニングされた
レジスト膜をマスクとして例えば四塩化炭素(01!4
)ガス等をエツチング用ガスとして用いてプラズマエツ
チング法によって、前記Mo8i2の窒素化合物膜を所
定のパターンに形成してゲート電極とする。その後この
ようにパターニングされたゲート電極をマスクとして基
板上にASまたはP原子をイオン注入してソース領域8
およびドレイン領域4を形成する。
Next, a photoresist film is applied on the substrate, and then the resist film is formed into a predetermined pattern by photolithography and plasma etching.The patterned resist film is used as a mask, for example, carbon tetrachloride (01!). 4
) The Mo8i2 nitrogen compound film is formed into a predetermined pattern by a plasma etching method using etching gas or the like as an etching gas to form a gate electrode. After that, using the gate electrode patterned in this way as a mask, AS or P atoms are ion-implanted onto the substrate to form the source region 8.
and drain region 4 is formed.

(g)  発明の効果 以上述べたように本発明の半導体装置によれば、ゲート
酸化膜中にゲー)!極を形成する金属シリサイド膜の金
属原子が拡散するのが防止され耐圧の高いゲート酸化膜
が得られ、特性の良好な半導体装置が得られる利点を生
じる。
(g) Effects of the Invention As described above, according to the semiconductor device of the present invention, the gate oxide film contains G! This has the advantage that metal atoms in the metal silicide film forming the electrode are prevented from diffusing, a gate oxide film with high breakdown voltage is obtained, and a semiconductor device with good characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

筑I俯は木感叩の半這伏紡督の漕ルル箒ネ鮪占図、第2
図は本発明の牛導体装置を形成するのに用いる装置の概
略図である。 図においてlは素子間分離用8102膜、2はSi基板
、8はソース領域、4はドレイン領域、5はゲート用5
in2膜、6はM OS + 2と窒素との化合物より
なるゲート電極、11は容藷、栓は基板設置台ζmは排
気口、14はガス導入孔、15けMOツタ−ット、16
はSiターゲットを示す。 第1図 第2図 275−
Chiku I-kun is a map of half-crying spinners with wooden handles, 2nd edition.
The figure is a schematic diagram of the equipment used to form the bovine conductor device of the present invention. In the figure, l is an 8102 film for element isolation, 2 is a Si substrate, 8 is a source region, 4 is a drain region, 5 is a gate 5
in2 film, 6 is a gate electrode made of a compound of MOS + 2 and nitrogen, 11 is a container, the plug is a substrate installation stand ζm is an exhaust port, 14 is a gas introduction hole, 15 is a MO tube, 16
indicates a Si target. Figure 1 Figure 2 275-

Claims (2)

【特許請求の範囲】[Claims] (1)  ソース領域、ドレイン領域、ゲート絶縁膜及
びゲート電極を具備するMIS型半導体装置の前記ゲー
ト電極が金属シリサイドの窒素化合物から成ることを特
徴とする半導体装置。
(1) A MIS type semiconductor device comprising a source region, a drain region, a gate insulating film, and a gate electrode, wherein the gate electrode is made of a nitrogen compound of metal silicide.
(2)前記ゲート電極が金属シリサイドの窒票化合吻膜
及び金属シリサイド膜を順次極層して形成されているこ
とを特徴とする特許請求の範匣第(1)項に記載の午導
不装置。
(2) The meridional non-conductor according to claim 1, wherein the gate electrode is formed by sequentially forming a nitride film of metal silicide and a metal silicide film. Device.
JP21900582A 1982-12-13 1982-12-13 Semiconductor device Granted JPS59108358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21900582A JPS59108358A (en) 1982-12-13 1982-12-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21900582A JPS59108358A (en) 1982-12-13 1982-12-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59108358A true JPS59108358A (en) 1984-06-22
JPH0157507B2 JPH0157507B2 (en) 1989-12-06

Family

ID=16728766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21900582A Granted JPS59108358A (en) 1982-12-13 1982-12-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59108358A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213075A (en) * 1985-07-10 1987-01-21 Nec Corp Semiconductor device
JPS6254960A (en) * 1985-09-04 1987-03-10 Nec Corp Mis field effect transistor
JPS62124772A (en) * 1985-11-26 1987-06-06 Hitachi Ltd Semiconductor device
JPS62203370A (en) * 1986-03-03 1987-09-08 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS63174371A (en) * 1987-01-13 1988-07-18 Nec Corp Field-effect transistor
JP2000183329A (en) * 1998-10-08 2000-06-30 Sony Corp Semiconductor device and manufacture of the same
JP2007335891A (en) * 1997-03-31 2007-12-27 Freescale Semiconductor Inc Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213075A (en) * 1985-07-10 1987-01-21 Nec Corp Semiconductor device
JPS6254960A (en) * 1985-09-04 1987-03-10 Nec Corp Mis field effect transistor
JPS62124772A (en) * 1985-11-26 1987-06-06 Hitachi Ltd Semiconductor device
JPS62203370A (en) * 1986-03-03 1987-09-08 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device
JPS63174371A (en) * 1987-01-13 1988-07-18 Nec Corp Field-effect transistor
JP2007335891A (en) * 1997-03-31 2007-12-27 Freescale Semiconductor Inc Semiconductor device
JP2000183329A (en) * 1998-10-08 2000-06-30 Sony Corp Semiconductor device and manufacture of the same

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Publication number Publication date
JPH0157507B2 (en) 1989-12-06

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