JPS59107540A - Semiconductor device with wiring connection part using silicide - Google Patents

Abstract

PURPOSE:To enable to perform a connecting work using a small area and a small stepping by a method wherein a poly Si connection part, consisting of poly Si containing N type impurities and P type impurities, is lined with a metal silicide. CONSTITUTION:Transistors 1 and 2 of P type and N type are provided on an N type Si substrate 12, and a doping is performed on gates 2 and 6 and they are formed into P and N types. The connected parts of the gates 2 and 6 are exposed by providing an aperture on an insulating film 11, the above is covered by an Mo thin film, and P-ions are implanted. An MoSi2 film 15 is formed by having a knockon phenomenon, and the gates 2 and 6 are connected. The Mo film 13 is removed, and the semiconductor device is completed. According to this constitution, an N type poly Si layer and a P type poly Si layer can be ohmic-contacted using the least possible area and the smallest possible stepping.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device such as 4441. The present invention relates to a semiconductor device having a structure in which polycrystalline silicon (hereinafter referred to as polysilicon) arrangements s of different types are provided and wiring layers thereof are connected to each other.

In recent years, there has been a strong demand for semiconductor devices to have low power consumption, and for this reason complementary insulated gate field effect semiconductor devices (hereinafter referred to as CMO8) have been widely used. This C
An example of a large-scale integrated circuit (hereinafter referred to as LSI) using MO8 is as follows.

When CMO8 is used in a MOS LSI, it becomes an inverter circuit or a basic circuit as shown in FIG. This inverter circuit has an input by shorting the gate 2 of the P-type transistor 1 and the gate 6 of the N-type transistor 5, and an output by shorting the source 3 of the P-type transistor 10 and the drain 8 of the N-type transistor 5. be. FIG. 2 shows a layout of the P-type transistor 1 and the N-type transistor 5 of the circuit shown in FIG. 1 on a silicon chip.

When making a P-type transistor 1 here, after making a polysilicon gate 2, the source 3 and drain 4 of the transistor are diffused or ion-implanted using the gate 2 as a mask. P-type impurities will be introduced. Furthermore, since the same process is used to make the N-type transistor 5, N-type impurities are introduced into the polysilicon gate 6 of the N-type transistor. Therefore, when shorting the gate 2 of the P-type transistor and the gate 6 of the N-type transistor to form the inverter circuit shown in FIG. 1, it is not possible to directly connect these two gates.

Therefore, in the prior art, aluminum giant (hereinafter referred to as A/) wiring was used for connection as shown in Figure 3. However, this method requires less space for the Al wiring;
The difference in height also increases, which will become a disadvantage as microfabrication progresses in the future.

Therefore, the present invention has developed polysilicon containing n-type impurities and P.
The present invention provides a new structure in which polysilicon containing type impurities is connected ohmically while taking up as little space as possible and reducing steps.

The feature of the present invention is that polysilicon with P-type impurities and n
A semiconductor device in which a connecting portion of polysilicon containing type impurities is backed with metal silicide. To apply this structure to the silicon gate CMO8, when connecting the gate of the P-type transistor and the gate of the N-type transistor, the entire transistor is covered with an insulating film, and then the insulating film at the connection part is removed by selective etching. After the connection part is exposed, a thin high-melting point gold ingot, such as molybdenum or tungsten, is applied to the entire surface, and then,
A semiconductor device fabrication method is used in which the connecting portion is selectively made into metal silicide, the gate of a P-type transistor and the gate of an N-type transistor are ohmically connected, and then the defective melting point metal maple is removed. is desirable.

According to the present invention, polysilicon with n-type impurities and P
By adopting a structure in which the connection portion of polysilicon containing type impurities is backed with metal silicide, an ohmic connection is achieved, allowing connection to take up less space and with smaller steps.

Hereinafter, one embodiment of the present invention will be described in detail using the drawings. Figures 4 to 9 show 0MO8LS of an embodiment of the present invention.
It is a partial cross-sectional view of step I.

Figure 4: N-type silicon base &
P-type transistor 1. An N-type transistor 2 is provided. In this manufacturing process, the gate 2 of the P-type transistor is doped to P-type, and the gate 6 of the N-type transistor is doped to N-type. An insulating film 11 is placed over these transistors.
It is recognized by

FIG. 5: Next, selective etching is applied to the insulating film 11 to remove the insulating film at the connection portion between the gate 2 of the P-type transistor and the gate 6 of the N-type transistor.

FIG. 6: After that, a thin molybdenum layer 13 is placed on the chip.
I will investigate. The connection portion between the gate 2 of the P-type transistor and the gate 6 of the N-type transistor is connected without intervening the insulating film 11.
It is in contact with the molybdenum layer 13. Also, the molybdenum layer 13 used here must be very thin.

FIG. 7: Thereafter, phosphorus or boron ions are implanted into the entire surface of the chip, and the molybdenum layer 13 is bombarded with ions 14.

FIG. 8; Then, due to the knock-on phenomenon, the molybdenum layer 13 is directly in contact with the gate 2 of the P-type transistor.
Molybdenum atoms enter these polysilicon layers at the connection portion between the gate 6 and the gate 6 of the N-type transistor, and molybdenum silicide 15 forms @P! The gate 2 of the III transistor and the gate 6 of the N-type transistor are ohmically connected.

FIG. 9: The molybdenum on the insulating layer 11 is then removed by etching to complete the ohmic connection.

Note that instead of bombarding the molybdenum layer with ions, there is also a method of heating it at a low temperature to form molybdenum silicide, and even if a metal such as tungsten is used as a base for molybdenum, the process of the present invention can be used.

Based on the above, it is inevitable that the degree of integration of MO8LSI will further increase in the future, and that strict microfabrication will be required. The manufacturing method has a very high utility value (G).

[Brief explanation of the drawing]

Figure 1 is an example of a CMOS inverter circuit, Figure 2 is a plan view of the CfVIO8 in the middle of the process of the circuit in Figure 1,
FIG. 3 is a sectional view of a conventional CMOS in which aluminum and connection parts are formed on the equipment shown in FIG. . In addition, k in the figure, l... P-type transistor, 2
゜6...gate, 3,7...source,
4, 8...Drain, 5...N type transistor, 9...P well, 10...
Aluminum wiring, 11...Insulating film, 12...
... Nu silicon substrate, 13 ... Molybdenum layer, 14 ... Phosphorus or boron ion, 15.
...Molybdenum silicide. Mistake / Diagram

Claims (1)

[Claims] In a semiconductor device 1A in which a single-conductor type polycrystalline silicon fat layer and a reverse-type polycrystalline silicon wiring layer are provided on a substrate,
The - conductivity type polycrystalline silicon wiring layer and the 1eiJ conductivity type polycrystalline silicon wiring layer are connected to each other, and the contact second [
A bull monument device horn having a wiring connection part using silicide, characterized in that a silicide layer is provided on the - conductive 14L type polycrystalline silicon wiring layer of one part and the reverse conductivity type polycrystalline silicon wiring layer. .