JPS59107537A - Master slice type integrated circuit group - Google Patents

Abstract

PURPOSE:To contrive accomplishment of the layout design of the titled integrated circuit group in a highly efficient manner by a method wherein the channel width of the wiring located between functional blocks of the first kind and second kind master slice type ICs is variedly formed each other. CONSTITUTION:In two kinds of master slice type chips (a) and (b), the quantity of cell 1' in X and Y directions, which can be contained in one circuit functional block, is limited to P-pieces and q-pieces, and the blocks 3' and 4' are limited in size. The intercell distances l' and m' are made equal between the two chips (a) and (b) at the limit value or below, the group 5 consisting of the number of cells within the limit value is considered as 1 unit, and the intergroup distances (h), (i), (j) and (k) are independently established in the amount required for the chips (a) and (b). According to this constitution, circuit functional blocks can be used common between a plurality of master slice type ICs. Also, as cell groups are formed common in size, they can be made into macroscopic form by performing an interconnection, thereby enabling to obtain a layout structure suitable for multilayer automatic design.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate array type mask slice integrated circuit group that can accommodate a wide range of circuit scales.

In so-called gate arrays, which realize desired circuit functions on masked and sliced substrates, multiple types of master sliced substrates with different accommodating circuit sizes are prepared, especially when the circuit scale ranges from small to large. Ru. In other words, a mask/slice substrate with a large circuit scale capacity has a large tip size and a low wafer yield.
Since the cost per chip is high, the small number of times of cooking is 1.
Sui can be made to supply small masks and sliced substrates.

However, from the perspective of mask/slice board design, preparing multiple types of masks/slice boards in this way is difficult, even if the performance of the unit circuits is the same and the circuit size capacity is simply low. However, it is not possible to create a small chip by simply deleting a part of a thick chip, but by deleting a part and shrinking it by that amount, a new combination of bangs appears, and for that purpose, two types of masks and slices are needed. Difficulties such as the fact that the shapes of the batons that should be common between them end up being different from each other are usually involved.

In view of the above circumstances, it is an object of the present invention to provide a layout method for improving the efficiency of designing multiple types of mask/slice type chips with almost the same layout of unit circuits and different circuit scale capacities. , in the first type and second yuzu mask/slice type integrated circuits in which the mountable circuit f#A models are different from each other, the first type and the second mask/slice type integrated circuits are almost the same. It has a shaped circuit function block button,
Further, the width of the wiring channel region used for connection between the circuit devices N-Hypronoch is different between the first type mask slice type integrated circuit and the second type mask slice type integrated circuit.

The present invention will be explained below with reference to the drawings.

Figure 1 shows two types of masks with different circuit scale capacities.
This shows the cell layout of a sliced chip.
Figure (a) corresponds to a large-scale one, and Figure 1 (b) corresponds to a small-scale one, including transistors, resistors, etc. inside the tray.
It is composed of a cell 1, a wiring channel region 2, and 3, 4. are the circuit positions E7″ placed on the cell, respectively.
Showing lock.

The first feature of the present invention lies in the use of circuit functional blocks common to each of the two types of master slice type chips shown in FIG. 1(a) and Φ). , considering a circuit functional block using a plurality of cells 1, the inter-cell distance l in FIG.

It is necessary to keep the size of m the same between the two yuzu master slice chips. However, in the case of a small circuit, the width of the wiring channel region 2 for connecting circuit functional blocks to each other can be relatively small, so inter-cell interconnection QA is possible between the 28-mask slice type chips. , m are set to the same size, the chip shown in FIG. 1(b) suitable for small scale has an excessive wiring channel area V, which deteriorates the area efficiency of the chip.

In order to solve this problem, the first chip suitable for small scale t'<1
In (b), if the inter-cell distance l9m is reduced to the required amount, the circuit function block 4 cannot be used in common between the two types of mask/slice type chips. Although it is functional, it is necessary to create 17 separate 2-glaze circuit bimo-noh pro and kupatan that correspond to each mask and slice board individually. Normally, one circuit function is professional, and the circuit function is classified into tens of f! Considering the possible problems that may arise, this method is not at all good IL (no) from the point of view of circuit functional block button design.

In this paper, as shown in Fig. 2 (a) and (b), the size of the circuit function blocks 3' and 4' is
In order to set the J limit, a formation is established in the pllR:,Y
9 directions) Below the limit value, the distance between cells is 1
', rn' are set to the same size K between the two mask/slice chips, and the cell group 5 in the limit filter is defined as one C unit. It was decided that the mutual distances i, j, and k were set independently for only the necessary violet for each of the two master slice type chips to be set in HJ (a) and (b), respectively.

This is the second feature of the present invention. By doing so, it is possible to use circuit function blocks in common among multiple mask slice type integrated circuits without having to provide redundant RFJ channels. become.

In addition, in the cell layout form shown in the second example, the size of the cell group 5 is set in common to each of the mask and slice chip, so multiple circuit functional blocks are collected and mutually arranged within the size of the decell group 5. Since it is possible to connect it to a macro circuit function program, it has a layout structure suitable for hierarchical automatic design.

FIGS. 3(a) and 3(b) show an embodiment of the present invention, and the size of the circuit functional block 3" is not particularly limited in the X direction, and is 2 cells or less in the Y direction Fi. ing.

On the other hand, the size of the wiring channel region 2'' is the same as that of the cell group 5'.
The inside has a size of m'' and is set to the same size for each chip as shown in Fig. 3 (a) and (b), while the cell group 5
In the same embodiment, the wiring channel in the Y direction can pass directly over the cell 1, as shown in the second diagram.

The spacing indicated by j is not required.

As described above, the present invention contributes to the efficiency of chip baton design of multiple types of mask-sliced integrated circuits whose unit circuits have substantially the same performance but differ in circuit scale capacity, and
The present invention proposes a layout method suitable for hierarchical design without impairing chip area efficiency in each mask-sliced integrated circuit.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are plan views showing the cell layout of a conventional master slice type integrated circuit, and FIG. 2(a) is a plan view showing the cell layout of a conventional master slice integrated circuit.
. 3(b) is a plan view showing the cell layout of one embodiment of the present invention, and FIGS. 3(a) and 3(b) are plan views of other embodiments of the present invention. In the figure, 1. 1', 1"...cell, 2゜2', 2"...wiring channel area,
3.3', 3", 4゜4"...Circuit functional block, 5,5'...Cell group including a plurality of cells,
l, m... Relative distance between cells, 1'', l'', m
' , m''...Relative distance between cells within a cell group,
J F l's j+ l(+ ”...
- Relative distance between cell groups, p, q... Indicates the cell stage in the X direction and Y direction within the cell group, respectively. L-□-□) Shi-C--J'-)--------, ------. ::-111-is one---[

Claims (1)

[Claims] The first wire and the second wire have different circuit scales that can be used for
In the mask/slice type integrated circuit h1, each of the first and second master/slice type block circuits has a circuit function block having almost the same shape, and a circuit function block between the circuit function blocks. A group of mask slice type integrated circuits, characterized in that the inside of the wiring channel area used for connection is different between the first type and second master slice type integrated circuits.