JP3243421B2 - Automatic layout design method of master slice - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout design method for a master slice type semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, in the field of semiconductor integrated circuits, the production of many kinds and small quantities has been remarkable, and it is required to shorten the development and manufacturing period. Therefore, a master substrate in which transistors, resistors, capacitors and other underlying elements are formed in advance on a semiconductor substrate is prepared, and a plurality of types of semiconductor integrated circuits having different functions are realized by changing only the last wiring.
A so-called master slice method is employed. When designing a master slice type semiconductor integrated circuit, an automatic layout design using a computer is performed in which a base element on a master substrate is allocated to a circuit element and wired.

Conventionally, in an automatic layout design of the master slice system, a plurality of base element values are prepared by combining several transistor emitter sizes, resistance values, capacitance values, etc. on a master substrate, and the base element values are recommended. Provided to the designer as a value. The designer designs a circuit using these recommended values.

A specific example of a conventional automatic layout design method for a master slice will be described below with reference to FIGS.

FIG. 7 is a part of a circuit diagram to be designed for layout. In FIG. 7, the resistance elements 1 and
2 are designed to be 12 kΩ and 6 kΩ, respectively. Reference numerals 3 and 4 are transistors on the circuit.
As a master board on which this circuit is mounted, 1 kΩ, 5 k
Ω, 10kΩ resistance element, recommended value 12kΩ, 6
Consider a master substrate that contains both kΩ.

FIG. 8 shows a layout result by a conventional method based on element values. 1 kΩ resistance element 21A, 2
1B and a resistance element 21C of 10 kΩ are connected in series to
A 2 kΩ combined resistor 21 is realized, and a 1 kΩ resistor element 22
A and a resistance element 22B of 5 kΩ are connected in series and 6 kΩ
Is realized. Transistors 23 and 24 having a collector C, a base B and an emitter E are assigned to transistors 3 and 4 in FIG. 7, respectively, and combined resistors 21 and 22 are assigned to resistance elements 1 and 2 in FIG. 7, respectively. However, in the layout of FIG. 8, the combined resistor 21 and the transistor 23, which are preferably close to each other, are separated from each other. Further, since the combined resistors 21 and 22 are separated from each other, there is a high possibility that relative accuracy cannot be secured between the two combined resistors.

FIG. 9 is a circuit diagram obtained by modifying the circuit of FIG. 7 in order to solve these problems. According to FIG.
Resistance elements 1A and 1B of 6 kΩ obtained by changing the resistance element 1 of FIG.
Are connected in series with each other to create the same resistance value of 12 kΩ as that of the resistance element 1 on the circuit. As a result, the resistive elements 1A, 1B and 2 on the circuit of FIG. 9 are allocated with adjacent base elements in the same “combination of 1 kΩ and 5 kΩ” with the corresponding combination of base elements, so that relative accuracy is secured. However, it is easy to arrange them near the transistors 23 and 24.

[0008]

According to the above-mentioned conventional automatic layout design method, the following problems still occur.

First, the above-mentioned circuit change for the purpose of realizing a close layout and ensuring relative accuracy increases the burden on the designer. Particularly, in a typical analog IC circuit diagram, element values such as a resistance value and a capacitance value often take various numerical values, and when such a circuit element value is changed for a specific master substrate, the amount of work is increased. Becomes huge.

Next, even if the circuit is changed in accordance with a base element value that can be combined to realize a certain circuit element value, the combination of the base element values is limited. As a result, there is a possibility that a base element that is distant is allocated to a combination of circuit elements that are desired to be connected, resulting in a long wiring length.

Further, when there is a request to ensure relative accuracy between circuit elements, the base elements are laid out without considering the request, so that element groups having a request for relative accuracy can be arranged close to each other. However, the relative accuracy cannot be ensured in some cases. In this case, the circuit must be changed or the layout must be corrected by trial and error in consideration of the layout so as to satisfy the requirement of the relative accuracy.

An object of the present invention is to realize a close layout on a master substrate without changing a circuit.
Another object of the present invention is to provide an automatic layout design method of a master slice which can secure desired relative accuracy between required elements.

[0013]

In order to achieve the above-mentioned object, the present invention provides an automatic layout design method for a master slice by dividing an entire master substrate into a plurality of divided regions vertically and horizontally. In this configuration, an optimal base element is allocated in the divided area.

Specifically, a solution taken by the present invention is a first step of vertically and horizontally dividing the entire master substrate into a plurality of divided regions so as to include one priority underlying element of the same type, and A second step of allocating a priority underlayer element to each of the priority circuit elements that are the same type as the circuit element of the integrated circuit and of the same type as the priority underlayer element; and a priority step corresponding to each of the general circuit elements to be connected to the priority circuit element. And a third step of allocating an optimal combination of general base elements in the same divided region as the base element.

With the above arrangement, in the divided region including the priority underlying element, the priority underlying element and the general underlying element are arranged close to each other in order to allocate the optimum combination of the general underlying element to each of the general circuit elements. it can.

[0016]

[0017]

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a specific example of an automatic layout design method according to the present invention will be described with reference to the drawings.

FIG. 1 shows a part of a plan view of a master substrate on which the circuit shown in FIG.
7 includes transistor base elements 33 and 34 having a collector C, a base B, and an emitter E, respectively. The transistor base elements 33 and 34 are assigned to the transistor circuit elements 3 and 4 in FIG. 7 shows the results of the layout design method according to the present invention, in which the combined resistors 31 and 32 included in 35 and 36 are assigned to the resistance elements 1 and 2 in FIG. 7, respectively. In this specific example, the entire master substrate is vertically and horizontally divided into a plurality of divided regions so as to include one transistor base element as a priority base element in each divided area, and each of the transistor circuit elements as a priority circuit element is provided with a transistor. A base element is allocated, and to each of the general circuit elements to be connected to a certain transistor circuit element, an optimal combination of the general base elements in the same divided region as the transistor base element corresponding to the transistor circuit element is allocated. . According to FIG. 1, the divided region 3 including the transistor base element 33 which is the priority base element
5 out of 5 as 1 kΩ
Resistance elements 31A, 5kΩ resistance elements 31D and 31
E, a resistance element 31B of 1 kΩ is connected in series,
The combined resistance 31 of Ω is realized. Similarly, in the divided region 36 including the transistor base element 34 which is the priority base element, the optimum combination of the general base element is 1
A combined resistor 32 of 6 kΩ is realized by connecting a resistor 32 A of kΩ and a resistor 32 B of 5 kΩ in series.

According to the above example, the circuit elements included in FIG. 7, which is a circuit diagram designed without considering the recommended values and the underlying element values, are provided on the master substrate with a plurality of underlying elements to be connected to each other. Since elements are allocated in the same divided region, a short wiring length can be obtained. In addition, since the optimal combination of the base element values is assigned to the circuit elements, the circuit design can be performed without being conscious of the recommended values and the base element values. On the other hand, a plurality of types of master substrates can be used without changing the circuit, and shortage of a specific base element caused by biasing assignment of a specific base element value to a circuit element value can be avoided. Furthermore, a custom IC can be realized by using a base element by allocating a base element to a designed circuit element. Therefore, the circuit diagram information of the custom IC can be used as a database for designing a master slice type semiconductor integrated circuit.

If an optimum combination of general base elements cannot be assigned to a certain general circuit element within a certain division area, a new optimum one is added from adjacent unused division areas. An optimal combination of general base elements may be assigned again in the region.

In the above example, the entire master substrate is vertically and horizontally divided into a plurality of divided regions so that each divided region includes one transistor element as a priority base element. To form the master substrate, the entire master substrate may be divided vertically and horizontally so that one divided region includes a plurality of priority base elements. For example, when there are many circuit elements having twice the emitter size, it is effective to divide the master substrate so that one divided region includes two transistor elements.

FIG. 2 shows a flow of processing when the automatic layout design method according to the present invention is applied to a circuit to be designed.

First, in step S1, circuit diagram information (net list, circuit element values, etc.) of a circuit to be designed is input. In step S2, the element forming portion of the master substrate is divided into divided regions. At this time, in the element formation portion of the master substrate, the transistor base element is set as the priority base element. In addition, one divided region includes one of the transistor base elements, and another type of element (such as a resistor or a capacitor) near the transistor base element is included in the same divided region. In step S3, a transistor base element, which is a priority base element, is assigned to a transistor circuit element. At this time, an optimum priority base element is determined and assigned based on the relationship between the element value of the priority circuit element and the element value of the priority base element. For the transistor, for example, using an emitter size as an element value, a transistor having an emitter size corresponding to the value of the emitter current is determined as an optimal base element. In step S4, the processing priority is determined for each transistor.

At step S5, an assigned circuit element (transistor circuit element in this embodiment) which is a priority circuit element
A general circuit element, which is an element connected on a circuit, is extracted.
In step S6, it is determined whether a general circuit element has been extracted. If the extraction has failed, the process ends because no unassigned circuit elements remain.

If the extraction is successful, it is determined whether or not the general circuit element extracted in step S7 requires accuracy. If there is no accuracy requirement, in step S9a, a divided area to be assigned to each general circuit element is determined. At this time, the divided area including the priority underlying element corresponding to the priority circuit element is
The divided areas are assigned to general circuit elements connected to the priority circuit elements. In step S10a, the optimal combination of the general base elements is assigned to the general circuit elements so as to satisfy the circuit element values such as the resistance value and the capacitance value in the assigned divided area. At this time, the evaluation is performed using at least one of the positional relationship between the allocated divided area and another divided area, the type and element value of the underlying element included in the divided area, and the allocation state of other general circuit elements. Based on the function, an optimal combination of general base elements is quantitatively determined.

If it is determined in step S7 that there is a request for accuracy, an element group having a request for accuracy is extracted in step S8. In step S9b, the process proceeds to step S9a .
To determine the divided area to be assigned to each general circuit element.
As described above, the divided area to be allocated to the element group is determined . In step S10b, step S10
a , the resistance value and the capacitance within the allocated divided area
Circuit element values such as
Just as an appropriate combination is assigned to a general circuit element, an optimal combination of base elements is assigned to each general circuit element of an element group in the divided area.

In step S11a or S11b, it is determined whether a base element has been assigned to a circuit element in the divided area. If it is determined that the base element has been assigned, step S5
Then, the next general circuit element to be connected to the allocated circuit element is extracted. Step S11a or S11b
If it is determined that the area is not allocated in step S9a or S9b, the optimum area is added from the adjacent divided areas to form a new area, and the processing routine from step S10a or S10b is performed in the new area. Execute. When determining a divided region to be added in step S9a or S9b, the Manhattan distance to the center of the adjacent divided region, an element value ratio which is a ratio of an element value of a general circuit element to a base element value of the adjacent divided region, and a difference. When the circuit element value can be realized by mixing the general base elements configured in the layers, the additional divided area is quantitatively determined based on the evaluation function using at least one of the layer mixture degrees indicating the degree of the layer mismatch. To decide. For example, α × (Manhattan distance) + β × (element value ratio) + γ ×
(Layer mixture degree) + e is used. Here, α, β, γ, and e are weighting constants, and are determined by the designer according to which items are to be emphasized when determining the divided area to be added. According to the automatic layout design method according to the present invention, when assigning the optimal combination of the general base elements to the designed general circuit elements, the designer assigns the constants of the evaluation functions appropriately by using the evaluation functions. The selection can better reflect the requirements of the designer for the layout.

FIG. 3 shows an example of area division. In FIG. 3, reference numerals 41, 41,... Denote resistive elements on the master substrate, 42, a transistor element (transistor base element) on the master substrate, and 43, a capacitor on the master substrate. When the transistor is used as a priority base element, a middle line is drawn between the ends of the transistor 42 that are opposed to the right, upper, left, and lower adjacent transistors. A region surrounded by these four middle lines is a divided region including the transistor 42. The same operation is performed for each priority base element, and the entire master substrate is vertically and horizontally divided into a plurality of division areas so that each division area includes one priority base element.

FIG. 4 shows transistors t _{1 to} t ₃ and a resistor r
₁ ~r ₇ and out of the capacitor c _1, example when there is a request to be secured relative accuracy, circuit diagram resistors r ₄ and r ₅ and accuracy requirements group 54 between the resistor r ₄ and r ₅ Is shown. FIG. 5 shows a connection graph in which a node level is determined for each circuit element based on FIG. 4, and a branch indicating a connection relationship and an accuracy requirement is generated between each element. When the transistor priority circuit elements in FIG. 4, the collector C, r ₁ transistor group of t _1, t _2, t ₃ with emitter E is connected next section 51 of level 0, to the transistor group ~r 5 The resistance group of ₆ becomes the node 52 of the level 1,
Further, the resistor of r ₇ and the capacitor of c ₁ connected to the group of resistors form a node 53 of level 2. The resistors r ₄ and r ₅ are an accuracy request group 54. According to the circuit diagram and accuracy requirements, a branch 55 indicating a connection between the transistor t ₁ and the resistors r ₁ and r ₄ and a branch 55 indicating a connection between the resistors r ₄ and r ₇ are generated. Then, a branch indicating a connection relationship between other elements is generated. A branch 56 is generated between the resistors r ₄ and r ₅ to indicate the accuracy requirement.

FIG. 6 is a circuit diagram of the circuit shown in FIG.
In the case where there is a request to ensure relative accuracy between and, an element group having an accuracy requirement is arranged in the same divided area,
4 shows the results of the layout design method according to the present invention. 6, divided regions 45 and 46 obtained by dividing the master substrate vertically and horizontally include transistor base elements 43 and 44 having a collector C, a base B and an emitter E, respectively, and the transistor base elements 43 and 44 are priority circuit elements. FIG.
Of the transistors 3 and 4. The resistive elements 1 and 2 on the circuit of FIG. 7 having the required accuracy are extracted, and a divided area to be assigned is determined. In this case, there are two types of allocation candidate areas, 45 and 46. But,
Since the total circuit resistance which is the sum of the resistance values of the resistance elements 1 and 2 on the circuit in FIG. 7 is 18 kΩ, the resistance value cannot be realized in the divided region 46 having the total circuit resistance of 12 kΩ. On the other hand, since the divided area 45 has a total circuit resistance of 53 kΩ,
Are assigned to the resistance elements 1 and 2 on the circuit of FIG. In the divided region 45, a 1 kΩ resistance element 41A, a 5 kΩ resistance element 41D and a 41 kΩ resistance element 41B are connected in series to realize a combined resistance 41 of 12 kΩ.
A resistor 42A of 5Ω and a resistor 42B of 5kΩ are connected in series to realize a combined resistor 42 of 6kΩ, and the combined resistors 41 and 42 are assigned to the resistors 1 and 2 on the circuit of FIG. 7, respectively. Therefore, since the resistive elements 1 and 2 on the circuit are both formed of base elements that are close to each other in the same divided region, good relative accuracy can be ensured. If the optimum combination of the underlying elements cannot be assigned to a certain element group within a certain divided area, a new area obtained by adding the optimum one from adjacent unused divided areas is used again for the background. An optimal combination of elements may be assigned. According to the above example, for an element group having an accuracy requirement, the element group is formed of base elements that are close to each other in the same or adjacent divided regions, so that good relative accuracy can be ensured. it can.

In the above example, the exemplified evaluation function is used for determining an additional divided area. In addition, when base elements of different diffusion layer types are mixed on the master substrate, when handling circuit elements with very large element values, the distance between regions, the total element value for each diffusion layer type in the region In order to determine a region to be assigned to each element or each element group, an evaluation function employing the above as a variable can be used in step S9a or 9b in FIG.

Further, in the above-described example, the case of allocating to circuit elements by using the underlying element has been described, but a basic cell in which the underlying elements are combined may be used instead.

Further, in the above example, the case where the transistor base element is used as the reference for the region division has been described, but another base element may be used instead of the transistor. Further, when the element forming portion of the master substrate is configured by repeating the same shape by the same combination of the underlying elements,
It is also possible to divide the area in units of one of the repetitive shapes. In this case, the circuit is divided in consideration of the total value of the transistor emitter size, the total resistance value, the total capacitance value, and the like in one divided region, and each of the divided circuits corresponds to the divided region. A layout closer to a circuit image can be realized.

In the above example, the design target is an analog circuit, but the present invention can be applied to a digital circuit.

[0036]

As described above, according to the present invention, a base element is allocated to a priority circuit element and a general circuit element to be connected thereto within the same or close divided area on a master substrate. Therefore, it is possible to obtain a layout result in which the underlying elements corresponding to the priority circuit element and the general circuit element are wired in a short distance without changing the circuit diagram.

In addition, since a base element is assigned to an element group having an accuracy requirement on a circuit in the same or close divided area on the master substrate, it corresponds to each circuit element of the element group. A layout result in which the underlying elements are wired over a short distance can be obtained, and good relative accuracy can be secured between the elements of the element group without changing the circuit diagram.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of a wiring layout using an automatic layout design method according to the present invention.

FIG. 2 is a flowchart illustrating an automatic layout design method according to the present invention.

FIG. 3 is a plan view showing an example of area division of a master substrate.

FIG. 4 is a circuit diagram showing an example of an accuracy request.

FIG. 5 is a diagram showing a connection graph according to FIG. 4;

FIG. 6 is a plan view showing another example of a wiring layout using the automatic layout design method according to the present invention.

FIG. 7 is a circuit diagram showing an example of a layout design target.

FIG. 8 is a plan view showing an example of a wiring layout using an automatic layout design method according to a conventional example.

FIG. 9 is a circuit diagram after the change of FIG. 7;

[Explanation of symbols]

1 Resistive element on circuit (12 kΩ) 2 Resistive element on circuit (6 kΩ) 3, 4 Transistor on transistor (transistor circuit element) 31 Combined resistance (12 kΩ) 32 Combined resistance (6 kΩ) 31A, 31B, 32A On master substrate Resistance element (1
kD) 31D, 31E, 32B Resistance element (5
33, 34 Transistor base element 35, 36 Divided area on master substrate 41 Combined resistance (12 kΩ) 42 Combined resistance (6 kΩ) 41A, 41B, 42A Resistor element (1 on master substrate)
kD) 41D, 41E, 42B Resistance elements (5
43, 44 Transistor base element 45, 46 Divided area on master substrate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/118 H01L 21/82 G06F 17/50

Claims (7)

(57) [Claims] An automatic layout design method of a master slice for automatically allocating a base element formed in advance on the master substrate to a circuit element of a semiconductor integrated circuit so as to determine a layout on the master substrate. A first step of vertically and horizontally dividing the entire master substrate into a plurality of divided regions so as to include one priority underlying element of the same type; and a circuit element of the semiconductor integrated circuit, the same type as the priority underlying element. A second step of assigning a priority base element to each of the certain priority circuit elements; and a general process element to be connected to the priority circuit element.
A third step of allocating an optimal combination of a general base element in the same divided region as a corresponding priority base element. 2. The automatic layout design method for a master slice according to claim 1, further comprising a step of selecting a transistor as a priority underlying element. 3. The automatic layout designing method for a master slice according to claim 1, wherein the second step is performed based on a relationship between an element value of a priority circuit element and an element value of a priority underlying element. An automatic layout design method for a master slice, comprising a step of determining an element. 4. The automatic layout designing method of a master slice according to claim 1, wherein the third step comprises: a positional relationship between a divided region including a priority underlying element and another divided region;
A step of quantitatively determining an optimal combination of general base elements based on an evaluation function using at least one of the type and element value of the base element included in the divided region and the allocation state of another general circuit element An automatic layout design method for a master slice, comprising: 5. The method of automatically designing a master slice according to claim 1, wherein a general base element in the same divided region as a corresponding priority base element is assigned to a general circuit element to be connected to a certain priority circuit element. The automatic layout design method for a master slice, further comprising a step of adding an unused divided area adjacent to the divided area as an assignment target when the division cannot be performed. 6. The automatic layout design method for a master slice according to claim 5, wherein the element is a distance to a center of an adjacent divided area, and a ratio between an element value of a general circuit element and a base element value of the adjacent divided area. Additional division based on an evaluation function using at least one of a value ratio and a layer mixture degree indicating a degree that layers do not match when a circuit element value can be realized by mixing general base elements configured in different layers. An automatic layout design method for a master slice, comprising a step of quantitatively determining an area. 7. An automatic layout design method for a master slice for automatically assigning a base element formed in advance on the master substrate to a circuit element of a semiconductor integrated circuit so as to determine a layout on the master substrate. A step of vertically and horizontally dividing the entire master substrate into a plurality of divided regions; and, for an element group consisting of a plurality of circuit elements having an accuracy requirement to ensure relative accuracy, a sum of circuit element values in the element group Allocating a combination of base elements in the same divided area so that the base element in the same divided area satisfies the above condition, wherein the combination of base elements is a Manhattan distance to the center of an adjacent divided area, In the element value ratio given the ratio of the element value of the general circuit element in the element and the element value of the base element in the adjacent divided region, or the general base element configured in a different layer An automatic layout design method for a master slice, characterized in that it is determined by a weighting evaluation function for each of the layer mixture degrees giving the degree of disagreement of layers when mixed.