JPH10135339A - Automatic layout wiring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an automatic layout wiring method which improves the design efficiency. SOLUTION: For designing an LSI by a hierarchical layout technique, the layout wiring is automatically designed for an undesigned module and designed module. In this wiring method a schematic wiring graph is prepared from the relative layout of the modules. For power feed cells, subsets of module are determined. The routes, wiring width, terminal positions of the undesigned module and directionality of the designed module are determined. Module interconnection regions are estimated and terminal positions of the undesigned module are determined.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing method in a floor planning step when performing hierarchical design in LSI design.

[0002]

2. Description of the Related Art In the above-mentioned LSI design, a circuit mounted on one chip is divided into partial circuits and the layout is performed in order from a lower layer due to an increase in the scale of a circuit mounted on the LSI and multi-functionality. Techniques are being adopted.

In this hierarchical layout method, the structure of partial circuits (modules) in each layer, their relative arrangement and shape are determined, and the input / output terminals are arranged from the upper layer to the lower layer, that is, from the top down. A floor planning process for finding a position, and a process for designing detailed placement and wiring such as signal lines and power supply wiring based on a result of floor planning from a lower hierarchy to an upper hierarchy, that is, from the bottom up. It is composed of The floor planning step is a part that globally optimizes the chip area and electrical characteristics, and obtains the shape and relative position of the module.

The power supply wiring is a special wiring required for electrically operating each module. In order to supply power from the outside of the chip, a power supply cell is arranged at the outermost part of the chip, and a voltage is applied to each module inside from the power supply wiring. . Such a power supply wiring physically has a width larger than a normal signal line. The type of power supply wiring is
Normally, two or more types of nets, for example, a positive potential of VCC or VDD and GN
It is composed of a net having a negative potential of D or VSS. When realizing power supply wiring, two-layer metal wiring is adopted,
A method of reducing the number of contacts connecting between two layers by preferentially using one of the layers has been proposed (MM-Sadowska and TT. Tar.).
ng, "Sing-Layer Routing fo
r VLSI: Analysis and Algor
itms "IEEE Trans. on CAD,
pp. 246-pp. 259. 1983). Also, regarding the line width of the power supply wiring, the current consumption is calculated from the number of signal switching, focusing on the logical operation in each module.
A method of changing the wiring width according to the calculated value has been proposed (Japanese Patent Laid-Open No. 1-248640).

[0005]

By the way, in the floor planning step, the area of an undesigned block is designed to accurately estimate the chip area and optimize the electrical characteristics without performing the actual layout. Items such as shape, shape and position of external terminals, their relative arrangement, and directionality and relative arrangement of already designed modules are determined. Optimization of such matters is indispensable because the chip area is determined by the shape of the module and the wiring between the modules. In particular, since the power supply wiring is wider than a normal signal line, it becomes a factor that determines the area of a wiring area between modules. In order for each module to operate electrically stably, it is important to design a power supply, that is, to determine a wiring path in consideration of a power supply capacity in an actual layout.

However, since the above-described determination of each item and the like has conventionally been performed manually, there has been a problem that the LSI design cannot be efficiently performed.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and has as its object to provide an automatic placement and routing method capable of improving design efficiency.

[0008]

An automatic placement and routing method according to the present invention is an automatic placement and routing method for automatically designing placement and routing for an undesigned module and an already designed module when designing an LSI by a hierarchical layout technique. In the placement and routing method, a first step of creating a schematic wiring graph from the relative arrangement of each module, a second step of determining a module subset for a power supply cell, a path and a wiring width in each module subset A third step of determining the terminal position of the undesigned module and the directionality of the already designed module, and a fourth step of estimating the wiring area between the modules and determining the terminal position of the undesigned module. Achieved.

In the second step of the automatic placement and routing method according to the present invention, a set of modules supplied from a power supply source is divided on the wiring area after the relative placement of each module is determined, with the wiring area as a boundary. It is preferable to determine a subset composed of modules such that the estimated power consumption from the power supply source is evenly distributed by repeating the two divisions.

In the automatic placement and routing method according to the present invention, when the terminal position and the wiring path of the undesigned module have not been determined in the fourth step, the power supply is used to determine the approximate power supply path for each set of modules. Determine the approximate route of the signal lines other than the wiring, consider the degree of congestion in each wiring region by the number of signal lines passing through the wiring region, and then set the route of the power supply wiring so as to reduce the overall chip area. Is preferably determined.

In determining the power supply terminal position of the undesigned module in the third step in the automatic placement and routing method according to the present invention, the wiring area between the undesigned module and the module is reduced so that the entire chip area is reduced. It is preferable to improve the estimation accuracy of the inter-module wiring area by reallocating the terminal positions while determining the power supply wiring path beyond the hierarchy.

In the automatic placement and routing method according to the present invention, when determining the direction of the already-designed module in the third step, the already-designed module is designed so as to reduce the entire chip area from the power supply wiring and the approximate path of the signal line. It is preferable to determine the optimal direction by changing the direction of the module.

The operation of the present invention will be described below.

In the present invention, the path of the power supply wiring is determined on the wiring area after the relative arrangement of each module (undesigned and already designed) is determined in floor planning.
At this time, first, a set of modules supplied from a power supply source is globally determined so that the entire chip area is reduced, and then a schematic path and a wiring width are obtained for each set of modules. By determining the electrically required wiring width at this time, the path optimization of a normal signal line (terminal position determination of an undesigned module) can be performed in a form close to the actual layout.

Here, the number of power supplies is not particularly limited, and the route is determined only by giving the capacity of each power supply source as a constraint.

In the inter-module wiring area, a minimum necessary area can be estimated. In particular, the power supply wiring, which is electrically important, has a width up to several hundred times that of a normal signal line, making it difficult to estimate with conventional floor plan technology. Estimating the area. In addition, for an already designed module, the optimal directionality is determined for the power supply wiring.

As described above, according to the present invention, in the floor planning step, the power supply wiring most dependent on the wiring area is optimized mainly for the path and the wiring width. The direction of the design module is determined. According to the present invention, it is possible to minimize the area that is important in chip manufacturing, taking into account electrically important items such as the operation of the module.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a layout model of a block for performing floor planning according to the present invention.

The shape of each block is a rectangle of an arbitrary size, and a target size, for example, a size in a horizontal direction × a vertical direction, is given before the design is performed. Inside the block, the module that performs the operation of the block (including undesigned modules and pre-designed modules)
Are given. Here, the difference between the undesigned module and the already-designed module is whether or not the internal layout pattern is determined before floor planning.

The configuration of the module differs between the chip level and the intermediate level. That is, at the chip level, the relative positions of input / output cells (for example, input / output cells for normal signal lines and input / output cells for power supply) are given, while at the intermediate level, physical positions are given. The relative positions of terminals for making connections (for example, terminals for normal signal lines and terminals for power supply) are given. Each module is a rectangle of an arbitrary size, and finally, terminals for connection are arranged around the rectangle. However, it is assumed that the current consumption inside each module is determined in advance.

Undesigned modules are handled differently depending on the layout model. Signal lines having upper and lower signal line terminals and arranged / wired in an array of cells of the same height are called standard cell blocks. In addition, a rectangular shape having an arbitrary size, in which a block having signal line terminals on four sides is arranged / wired, is called a build-up block. Here, the build-up block forms an intermediate level of the chip described above. As for the power supply wiring and the signal line wiring, wiring on the cell is performed by using two-layer wiring.

Next, an automatic placement and routing method according to an embodiment of the present invention will be described.

FIG. 2 is a process chart showing the automatic placement and routing method of the present invention. FIG. 3 shows the first step and the second step in more detail than FIG.
FIG. 4 is a process diagram for explaining the process, and FIG. 4 is a process diagram for explaining the third process to the fourth process in more detail than FIG.

Prior to the implementation of the present invention, as input information, connection requests (netlists) between modules and input / output cells, modules whose relative arrangement is determined, current consumption of each module, and power supply source It is assumed that a maximum current capacity for a cell, a set of merging prohibited modules, and the like are given as input information. In the following, the case of an input / output cell will be described.

In the method of the present invention, as shown in FIG. 2, in the first step, a schematic wiring graph is created from the relative arrangement of each module.

Next, in a second step, a module subset is determined for the power supply cells.

Next, in a third step, a route and a wiring width in each module subset are determined. Also, the terminal positions of the undesigned modules and the directionality of the already designed modules are determined.

Next, in a fourth step, a schematic wiring is designed on the shortest path for a normal signal line, and the wiring capacitance of each side is calculated. Also, the position of the terminal for the normal signal of the undesigned module is determined.

Hereinafter, each step will be described in detail.
Here, the layout model shown in FIG. 1 is referred to.

(First Step) This step is, as shown in FIG. 3, a step of creating a schematic wiring graph from the relative positions of each module.

The information input in advance is, as shown in FIG. 3, that the area to be floor-planned for each module is rectangular, the shapes of all undesigned modules are determined, It has already been given that each module is arranged without touching inside the rectangle.

In this step, each of the following three types of graph models, each representing a schematic wiring, is created based on the input information.

(1) Floor Plan Graph As shown in FIG. 5, the floor plan graph is a graph expressing the relative arrangement between modules and the wiring channels. When creating this floor plan graph, vertex a
Is given the position information from the module arrangement, and the side b is given the distance information between the vertices.

(2) Route Search Graph This route search graph is a graph obtained by adding the vertex a1 and the side b1 for the route search to the floor plan graph as shown in FIG. The added vertices include those corresponding to the terminals of the already-designed module, those for determining the terminal position in the undesigned module, and those for the in-module partial graph used for wiring in the module. In this case, as in the floor plan graph, the vertices are provided with position information, and the sides are provided with distance information between vertices.

(3) Channel Position Graph As shown in FIG. 7, the channel position graph is a graph expressing the relative positions of the module and the wiring channel. Vertices correspond to modules, and edges correspond to channels. There are two types, a horizontal channel position graph indicated by a broken line and a vertical channel position graph indicated by a solid line.

The above-described graphs are created based on the connection relationship of rectangular areas (tiles) obtained by defining dividing lines in the horizontal and vertical directions along the sides of the module.

(Second Step) This step corresponds to FIGS.
This is a step of determining a subset for the power supply cells as shown in FIG.

FIG. 8 shows a state before the processing in the second step, that is, a state before the module subset is allocated to the set of the respective power supply cells. 9 and 1
0 indicates after the processing in the second step. FIG. 9 shows that the power supply cell is V
FIG. 10 shows a case where the power supply cell is GND. Here, D1, D2, D3, D4 and D5 in the figure indicate the already designed module shown in FIG.
And S2 similarly indicate an undesigned module, P1 and P2 indicate power supply cells, and G1, G2, G3 and G4 similarly indicate input / output cells.

In this step, a subset is determined for each set of the same power supply cells. The subset is determined according to the following method.

First, the floor plan area is hierarchically divided horizontally and vertically along the side b of the floor plan graph shown in FIG. The divided subset area becomes a rectangle.

Next, the division process is completed with one power supply cell included in the divided subset area and one or more modules included. At this time, the division position is adjusted so that the sum of the current consumption amounts in the divided subset regions becomes equal.

Next, after the division process is completed, the subsets that do not include the power supply cells are merged into adjacent subsets.

By the above processing, a subset of modules supplied to one power supply cell is determined. At this point, each wiring width is set to a value corresponding to the minimum necessary current amount.

(Third Step) This step is performed in accordance with FIGS.
As shown in (1), this is a step of determining the path and wiring width in the module subset, the terminal positions of the undesigned module, and the directionality of the already designed module. FIG. 11 shows the determined result.

First, the wiring path between the module sets for one power supply cell determined in the second step is determined. An outline of the processing is as follows.

(1) Terminal Ordering The wiring order of the terminals for each net is as follows: among the terminals of the already-designed module, the module is regarded as a vertex, and the terminals are arranged in order from the one having the smallest distance between the vertices. Order as you would for the module terminals. FIGS. 12 and 13 show this ordering. FIG. 12 shows a case where the wiring order on the VCC side is determined, and FIG.
This is a case where the wiring order on the ND side is determined.

(2) Determination of Wiring Path and Terminal Position The wiring path is determined by the minimum cost maze method on the graph shown in FIG. Perform using

The maze method is suitable for finding the minimum cost (minimum distance) path between two terminals. The application to a multi-terminal network is based on the wiring order of the terminals and the path between the terminal and the searched path. Perform a search to find a solution.

The setting of the start point and end point of the maze method is shown in FIG.
4. Perform as shown in FIG. In other words, there is a case of a power supply cell and a searched path, but in the case of a power supply cell, a terminal is set as a starting point. In the case of an undesigned module,
The vertices of the four corners of the adjacent route search graph are defined as end points. In the case of a designed module, the vertex is the end point. Regarding the searched paths, all the vertices of the path search graph on the wiring path are set as end points. The numbers 1 to 4 in FIGS. 14 and 15 indicate the order.

For the determined path, the wiring width obtained in the second step is used as the wiring channel width of each graph. Basically, the shortest route is determined, but the channel width of the route search graph is assigned to the channel position graph, and the route is set so that the floor planning area is minimized, that is, the chip area is minimized. Make improvements.

Here, the cost of the graph of FIG. 11 used in the maze method is calculated. That is, as shown in FIG. 16, the cost (Ccha) of an edge other than the undesigned block subgraph
nnel), the cost of the subgraph in the designed block (C
dcell) and the cost (Cscell) of the subgraph in the undesigned block are calculated by the following equations (1) to (3).

Cchannel = Ledg (1) Cdcell = a × Ledg (2) Cscell = b × Ledg (3) where a: weighting coefficient b: weighting coefficient Ledg: length in the path search graph Cost of edge of position graph (Ccp
gi) is calculated by the following equations (4) and (5). The above Ccp
FIG. 7 shows gi and the following symbols Bwi-1, Bwi + 1, and Cw.

Ccpgi = Bwi − ／ + Bwi + ／ + Cw (4) Cw = Σ (Wti + D) + D (5) where Bwi−1: the horizontal width (or vertical height) of the module on the left (lower) side of the side Bwi + 1: Horizontal width (or vertical height) of the module on the right (top) of the side Cw: Wiring channel width Wti: Power supply line width passing through the side D: Wide line end-to-end design rule The direction of the already designed module is determined by the following method, except for the direction specified at the time of floor planning.

Although there are eight ways to select the directionality, basically, taking the case of the already designed module (D1) as an example, all four ways are tried as shown in FIG. Is the shortest or has the smallest number of bends.
This makes it possible to reduce the chip area.

For an undesigned module, the position of the power supply terminal is determined using the result of the path determination. at this point,
The terminals of the undesigned module are assigned to the vertices of the path search graph. Undesigned modules may be build-up blocks or standard cell blocks.

Here, in the case of the standard cell block,
The pattern of the internal power supply wiring varies depending on the terminal position as shown in FIG. That is, it is necessary to correct the wiring width between modules depending on whether the power supply terminal is allocated to the vertical side or the horizontal side outside the standard cell block. FIG. 18A shows a case where a power supply terminal is provided on the horizontal side, and FIG. 18B shows a case where a power supply terminal is provided on the vertical side. Therefore, when the terminal is allocated to the vertical side as shown in FIG. 18B, the terminal is re-allocated to the position furthest from the power supply cell regardless of the terminal position. Then, the area of each wiring region is estimated, that is, the estimation is performed with the worst value.

(3) Determination of Wiring Width As shown in FIG. 19, the wiring width expresses a connection relationship from a power supply cell to a power supply terminal of each module in a tree structure.

When the power supply cell is set as a parent, a path is searched from the parent toward each module, and a tree is formed with a branch point of the path or a power terminal of the module as a vertex and the path as a side. FIG. 19B shows a tree structure related to the power terminal (P1) in FIG. 19A, and FIG. 19C shows a tree structure related to the power terminal (P2) in FIG. 19A. Here, starting from the bottom of the tree,
When searching, the terminal width is assigned to the side as the wiring width. That is, the wiring width is determined in order from the branch (end).

The width of a vertex having two or more sides as children,
For example, the wiring width (Wi) at the level i is calculated by the following six equations.

Wi = Ptrnk (ΣWij) (6) where Wij: the width of each wiring and the terminal width of the module at the level below level i Ptrnk (Wsum): Wiring width calculation function Wiring that is Ptrnk (Wsum) The width calculation function is
This is a function for determining the merged wiring width, an example of which is shown in FIG. In FIG. 20, the horizontal axis represents Wsum (μ) and the vertical axis represents Ptrnk (Wsum) (μ).

If the wiring width exceeds the maximum width specified by the design rule as a result of the calculation according to the above equation (6),
The width of the design rule.

When the operation of allocating all the trees is completed, the wiring width is mapped to the wiring path corresponding to each side, and the processing for the power supply wiring is completed. FIG. 21 is a diagram showing a state in which the width of the power supply wiring is mapped.

(Fourth Step) This step corresponds to FIGS.
As shown in (1), this is a step of performing general wiring in order to estimate a wiring area between modules and determine terminal positions of undesigned modules. The outline of the processing is as follows.

(1) Terminal Ordering The terminal wiring order for each net is determined in such a manner that the terminals of the designed module are arranged in order from the terminal having the smallest inter-terminal distance, and finally the terminals of the undesigned module are arranged. Do.

(2) Determination of Wiring Path The wiring path is determined by using the minimum cost maze method on the path search graph. The maze method is suitable for finding the minimum cost route between two terminals. In the application to a multi-terminal net, a route search between a terminal and a searched route is performed according to the wiring order of the terminals to find a solution. The setting of the start point and the end point of the maze method may be the terminal and the searched path, but in the case of the designed module, the terminal is set as the start point or the end point. In the case of an undesigned module, the vertices of the four corners of the adjacent route search graph are set as the start point or the end point. Regarding the searched paths, all the vertices of the path search graph on the wiring path are set as end points.

The route search is basically performed using a route search graph. As shown in FIG. 22A, the channel position graph is updated every time a route of one net is determined, and the route search graph shown in FIG. As shown in ()), the process proceeds while confirming whether the constraint on the size of the floor plan area given first is satisfied. Note that the critical path length in each of the horizontal and vertical directions of the channel position graph is the estimated chip size. The critical path length refers to the length at which the maximum cost sum is obtained when the costs of the sides are added.

Here, the cost of the edge of each graph used in the maze method, that is, the cost (Cchannel) of an edge other than the subgraph in the undesigned block and the cost (Cincell) of the subgraph in the undesigned block are expressed by the following equation (7). Calculate with equation 8.

Cchannel = Ledg (7) Cincell = a × Ledg (8) where a: weighting factor Ledg: length in the path search graph Cost of the side of the channel position graph (Ccp
gi) is calculated by the following equations (9) and (10).

Ccpgi = Bwi-1 / 2 + Bwi + 1/2 + Cw (9) Cw = D × (Ctrnk + 1) (10) where Bwi-1 is the horizontal width (or vertical height) of the module on the left (lower) side of the side. Bwi + 1: Horizontal width (or vertical height) of the module on the right (upper side) of the side Cw: Wiring channel width D: Wiring center design rule Ctrnk: Maximum number of passing trunk lines Ctrnk (Maximum number of passing trunk lines) ) Means cha
The maximum number of overlapping paths on nnel. Therefore, when determining the wiring path in the above (2), the number of signal lines passing through the wiring area is regarded as the wiring congestion, and the entire chip surface is reduced.

(3) Determination of Terminal Position The optimum terminal position is determined for the terminals of the undesigned module, as shown in FIG. 23, using the result of the route determination. FIG. 23A is a view showing the state, and FIG. 23B is an enlarged view showing the details. At this point,
The terminals of the undesigned module are assigned to the vertices of the path search graph.

As a specific process, the terminal is actually moved to the side of the module. In this case, the terminal positions are dispersed for each vertex of the path search graph so that the wiring capacity does not increase and the terminals of different nets do not overlap within each side of the path search graph.

(4) Estimation of Wiring Area Estimation of the wiring area is performed by re-determining the channel width calculated by the path search graph more accurately by determining the detailed terminal positions, and by determining the critical area determined by the channel position graph. By allocating a surplus of the path length to each side, the width of each wiring region is calculated.

(5) Improvement of the wiring path The net passing through the side corresponding to the critical path on the channel position graph is peeled off, and the minimum cost maze method on the path search graph is used so that the critical path length is reduced. Improve the route. The execution is performed a certain number of times.

(6) Estimation of Wiring Area The wiring area is estimated again with respect to the result of the improved wiring path, and the width of each wiring area is calculated more accurately.

The estimation of the terminal position of the undesigned module and the wiring area between the modules with respect to the normal signal line is determined by the above operation.

[0077]

As described above, according to the present invention, in the floor planning process, the path division and the wiring of the power supply wiring related to the operation are automatically optimized, and the terminal positions including other ordinary signal lines are also included. In addition, the area of the floor plan region can be automatically optimized, which contributes to the efficiency of the design process.

[Brief description of the drawings]

FIG. 1 is a diagram showing a layout model of a block on which floor planning is performed according to the present invention.

FIG. 2 is a process chart showing an automatic placement and routing method of the present invention.

FIG. 3 is a process diagram illustrating a first process and a second process in more detail than FIG. 2;

FIG. 4 is a process diagram illustrating third to fourth steps in more detail than FIG.

FIG. 5 is a diagram showing a floor plan graph.

FIG. 6 is a diagram showing a route search graph.

FIG. 7 is a diagram showing a channel position graph.

FIG. 8 is a diagram showing a state before a process in a second step.

FIG. 9 is a diagram showing a state after the processing of the second step, in which the power supply cell is at VCC.

FIG. 10 is a view showing a state after the processing of the second step;
This is a case where the power supply cell is GND. You.

FIG. 11 is a diagram determined in a third step.

FIG. 12 is a diagram showing a case where VCC is used in ordering terminals in a third step.
FIG. 10 is a diagram when the wiring order on the side is determined.

FIG. 13 is a view showing a state in which a GND is used in ordering terminals in a third step;
FIG. 10 is a diagram when the wiring order on the side is determined.

FIG. 14 is a diagram for explaining setting of a start point and an end point of the maze method used in the present invention.

FIG. 15 is a diagram for explaining setting of a start point and an end point of the maze method used in the present invention.

FIG. 16 is a diagram showing each unit when calculating a cost in the maze method used in the present invention.

FIG. 17 is a diagram illustrating an example of selecting the direction of a designed module used in the present invention.

FIG. 18 is a diagram showing a power supply wiring pattern in an undesigned module (standard cell block).

FIG. 19 is a diagram showing a tree structure for expressing a path width with respect to an example of a path of a power supply wiring determined in a third step.

FIG. 20 is a diagram illustrating a function P used for calculating a wiring width according to the present invention;
It is a figure showing an example of trnk.

FIG. 21 is a diagram schematically showing a wiring width with respect to a wiring path as a final result of the third step.

FIG. 22 is a diagram illustrating a route search performed in a fourth step.

FIG. 23 is a diagram showing schematic assignment of terminals of a normal signal line and assignment of detailed terminal positions in a fourth step.

[Explanation of symbols]

 D1, D2, D3, D4, D5 Designed module S1, S2 Undesigned module P1, P2 Power supply cell G1, G2, G3, G4 Input / output cell

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/82 B 27/04 D

Claims (5)

[Claims] 1. An automatic placement and routing method for automatically designing placement and routing for an undesigned module and an already-designed module when designing an LSI by a hierarchical layout method. A first step of creating a graph, a second step of determining a module subset for a power supply cell, a route, a wiring width, a terminal position of an undesigned module, and a direction of a designed module in each module subset. An automatic placement and routing method, comprising: a third step of determining the characteristics; and a fourth step of determining the inter-module wiring area and determining the terminal positions of the undesigned modules. 2. In the second step, on a wiring area after the relative arrangement of each module is determined,
Subset composed of modules such that the estimated power consumption from the power supply source is evenly distributed by repeatedly dividing the set of modules supplied from the power supply source into two parts with the wiring area as a boundary 2. The automatic placement and routing method according to claim 1, wherein 3. In the fourth step, when a terminal position and a wiring path of an undesigned module are not determined, when determining an approximate power supply path for each set of modules, signal lines other than the power supply wiring are determined. 2. The method according to claim 1, further comprising: determining an approximate path, determining a degree of congestion in each wiring area by the number of signal lines passing through the wiring area, and determining a path of the power supply wiring so as to reduce the entire chip area. Automatic placement and routing method described in 1. 4. The method of determining the position of a power supply terminal of an undesigned module in the third step, wherein the power supply wiring extends over a layer of a wiring region in the undesigned module and between the modules so as to reduce the entire chip area. 2. The automatic placement and routing method according to claim 1, wherein the terminal positions are reallocated while determining the path, thereby improving the estimation accuracy of the inter-module wiring area. 5. The method according to claim 3, wherein the direction of the already designed module is determined by changing the direction of the already designed module from the power supply wiring and the approximate path of the signal line so as to reduce the entire chip area. 2. The automatic placement and routing method according to claim 1, wherein the optimal directionality is determined by performing the determination.