JPH0125225B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides:
The present invention relates to a method of manufacturing a gate array type master slice integrated circuit.

In so-called gate arrays that realize desired circuit functions on a master slice board, multiple types of master slice boards with different accommodating circuit sizes are prepared, especially when the circuit scale ranges from small to large. . In other words, a master slice board with a large circuit scale capacity has a large chip size, a low wafer yield, and a high cost per chip, so a small master slice board is used for a small scale circuit. .

However, from the perspective of master slice board design, preparing multiple types of master slice boards in this way is simply It is not possible to create a small chip by simply deleting a part of a large chip, but by deleting a part and shrinking it by that amount, a new pattern combination appears.
This usually involves difficulties such as the pattern shapes that should be common between the two types of master slices becoming different from each other.

In view of the above circumstances, it is an object of the present invention to provide a layout method for improving the efficiency of designing multiple types of master slice type chips in which the performance of the unit circuits is almost the same but the circuit scale capacity is different. A master slice type integrated circuit has a plurality of circuit blocks formed by a plurality of cells, and the width of the wiring channel between the circuit blocks is wider than the width of the wiring channel between the cells. A method for manufacturing a master slice type integrated circuit is provided in which the width of the wiring channel between the circuit blocks is changed according to the number of the circuit blocks mounted on the semiconductor substrate without changing the width.

The present invention will be explained below with reference to the drawings.

Figure 1 shows an example of a conventional cell layout for two types of master slice type chips with different circuit scale capacities; Figure 1a shows a large-scale one;
FIG. 1b corresponds to a small-scale cell, which is composed of a cell 1 containing transistors, resistors, etc., and a wiring channel region 2, and 3 and 4 are circuits placed on the cell 1, respectively. Shows functional blocks. In particular, the wiring channel regions l and m had the same size in both the large-scale chip (FIG. 1a) and the small-scale chip (FIG. 1b).

One of the characteristic elements of the invention includes FIGS.
The main point is that the circuit function blocks common to each of the two types of master slice type chips shown in the figure are used.
To make this possible, considering a circuit function block that uses a plurality of cells 1, it is necessary to
It is necessary to keep the inter-cell distances l and m shown in the figure the same between the two types of master slice type chips. However, in a case where the circuit size is small, the width of the wiring channel area 2 for interconnecting the circuit function blocks can be relatively small, so that between the two types of master/slice chips mentioned above,
If the distances l and m between the cells are set to the same size, the chip shown in FIG. 1b, which is suitable for a small scale, will have an excessive wiring channel area, and the area efficiency of the chip will deteriorate.

In order to solve this problem, the distances l and m between the cells in the small-scale chip shown in FIG. . Considering that normally, circuit function blocks can be classified into several dozen types by circuit function, this method is completely undesirable from the viewpoint of circuit function block pattern design.

Therefore, in the present invention, as shown in the first embodiment and FIGS. 2a and 2b, in order to limit the size of the circuit function blocks 3' and 4', the number of cells that can be included in one circuit function block is limited. ′ in the X direction and Y direction (the cell number limit is p in the X direction and q in the Y direction). Below the limit, the distances between cells l′ and m′ are The master slice chips are of the same size, and the cell group 5 consisting of the number of cells within the limit value is taken as one unit, and the distances h, i, j, k between the cell groups are shown in FIG. 2a, It was decided to independently set the required amount for each of the two types of master slice chips shown in b. This is the second feature of the present invention. This allows common use of circuit functional blocks among multiple master slice integrated circuits without having excessive wiring channels.

In addition, in the cell layout form shown in FIG. 2, the size of the cell group 5 is set in common to each of the master and slice chips, so multiple circuit function blocks are collected and arranged within the size range of the cell group 5. Since it is possible to interconnect them and create macro circuit function blocks, the layout structure is suitable for hierarchical automatic design.

Figures 3a and 3b show a second embodiment of the present invention, and the size of the circuit function block 3'' is such that there is no wiring channel in the X direction as shown in Figure 2 l', h, and j. There is no limit to the number of cells, and the number of cells in the Y direction is 2 or less.On the other hand, the size of the wiring channel region 2'' is m'' inside the cell group 5', and While the chips are set to the same size, the cell groups 5' are set to different sizes i' and k'.In addition, in the same embodiment,
Since the wiring channel in the Y direction can freely pass over the cell 1'', the spacings shown in FIG. 2, l', h, and j are not required.

As described above, the present invention contributes to improving the efficiency of chip pattern design for multiple types of master slice type integrated circuits whose unit circuits have substantially the same performance but different circuit scale capacities, and This invention presents a layout method that is suitable for hierarchical design without sacrificing chip area efficiency.

[Brief explanation of drawings]

1A and 1B are plan views each showing a cell layout of a conventional master slice type integrated circuit, FIGS. 2A and 2B are plan views each showing a cell layout of an embodiment of the present invention, and FIG. 3A , b are plan views of other embodiments of the present invention. In the figure, 1, 1', 1''... cell, 2,
2', 2''...Wiring channel area, 3, 3',
3″, 4, 4′……Circuit function block, 5, 5′…
...Cell group containing multiple cells, l, m...Relative distance between cells, l', m', m''...Relative distance between cells within a cell group, h, i, i', j, k, k'... indicates the relative distance between cell groups, p, q... indicates the number of cells in the X direction and Y direction within the cell group, respectively.

Claims (1)

[Claims] 1. In a method for manufacturing a master slice type integrated circuit having a plurality of circuit blocks formed of a plurality of cells on a semiconductor substrate, the width of the wiring channel between the circuit blocks is wider than the width of the wiring channel between the cells. , a master slice type integrated circuit characterized in that the width of the wiring channel between the circuit blocks is changed according to the number of the circuit blocks mounted on the semiconductor substrate without changing the width of the wiring channel between the cells. manufacturing method.