JPS59107330A - Driving method of liquid crystal matrix panel - Google Patents

Abstract

PURPOSE:To suppress the previous history of a liquid crystal capacity, etc. by constituting so that an AC signal in which positive and negative potential signals exist at least once or more is used, in one scanning period, and the liquid crystal panel capacity is charged and discharged almost completely. CONSTITUTION:An AC signal V4 in which positive and negative potential signals exist at least once is applied to the drain of the second FET Q2, in one scanning period of a scanning signal V2. In a period to the time (t) when an information signal V1 is in a high potential level, the source-drain impedance is in a low state. On the other hand, if the information signal V1 is varied suddenly to a low potential level from a high potential level at the time (t), the drain-source impedance of the FET Q2 rises suddenly. Therefore, the amplitude of a drain- source current I4 of this FET Q2 also becomes near zero. In this case, since an electric discharge period of a liquid crystal panel is set short, the charged charge is discharged quickly. In this way, the previous history of a liquid crystal capacity, etc. can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for driving a liquid crystal matrix panel. A switching element such as a thin film FET (TPT) is placed at the intersection of the lines,
This switching element opens and closes the display provided at each of the above intersections! The present invention relates to a method for driving a liquid crystal matrix panel that displays an image by applying a display signal to a pole and driving the liquid crystal in this part for display.

Prior art Figure 1 shows the overall structure of this type of matrix panel, (
1) is the front glass transparent substrate, and (2) is this transparent substrate (1).
) A common electrode made of an ITO film coated on the entire inner surface, (
3) is a liquid crystal layer, and (4) is a spacer made of glass frit, resin, etc., which also functions as a sealing material.

(5) is a rear glass transparent substrate, on its inner surface, a plurality of scanning lines X and information lines Y are arranged orthogonally insulated from each other. (6H6)... are display electrodes connected to each intersection of the scanning line X and the information line Y via an amorphous silicon FET. The circuit configuration of one liquid crystal cell of a matrix panel using such an FET array is shown in FIG. That is, the drain of FET (Q) is connected to the scanning line X, the gate is connected to the information line Y, and the liquid crystal panel (LCD) is connected between the source and ground (common electrode (2+). However, with such a configuration, the above FE
Amorphous silicon 1'E used as T(Q)
Since the on-current of T is small, it takes time to charge the liquid crystal panel capacitance and additional capacitance, which is a major problem in cases where the address timing cannot be set for a long time, such as in the display panel of a television.

On the other hand, the FET is configured in two stages, the first stage FET is driven at the addressed timing, the gate capacitance of the second stage NET is charged, and the second stage NET is charged using one frame time until the next address. A method has been proposed in which a liquid crystal capacitor or an additional capacitor is charged and discharged using a second stage FET. However, in this method, the charging and discharging of the liquid crystal capacitor or additional capacitor is
This is done through the source and drain of the ET, and this gate is charged according to the signal voltage, so if the signal suddenly changes from a high level to a low level, the charge in the liquid crystal capacitor or additional capacitor cannot be completely discharged in one scanning period. , the previous history will remain for a while. For this reason, even if the signal changes suddenly, the potential applied to the liquid crystal cannot follow this, resulting in a gradual change. This relationship is shown in FIG. 4 by dashed lines for the voltages ■■currents■ and the voltages V■.

Purpose of the Invention The present invention uses a two-stage FET to generate a liquid crystal spring/I/
This method takes measures against the slow discharge of the liquid crystal capacitor or additional capacitor as described above, and suppresses the antecedent history.

Structure of the Invention The present invention provides a first FET which inputs a scanning line signal to its gate and inputs an information line signal to its drain (or source).
is connected to the gate of the second FET, information is written and accumulated in the gate capacitance of the second FET, and an AC signal for driving the liquid crystal is connected to the drain (or source) of the second FET and the display electrode of the liquid crystal panel is connected to the drain (or source) of the second FET. In a driving method in which the LCD panel is charged and discharged using one scanning period, an AC signal in which a positive potential signal and a negative potential signal exist at least once within one scanning period is used as the liquid crystal driving signal. The capacitance of the liquid crystal panel is set to a value such that it can be almost completely charged and discharged by a positive potential signal and a negative potential signal.

Embodiment In FIG. 6, Xi and Yj each represent one of the aforementioned scanning lines and information lines. (Ql) is the first FET to which the scanning line Xj times signal ■ is input to the gate and the information line Yj times signal ■ is input to the drain (or source);
A second FET to which the source potential (or drain potential) V■ of the FET (Ql) is applied to the gate, the liquid crystal driving AC signal ■■ is applied to the drain (or source), and the source (or drain) is It is connected to the display voltage m (61) of the liquid crystal panel (LCD).

Next, the operation of the first FET (Ql
) When the scanning signal V■ is input at a predetermined period to the gate of the second FET (Ql), the information signal V■ sent from the information line Yj to the gate of the second FET (Ql) is transmitted to the drain of the first FET (Ql).
Written and stored across sources. 2nd FET
An alternating current signal ■■ in which a positive potential signal and a negative potential signal exist at least once within one scanning period of the scanning signal ■■ is applied to the drain of (Ql). In the case of this example, a signal in which a positive potential signal and a negative potential signal exist once each within one scanning period is used, but the present invention is not limited to this, and each potential signal can also exist twice. The number can be set arbitrarily.

In this case, each output period of the high potential signal and the low potential signal becomes short, but if the charge/discharge time constant of the liquid crystal panel (LCD) is determined according to this period, and the frequency of the drive signal V becomes large, The charging and discharging period is also shortened accordingly. Adjustment of the time constant of this liquid crystal panel (LCD) is performed using the second FET (
This is done by changing the impedance between the drain and source of Q2) or by changing the capacitance of an additional capacitor (not shown) placed in parallel with the liquid crystal panel (LCD). For example, if the frequency of AC voltage ■■ is increased, the second F
The time constant may be reduced by lowering the impedance of ET (Q2) or by lowering the ratio of the additional capacitance.

During the period up to time t when the information signal ■■ is currently at a high potential level, charges corresponding to the information signal V■ are accumulated at the gate of the second FET (Q2), and the source-drain impedance (voltage ■■) increases. is in a low state. Therefore, the current flowing between the source and drain is the voltage
A pulse signal that draws a relatively large waveform that reflects the
A liquid crystal panel (LCD) display is added to the pole (6). The voltage applied to a liquid crystal panel (LCD) has a waveform as shown in voltage (■) due to its capacitance. During this period, the liquid crystal panel (LCD) performs a display operation and displays dots forming pixels.

On the other hand, at time t, if the information signal V■ suddenly changes from a high potential level to a low potential level, then the second F in synchronization with the first arriving scanning line signal ■■ (time t)
The charge accumulated in the gate capacitance of the ET (Q2) is discharged, and the drain-source impedance of the second NET (Q2) increases rapidly. Therefore, this second FET (Q2
)'s drain-to-source current ■■ amplitude also approaches zero. However, since the discharge period of the liquid crystal panel (LCD) is set to be short in response to the higher frequency of the AC drive signal, this charge is quickly discharged.

Effects of the Invention The present invention shortens the period of the AC liquid crystal driving signal as well as the scanning signal period, - adjusts the driving voltage signal so that a high potential signal and a low potential signal exist multiple times within the scanning period, and Since the charging/discharging time constant of the liquid crystal panel is made to match each pulse period of this drive voltage signal, the charging/discharging period of the liquid crystal panel can be shortened, and the display response can be made faster.

[Brief explanation of the drawing]

FIG. 1 is an exploded perspective view showing the general structure of a liquid crystal matrix panel, FIG. 2 is a conventional circuit diagram, FIG. 6 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a waveform diagram of the same operation. (11 (57...transparent substrate, (2)...
・Common ti, (3)...Liquid crystal layer, (6)...
... Display electrode, (LCD) ... Liquid crystal panel,
(Ql)...1st FET, (Q2)...
・Second FET. 175

Claims (1)

[Claims] 1. A method for driving a liquid crystal matrix panel, in which a switching element is arranged at the intersection of a plurality of orthogonal scanning lines and information lines, and the liquid crystal between electrodes provided at the intersection is driven to display by driving the switching element. The switching element includes a first FET to which a scanning signal is applied to the gate and an information signal is applied to the drain (or source), the source (or drain) of the first FET is connected to the gate, and the drain (or source) is connected to the liquid crystal drive power supply. and a second FET whose source (or drain) is connected to the display electrode of the liquid crystal panel, and transmits information to the second FET.
In a driving method in which the liquid crystal panel is charged and discharged using one cycle of the scanning signal by accumulating in the gate capacitance of T, the driving signal applied to the drain (or source) of the second F B and T is the one described above. An AC signal in which a positive potential signal and a negative potential signal exist at least once within a scanning period is used, and the capacity of the liquid crystal panel is set to be charged and discharged with one cycle signal of a positive potential signal and a negative potential signal. A method of driving a liquid crystal matrix panel.