JPS59107330A - Driving method of liquid crystal matrix panel - Google Patents
Driving method of liquid crystal matrix panelInfo
- Publication number
- JPS59107330A JPS59107330A JP21903582A JP21903582A JPS59107330A JP S59107330 A JPS59107330 A JP S59107330A JP 21903582 A JP21903582 A JP 21903582A JP 21903582 A JP21903582 A JP 21903582A JP S59107330 A JPS59107330 A JP S59107330A
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- signal
- drain
- fet
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、液晶マトリクスパネルの駆動方法、更に詳し
くは液晶パネルの一方の基板に走査線及び情報線を多数
互いに絶縁した状態で形成し、これらの線の交差点に薄
膜FET(TPT)よシなるスイッチング素子を配し、
このスイッチング素子を開閉して上記各交差点ごとに設
けられた表示!極に表示信号を与え、この部分の液晶を
表示駆動させることにより、画像表示を行なう液晶マト
リクスパネルの駆動方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for driving a liquid crystal matrix panel. A switching element such as a thin film FET (TPT) is placed at the intersection of the lines,
This switching element opens and closes the display provided at each of the above intersections! The present invention relates to a method for driving a liquid crystal matrix panel that displays an image by applying a display signal to a pole and driving the liquid crystal in this part for display.
従来技術
第1図はこの種マトリクスパネルの全体構造を示し、(
1)は前面ガラス透明基板、(2)はこの透明基板(1
)内面全面に被着されたITO膜よりなる共通電極、(
3)は液晶層、(4)はガラスフリット、樹脂等よシな
るスペーサでシール材としてもはたらく。Prior art Figure 1 shows the overall structure of this type of matrix panel, (
1) is the front glass transparent substrate, and (2) is this transparent substrate (1).
) A common electrode made of an ITO film coated on the entire inner surface, (
3) is a liquid crystal layer, and (4) is a spacer made of glass frit, resin, etc., which also functions as a sealing material.
(5)は背面ガラス透明基板で、その内面に複数本の走
査線X及び情報線Yが互いに絶縁して直交配置されてい
る。(6H6)・・・は走査線X、情報線Yの各交差点
に、アモルファスシリコンFETを介して接続された表
示電極である。かかるFETアレイを利用したマトリク
スパネルの1液晶セルの回路構成は、第2図に示される
。即ちFET(Q)のドレインが走査線Xに、ゲートが
情報線Yに、寸たソース・接地(共通電極(2+ >間
に液晶パネル(LCD)が接続される。(0)は液晶パ
ネル(L cD)に並列に付加容量として介挿されたコ
ンデンサである しかしかかる構成であれば、上記FE
T(Q)として使用されるアモルファスシリコン1’E
Tのオン電流が小さいため液晶パネル容量及び付加容量
を充電するのに時間がかかり、テレビの表示パネルのよ
うにアドレスのタイミングを長くとれない場合には、大
きな障害となっている。(5) is a rear glass transparent substrate, on its inner surface, a plurality of scanning lines X and information lines Y are arranged orthogonally insulated from each other. (6H6)... are display electrodes connected to each intersection of the scanning line X and the information line Y via an amorphous silicon FET. The circuit configuration of one liquid crystal cell of a matrix panel using such an FET array is shown in FIG. That is, the drain of FET (Q) is connected to the scanning line X, the gate is connected to the information line Y, and the liquid crystal panel (LCD) is connected between the source and ground (common electrode (2+). However, with such a configuration, the above FE
Amorphous silicon 1'E used as T(Q)
Since the on-current of T is small, it takes time to charge the liquid crystal panel capacitance and additional capacitance, which is a major problem in cases where the address timing cannot be set for a long time, such as in the display panel of a television.
これに対し、FETを2段構成とし、アドレスしたタイ
ミングで初段のFETを駆動して2段目のNETのゲー
ト容量に充電し、次にアドレスされるまでの1フレーム
の時間を使って、2段目のFETで液晶容量又は付加容
量を充放電する方法が提案されている。しかし、かかる
方法では、液晶容量又は付加容量の充放電が2段目のF
ETのソース・ドレインを通じて行われ、このゲートが
信号電圧に応じて充電されているため、信号が高いレベ
ルから低いレベルに急激に変った場合1走査期間では液
晶容量又は付加容量の電荷が抜けきらず、しばらくは前
歴が残ることとなる。このため信号が急に変っても液晶
にかかる電位は、・これに追随できず、緩漫な変化とな
ってしまう。この関係を第4図に電圧■■電流工■及び
電圧V■に破線で示す。On the other hand, the FET is configured in two stages, the first stage FET is driven at the addressed timing, the gate capacitance of the second stage NET is charged, and the second stage NET is charged using one frame time until the next address. A method has been proposed in which a liquid crystal capacitor or an additional capacitor is charged and discharged using a second stage FET. However, in this method, the charging and discharging of the liquid crystal capacitor or additional capacitor is
This is done through the source and drain of the ET, and this gate is charged according to the signal voltage, so if the signal suddenly changes from a high level to a low level, the charge in the liquid crystal capacitor or additional capacitor cannot be completely discharged in one scanning period. , the previous history will remain for a while. For this reason, even if the signal changes suddenly, the potential applied to the liquid crystal cannot follow this, resulting in a gradual change. This relationship is shown in FIG. 4 by dashed lines for the voltages ■■currents■ and the voltages V■.
発明の目的
本発明は、2段構成のFETを使用して液晶バネ/I/
を駆動する方法であって、前述したような液晶容量又は
付加容量の緩漫な放電に対策を施し、前歴の抑制をはか
ったものである。Purpose of the Invention The present invention uses a two-stage FET to generate a liquid crystal spring/I/
This method takes measures against the slow discharge of the liquid crystal capacitor or additional capacitor as described above, and suppresses the antecedent history.
発明の構成
本発明は、走査線信号をゲートに、情報線信号をドレイ
ン(若しくはソース)に入力する第1FETを設け、こ
の第1 F E ’I’のソース(若しくはドレイン)
を第2FETのゲートに接続し、情報を第2FETのゲ
ート容量に書き込み、かつ蓄積し、この第2FETのド
レイン(若しくはソース)に液晶駆動用交流信号をソー
ス(若しくはドレイン)に液晶パネルの表示電極を接続
して、1走査期間を使って液晶パネルの充放電を行なう
駆動方法において、液晶駆動信号として、1走査期間内
に正電位信号及び負電位信号が少なくとも1回以上存在
する交流信号が使用され、上記液晶パネルの容量は、正
電位信号及び負電位信号にて略完全に充、放電されるよ
うその値が設定されたものである。Structure of the Invention The present invention provides a first FET which inputs a scanning line signal to its gate and inputs an information line signal to its drain (or source).
is connected to the gate of the second FET, information is written and accumulated in the gate capacitance of the second FET, and an AC signal for driving the liquid crystal is connected to the drain (or source) of the second FET and the display electrode of the liquid crystal panel is connected to the drain (or source) of the second FET. In a driving method in which the LCD panel is charged and discharged using one scanning period, an AC signal in which a positive potential signal and a negative potential signal exist at least once within one scanning period is used as the liquid crystal driving signal. The capacitance of the liquid crystal panel is set to a value such that it can be almost completely charged and discharged by a positive potential signal and a negative potential signal.
実施例
第6図において、Xi、Yjはそれぞれ前述した走査線
及び情報線の各一本である。(Ql)は走査線Xj倍信
号■がゲートに、情報線Yj倍信号■がドレイン(若し
くはソース)に入力される第1FET、(Ql)は第1
FET(Ql )のソース電位(若しくはドレイン電位
)V■がゲートに加えられる第2FETで、そのドレイ
ン(若しくはソース)には、液晶駆動交流信号■■が加
えられ、またソース(若しくはドレイン)は、液晶パネ
ル(LCD)の表示電m(61に接続される。Embodiment In FIG. 6, Xi and Yj each represent one of the aforementioned scanning lines and information lines. (Ql) is the first FET to which the scanning line Xj times signal ■ is input to the gate and the information line Yj times signal ■ is input to the drain (or source);
A second FET to which the source potential (or drain potential) V■ of the FET (Ql) is applied to the gate, the liquid crystal driving AC signal ■■ is applied to the drain (or source), and the source (or drain) is It is connected to the display voltage m (61) of the liquid crystal panel (LCD).
次に第4図とともに動作を説明する 第1FET(Ql
)のゲートに、所定の周期で走査信号V■が入力すると
、第2FET(Ql)のゲートに、情報線Yjから送ら
れる情報信号V■が、第1FET(Ql)のドレイン・
ソース間を通して、書き込まれ蓄積される。第2FET
(Ql)のドレインには、走査信号■■の1走査期間内
に正電位信号及び負電位信号が少なくとも一回存在する
交流信号■■が加えられる。本例の場合、1走査期間内
に正電位信号及び負電位信号が1回ずつ存在する信号を
使用しているが、これに限らず、各電位信号を2回ずつ
存在させることもでき、その数は、任意に設定できる。Next, the operation of the first FET (Ql
) When the scanning signal V■ is input at a predetermined period to the gate of the second FET (Ql), the information signal V■ sent from the information line Yj to the gate of the second FET (Ql) is transmitted to the drain of the first FET (Ql).
Written and stored across sources. 2nd FET
An alternating current signal ■■ in which a positive potential signal and a negative potential signal exist at least once within one scanning period of the scanning signal ■■ is applied to the drain of (Ql). In the case of this example, a signal in which a positive potential signal and a negative potential signal exist once each within one scanning period is used, but the present invention is not limited to this, and each potential signal can also exist twice. The number can be set arbitrarily.
この場合、高電位信号及び低電位信号の各出力期間は短
かくなるが、この期間に合せて液晶パネル(LCD)の
充放電時定数が決定され、駆動信号V■の周波数が大き
くなれば、充放電期間もそれに応じて短縮される。この
液晶パネル(LCD)の時定数の調整は、第2FET(
Q2 )のドレイン・ソース間インピーダンスの変更或
は、液晶パネル(LCD)と並列に配される付加コンデ
ンサ(図示せず)の容量の変更によって行なわれる。例
えば、交流電圧■■の周波数を上昇させた場合、第2F
ET(Q2)のインピーダンスを低下させるか、若しく
は付加容量の伯を下げて、時定数を小さくしてやればよ
い。In this case, each output period of the high potential signal and the low potential signal becomes short, but if the charge/discharge time constant of the liquid crystal panel (LCD) is determined according to this period, and the frequency of the drive signal V becomes large, The charging and discharging period is also shortened accordingly. Adjustment of the time constant of this liquid crystal panel (LCD) is performed using the second FET (
This is done by changing the impedance between the drain and source of Q2) or by changing the capacitance of an additional capacitor (not shown) placed in parallel with the liquid crystal panel (LCD). For example, if the frequency of AC voltage ■■ is increased, the second F
The time constant may be reduced by lowering the impedance of ET (Q2) or by lowering the ratio of the additional capacitance.
いま情報信号■■が高電位レベルにある時刻tまでの期
間では、第2FET(Q2 )のゲートには、情報信号
V■に応じた電荷が蓄積され、(電圧■■)ソース・ド
レイン間インピーダンスは低い状態にある。したがって
このソース・ドレイン間に流れる電流■■は、電圧■■
を反映した比較的大きな波形を描くパルス信号となシ、
液晶パネル(LCD)の表示を極(6)に加わる。液晶
パネル(LCD)に加わる電圧は、その容量のために電
圧■■に示す如き波形となる。かかる期間では、液晶パ
ネル(LCD)は表示動作し、画素を構成するドツト状
の表示が行なわれる。During the period up to time t when the information signal ■■ is currently at a high potential level, charges corresponding to the information signal V■ are accumulated at the gate of the second FET (Q2), and the source-drain impedance (voltage ■■) increases. is in a low state. Therefore, the current flowing between the source and drain is the voltage
A pulse signal that draws a relatively large waveform that reflects the
A liquid crystal panel (LCD) display is added to the pole (6). The voltage applied to a liquid crystal panel (LCD) has a waveform as shown in voltage (■) due to its capacitance. During this period, the liquid crystal panel (LCD) performs a display operation and displays dots forming pixels.
他方、時刻tにおいて、情報信号V■が急激に高電位レ
ベルから低電位レベルへ変化したとすると、その後最初
に到来する走査線信号■■に同期して(時刻t)第2F
ET(Q2)のゲート容量に蓄積されていた電荷は放電
され、第2NET(Q2)のドレイン・ソース間インピ
ーダンスハ急上昇する。それ故、この第2FET(Q2
)のドレイ、ン・ソース間電流■■の振幅も略ゼロに近
くなる。しかし液晶パネル(LCD)の放電期間が、交
流駆動信号■■の高周波数化に応答して、短かく設定さ
れてい名から、この充電々荷は速かに放電される。On the other hand, at time t, if the information signal V■ suddenly changes from a high potential level to a low potential level, then the second F in synchronization with the first arriving scanning line signal ■■ (time t)
The charge accumulated in the gate capacitance of the ET (Q2) is discharged, and the drain-source impedance of the second NET (Q2) increases rapidly. Therefore, this second FET (Q2
)'s drain-to-source current ■■ amplitude also approaches zero. However, since the discharge period of the liquid crystal panel (LCD) is set to be short in response to the higher frequency of the AC drive signal, this charge is quickly discharged.
発明の効果
本発明は、走査信号周期よシも、交流液晶駆動信号の周
期を短かくし、−走査期間内に複数回高電位信号及び低
電位信号が存在するよう駆動電圧信号を調整し、かつ液
晶パネルの充放電時定数をこの駆動電圧信号の各パルス
期間に一致させるものであるから、液晶パネルの充放電
期間を短縮することができ、表示レスポンスを敏速化す
ることが可能となる。Effects of the Invention The present invention shortens the period of the AC liquid crystal driving signal as well as the scanning signal period, - adjusts the driving voltage signal so that a high potential signal and a low potential signal exist multiple times within the scanning period, and Since the charging/discharging time constant of the liquid crystal panel is made to match each pulse period of this drive voltage signal, the charging/discharging period of the liquid crystal panel can be shortened, and the display response can be made faster.
第1図は、液晶マトリクスパネルの一般的構造を示す分
解斜視図、第2図は、従来例回路図、第6図は本発明実
施例回路図、第4図は同動作波形図である。
(11(57・・・・・・透明基板、(2)・・・・・
・共通ti、(3)・・・・・・液晶層、(6)・・・
・・・表示電極、(LCD)・・・・・・液晶パネル、
(Ql)・・・・・・第1FET、(Q2)・・・・・
・第2F E T。
175FIG. 1 is an exploded perspective view showing the general structure of a liquid crystal matrix panel, FIG. 2 is a conventional circuit diagram, FIG. 6 is a circuit diagram of an embodiment of the present invention, and FIG. 4 is a waveform diagram of the same operation. (11 (57...transparent substrate, (2)...
・Common ti, (3)...Liquid crystal layer, (6)...
... Display electrode, (LCD) ... Liquid crystal panel,
(Ql)...1st FET, (Q2)...
・Second FET. 175
Claims (1)
チング素子を配し、該スイッチング素子の駆動によシ上
記交差点に設けられた電極間の液晶を表示駆動する液晶
マトリクスパネルの駆動方法であって、上記スイッチン
グ素子は、走査信号がゲートに加えられ情報信号がドレ
イン(若しくはソース)に加えられる第1FETと、該
第1FETのソース(若しくはドレイン)がゲートにド
レイン(若しくはソース)が液晶駆動電源に、かつソー
ス(若しくはドレイン)が液晶パネルの表示電極に接続
される第2 FETにて形成され、情報を上記第2FE
Tのゲート容量に蓄積し、走査信号1周期々間を使って
液晶パネルの充放電を行なう駆動方法において、上記第
2 F B、Tのドレイン(若しくはソース)に加えら
れる駆動信号として、上記1走査期間内に正電位信号及
び負電位信号が少なくとも1回以上存在する交流信号が
使用され、かつ上記液晶パネルの容量は、正電位信号及
び負電位信号の一サイクル信号にて充放電すべく設定さ
れてなる液晶マトリクスパネルの駆動方法。1. A method for driving a liquid crystal matrix panel, in which a switching element is arranged at the intersection of a plurality of orthogonal scanning lines and information lines, and the liquid crystal between electrodes provided at the intersection is driven to display by driving the switching element. The switching element includes a first FET to which a scanning signal is applied to the gate and an information signal is applied to the drain (or source), the source (or drain) of the first FET is connected to the gate, and the drain (or source) is connected to the liquid crystal drive power supply. and a second FET whose source (or drain) is connected to the display electrode of the liquid crystal panel, and transmits information to the second FET.
In a driving method in which the liquid crystal panel is charged and discharged using one cycle of the scanning signal by accumulating in the gate capacitance of T, the driving signal applied to the drain (or source) of the second F B and T is the one described above. An AC signal in which a positive potential signal and a negative potential signal exist at least once within a scanning period is used, and the capacity of the liquid crystal panel is set to be charged and discharged with one cycle signal of a positive potential signal and a negative potential signal. A method of driving a liquid crystal matrix panel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21903582A JPS59107330A (en) | 1982-12-13 | 1982-12-13 | Driving method of liquid crystal matrix panel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21903582A JPS59107330A (en) | 1982-12-13 | 1982-12-13 | Driving method of liquid crystal matrix panel |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59107330A true JPS59107330A (en) | 1984-06-21 |
Family
ID=16729228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21903582A Pending JPS59107330A (en) | 1982-12-13 | 1982-12-13 | Driving method of liquid crystal matrix panel |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59107330A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4917467A (en) * | 1988-06-16 | 1990-04-17 | Industrial Technology Research Institute | Active matrix addressing arrangement for liquid crystal display |
-
1982
- 1982-12-13 JP JP21903582A patent/JPS59107330A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4917467A (en) * | 1988-06-16 | 1990-04-17 | Industrial Technology Research Institute | Active matrix addressing arrangement for liquid crystal display |
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