JPH06242417A - Active matrix type display device and its driving method - Google Patents

Abstract

PURPOSE:To improve the display quality and to reduce both the power consumption and a flicker. CONSTITUTION:The grounded-side electrodes of storage capacitances 711, 713... are connected to a scan bus line 1-1, and the grounded-side electrodes of storage capacitances 712, 714... and storage capacitances 722, 724... are connected to a scan bus line 10; and the grounded-side electrodes of storage capacitances 721, 723... and 731, 733... are connected to a scan bus line 11 and the grounded-side electrodes of storage capacitances 732, 734... and storage capacitances 742, 744... are connected to a scan bus line 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device used for a display device such as a small portable television or a notebook personal computer, and a driving method thereof.

[0002]

2. Description of the Related Art Active matrix type display devices are
At present, it is used as a thin display device for information terminals together with a simple matrix display device, and liquid crystal is often used as a display medium. Since this active matrix type display device can drive a large number of liquid crystal cells independently of each other, even if the number of lines increases as the display area becomes larger, the duty ratio of the drive voltage becomes different from that of the simple matrix type display device. It has features that the ratio does not decrease, the contrast does not decrease, and the viewing angle does not narrow.

FIG. 5 is an equivalent circuit diagram showing a structural example of a part of a conventional active matrix type display device. Scan bus lines 1 ₀ , 1 ₁ , ... Are arranged at predetermined intervals in the pixel row direction on one glass substrate (not shown) of two glass substrates arranged facing each other. The data bus lines 2 ₁ , 2 ₂ , ... Are arranged at predetermined intervals in the pixel column direction orthogonal to the lines 1 ₀ , 1 ₁ ,.

The scan bus lines 1 ₁ , 1 ₂ , ...
- a data bus line 2 _{1, 2} 2, the each pixel of the matrix intersections of the ..., pixel electrodes 3 _11, 3 _12, ...
., 3 ₂₁ , 3 ₂₂ , ..., 3 ₃₁ , 3 ₃₂ , ..., And TFTs (thin film transistors) 4 ₁₁ , 4 ₁₂ as switching elements whose sources are connected to the respective pixel electrodes 3.
.., 4 ₂₁ , 4 ₂₂ , ..., 4 ₃₁ , 4 ₃₂ ,. The gates of the respective TFTs 4 have scan bus lines 1 ₁ , 1 ₂ , ...
.., and the drains are connected to the data bus lines 2 ₁ , 2 ₂ , ... For each pixel column.

On the other hand, the common electrode 5 is provided on the other glass substrate (not shown) arranged to face the glass substrate.
Is provided. Further, a liquid crystal layer (not shown) is formed between the two glass substrates, and a pixel electrode 3, a common electrode 5 also serving as a counter electrode of the pixel electrode 3, and a liquid crystal layer (not shown) 5, liquid crystal cells 6 ₁₁ , 6 ₁₂ , ..., 6 ₂₁ , 6 ₂₂ , ...
.., 6 ₃₁ , 6 ₃₂ , ... further,
The connection point between each pixel electrode 3 and the source of the TFT 4 and the scan bus line 1 of the pixel row one row before (upper side in FIG. 5)
_{, 0} , 1 _1, ... Between the pixel electrodes 3 of each liquid crystal cell 6 and the common electrode 5, storage capacitors 7 ₁₁ , 7 ₁₂ for stabilizing the liquid crystal cell voltage applied. ...., 7 ₂₁ , 7 ₂₂ ,
.., 7 ₃₁ , 7 ₃₂ , ... Are provided respectively.

In such a structure, for example, FIG.
As shown in (c), when the address pulse V _S21 is applied to the scan bus line 1 ₂ at the timing T ₂ ,
TF with gate connected to scan canvas line 1 ₂
T4 _21, 4 _22, since ... are turned on in synchronization with the address pulse V _S21, for example, when the data bus lines 2 ₁ to the data voltage V _D11 (see FIG. 6 (a)) is applied , The difference voltage (V _D11 −) between the data voltage V _D11 and the common voltage V _C1 (see FIG. 6D) applied to the common electrode 5.
V _C1) is written as a liquid crystal cell voltage to the liquid crystal cell 6 _21. At this time, the storage capacitor 7 _21, the difference between the voltage V _S11 which voltage across is applied to the scan bus lines 1 ₁ pixel line before one line and the data voltage V _D11 (see FIG. 6 (b)) The battery is charged until it reaches the voltage (V _D11 −V _S11 ).

[0007] Then, the voltage of scan bus lines 1 ₂ is returned to the off bias voltage V _OFF (see FIG. 6 (c))
If, TFT4 _21, 4 _22, because ... is turned off,
Charges accumulated in the liquid crystal cell 6 ₂₁ and the storage capacitor 7 ₂₁ is retained, as a result, the liquid crystal cell voltage applied to the liquid crystal cell 6 _21, the voltage following the address pulse has been written until applied (V It is held in _D11 -V _C1). The operation of writing the voltage (V _D −V _C ) to the liquid crystal cell 6 described above is similarly performed line-sequentially.

As described above, the effective liquid crystal cell voltage of each liquid crystal cell 6 corresponding to each pixel is the voltage (V _D
Since it is held at −V _C ), the contrast is not lowered and the viewing angle is not narrowed unlike the simple matrix display device. As described above, the storage capacitor 7 is for improving the holding characteristic of the liquid crystal cell voltage applied to the liquid crystal cell 6, and more specifically, the liquid crystal cell caused by the leakage of charges due to liquid crystal resistance or the like. This is to reduce the influence of the voltage drop and the fluctuation of the liquid crystal cell voltage due to the parasitic capacitance between the pixel electrode 3 and the scan bus line 1 or the data bus line 2.

Further, in the above-mentioned conventional active matrix type display device, a driving method of compressing the amplitude of the data voltage V _D is used in order to reduce the power consumption in the driving circuit. For example, in FIG. 5, the electrode of the liquid crystal cell 6 on the grounded side, that is, the common electrode 5
The potential V _C of the scan bus lines 1 ₀ connected to the side electrode which is grounded in the storage capacitor 7, 1 _1, of ..., the potential other than the address pulse V _S applied, the data voltage V _D By switching between the voltages in the opposite direction to the polarity of (1) (potentials V _C1 and V _C2 (see FIG. 6D), and potentials V _S11 and V _S12 (see FIG. 6B)). The amplitude value of the data voltage V _D (see FIG. 6A) is reduced while maintaining the voltage values written in the capacitors 7 and.

[0010]

By the way, in the above-mentioned conventional active matrix type display device, among the plurality of storage capacitors 7 connected to the scan bus line 1 of the same pixel row one row before, a line sequential method is used. Voltage (V _D −
The plurality of storage capacitors 7 connected to the plurality of TFTs 4 which are simultaneously turned on during the writing operation of V _C ) to the liquid crystal cell 4 are applied to the corresponding liquid crystal cell 6 with the data voltage V _D and the common electrode 5. Voltage difference from common voltage V _C (V _D −V _C )
Is written as a liquid crystal cell voltage, and at the same time, the voltage across each of them is the difference between the data voltage V _D and the voltage V _S applied to the scan bus line 1 of the preceding pixel row (V _D −V _S ) Is charged all at once.

At this time, all the charging currents of the plurality of storage capacitors 7 that are charged to the voltage (V _D -V _S ) are concentrated on the scan bus line 1 of the pixel row that is one row before, so that the scan is performed. There is a problem that the voltage of the scan bus line 1 tends to fluctuate due to the wiring resistance of the bus line 1. The voltage fluctuation in the scan bus line 1 becomes a fluctuation of the voltage (V _D −V _S ) written in each storage capacitor 7, and appears as a horizontal striped pattern on the display screen, which is an active matrix display. This has been a cause of marked deterioration in the display quality of the device.

Further, in the above-mentioned conventional active matrix type display device, as described above, the scan bus line 1 of the pixel row one row before is connected to the grounded side electrode of the storage capacitor 7. It is possible to switch the reference voltage for each pixel row in accordance with the polarity of the data voltage, compress the amplitude of the data voltage V _D , and drive so as to reduce power consumption. On the other hand, as one of the driving methods of the active matrix type display device for reducing the flicker, there is a driving method called a data inversion driving method for alternately switching the polarities of the data voltage V _D within one pixel row. In the above, since the reference potential (ground potential) of the storage capacitor 7 must be made common for each pixel row to be written, the above-described method of compressing the amplitude of the data voltage V _D cannot be used together. That is, in the conventional driving method of the active matrix type display device, there is a problem that it is difficult to achieve both reduction of power consumption and reduction of flicker. The present invention has been made under such a background, and an active matrix type display device and a driving method thereof which can improve display quality and can reduce power consumption and flicker at the same time. The purpose is to provide.

[0013]

The invention according to claim 1 is
A plurality of scan bus lines arranged at a predetermined interval in the pixel row direction on one of the two insulating substrates facing each other, and a pixel column direction orthogonal to the plurality of scan bus lines. A plurality of data bus lines arranged at predetermined intervals, a scan bus line provided for each pixel at a matrix intersection of the plurality of scan bus lines and the plurality of data bus lines, and each control end corresponds to the scan bus line. A plurality of switching elements each having an input end connected to a corresponding data bus line, a plurality of pixel electrodes connected to an output end of the switching element corresponding to each of the pixels, and the two insulating elements. A common electrode disposed on the other insulating substrate of the substrate and also serving as a counter electrode of the plurality of pixel electrodes, a liquid crystal layer formed between the two insulating substrates, and one end for each pixel. In an active matrix type display device having a plurality of storage capacitors connected to the output terminals of corresponding switching elements, a plurality of pixels belonging to the same pixel row are divided into at least two pixel groups, and each pixel group corresponds to each pixel group. It is characterized in that the other ends of the plurality of storage capacitors are connected to different scan bus lines for each pixel group other than the scan bus line of the corresponding pixel row.

According to a second aspect of the present invention, a plurality of scan bus lines arranged at a predetermined interval in the pixel row direction on one of the two insulating substrates facing each other, and the plurality of scan bus lines. A plurality of data bus lines arranged at a predetermined interval in the pixel column direction orthogonal to the scan bus line, and provided for each pixel at a matrix intersection of the plurality of scan bus lines and the plurality of data bus lines. Each control terminal is connected to the corresponding scan bus line, and each input terminal is connected to the plurality of switching elements connected to the corresponding data bus line, and the output terminal of the switching element corresponding to each pixel. A plurality of pixel electrodes, a common electrode that is disposed on the other insulating substrate of the two insulating substrates and also serves as a counter electrode of the plurality of pixel electrodes, and is formed between the two insulating substrates. An active matrix type display device including a liquid crystal layer and a plurality of storage capacitors each of which has one end connected to an output end of a corresponding switching element for each pixel, A bus line dedicated to the storage capacitors is provided, a plurality of pixels belonging to the same pixel row are divided into at least two pixel groups, and the other ends of the plurality of storage capacitors corresponding to the respective pixel groups are
It is characterized in that each pixel group is connected to a different storage capacity dedicated bus line.

According to a third aspect of the present invention, in the first aspect of the invention, the common electrode is electrically isolated for each portion corresponding to each pixel group. A fourth aspect of the invention is characterized in that, in the second aspect of the invention, the common electrode is electrically isolated for each portion corresponding to each pixel group.

According to a fifth aspect of the present invention, in the third aspect of the invention, the electrically separated common electrodes are arranged such that the electrode gap portions face the plurality of data bus lines. It is characterized by being. According to a sixth aspect of the invention, in the fourth aspect of the invention, the electrically separated common electrodes are arranged such that the electrode gap portions face the plurality of data bus lines. It is characterized by that.

The invention according to claim 7 is the invention according to claim 3 or 5.
In the driving method of the active matrix type display device for driving the active matrix type display device described,
The common electrodes having two voltage values and different phases are respectively applied to the electrically separated common electrodes, and the plurality of scan bus lines are respectively supplied at each timing except when an address pulse is applied. In addition, a pulse having the same waveform as each of the common voltages is applied.

The invention according to claim 8 is the invention according to claim 4 or 6.
In the driving method of the active matrix type display device for driving the active matrix type display device described,
Common voltages having two voltage values and different phases are respectively applied to the electrically separated common electrodes, and the same common voltage is applied to each of the plurality of storage capacitor dedicated bus lines. The feature is that each pulse of a waveform is applied.

[0019]

According to the first and second aspects of the present invention, the charge / discharge current for charging / discharging a plurality of storage capacitors flowing in one scan bus line during the write operation of the data voltage is reduced as compared with the conventional one, and the scan bus line is reduced. The voltage fluctuation due to the wiring resistance of is reduced compared with the conventional one. According to the invention described in claims 3 to 8, it is possible to achieve both reduction of power consumption and reduction of flicker. According to the invention described in claims 5 to 8, the parasitic capacitance between each common electrode and each data bus line can be reduced.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an equivalent circuit diagram showing a partial configuration example of an active matrix type display device according to the first embodiment of the present invention. In this figure, parts corresponding to respective parts in FIG. , The description is omitted. In the active matrix type display device shown in this figure, a scan bus line 1 _-1 is newly provided.
Then, the scan bus line _1-1 has a storage capacitor 7 ₁₁ ,
7 _13, is connected to each grounded by side electrodes ..., the scan bus lines 1 _0, the storage capacitor 7 _12,
The electrodes on the grounded side of 7 ₁₄ , ... And the storage capacitors 7 ₂₂ , 7 ₂₄ ,. Similarly, in the scan bus line 1 ₁ , the storage capacitors 7 ₂₁ ,
7 _23, ..., and the storage capacitor 7 _31, 7 _33, each grounded by side electrodes ... are connected to the scan bus line 1 _2, the storage capacitor 7 _32, 7 _34, ... and the storage capacitor 7 _42, 7 _{4 4,} the side of the electrode which is grounded, ... are connected.

Further, in FIG. 1, instead of the common electrode 5, common electrodes 8 ₁ , 8 ₂ , ... Are arranged in a stripe pattern for each pixel column, and the common electrode 8 corresponding to an odd pixel column is arranged. ₁ ,
8 _3, ... they are connected at the outer of each display area, the common electrode ₈₂ corresponding to the even-numbered pixel columns, 8 _4, is also connected at the outside of the display area,. The common electrode 8 ₁ also serves as a counter electrode for the pixel electrodes 3 ₁₁ , 3 ₂₁ , ... And the common electrode 8 ₂ serves as a counter electrode for the pixel electrodes 3 ₁₂ , 3 ₂₂ ,. 8 ₃ is the pixel electrodes 3 ₁₃ , 3 ₂₃ ,
Also serves as the counter electrode of.

The structure of the active matrix type display device described above can be expressed more generally as follows. That is, the grounded electrode of the storage capacitor 7 corresponding to the odd-numbered pixel of the odd-numbered pixel row is connected to the scan bus line 1 of the pixel row two rows before, and corresponds to the even-numbered pixel of the odd-numbered pixel row. The grounded electrode of the storage capacitor 7 is connected to the scan bus line 1 of the preceding pixel row, and the grounded electrode of the storage capacitor 7 corresponding to the odd-numbered pixel of the even pixel row is The electrode on the grounded side of the storage capacitor 7 connected to the scan bus line 1 of the pixel row one row before and corresponding to the even-numbered pixel of the even pixel row is the scan bus line 1 of the pixel row two rows before. It is connected to the. Separate common electrodes 8 are provided for each odd pixel column and each even pixel column.

[0023] In such a configuration, first, for example, as shown in FIG. 2 (d), when the scan bus line 1 ₃ at timing T ₃ the address pulse V _S31 is applied, the gate to the scan bus line 1 ₃ Since the TFTs 4 ₃₁ , 4 ₃₂ , ... To which are connected are turned on,
In synchronization with the address pulse V _S31 , for example, the data voltage V _D11 (see FIG. 2A) is applied to the data bus lines 2 ₁ and 2 ₂ .
Reference) and V _D21 (not shown), the data voltage V _D11 and the first common voltage V 1 applied to the common electrode 8 _1.
Voltage (V _D11 -V _C11 ) which is the difference from _C11 (see Fig. 2 (e))
Is written in the liquid crystal cell 6 ₃₁ as a liquid crystal cell voltage and is applied to the common electrode 8 ₂ and the data voltage V _D21 .
The voltage (V _D21 ) which is the difference from the common voltage V _C21 (see FIG. _2F )
-V _C21) is written as a liquid crystal cell voltage to the liquid crystal cell 6 _{3 2.}

At this time, the storage capacitor 7 ₃₁ has a voltage at both ends thereof as a data voltage V _D11 and a voltage V _S13 (see FIG. 2B) applied to the scan bus line 1 ₁ of the pixel row two rows before. Is charged up to the voltage (V _D11 −V _S13 ) of the difference between the two, and the voltage across the storage capacitor 7 ₃₂ is the data voltage V.
The voltage (V _D21 ) which is the difference between _D21 and the voltage V _S22 (see FIG. 2C) applied to the scan bus line 1 ₂ of the pixel line _immediately preceding
While being charged to a -V _S22), the charging current of the storage capacitor 7 ₃₁ flows into the second line scan bus line 1 ₁ of the previous pixel row, the charging current of the storage capacitor 7 _32, 1 row previous pixel It flows into the scan bus line 1 ₂ of the row.

Next, the voltage of scan bus lines 1 ₃ is returned to the off bias voltage V _OFF (FIG. 2 (d) see)
And the TFTs 4 ₃₁ , 4 ₃₂ , ... Are turned off,
The charges accumulated in the liquid crystal cells 6 ₃₁ , 6 ₃₂ and the storage capacitors 7 ₃₁ , 7 ₃₂ are retained, and as a result, the liquid crystal cell voltage applied to the liquid crystal cells 6 ₃₁ , 6 ₃₂ is applied with the next address pulse. _Are held at the written voltages (V _D11 -V _C11 ) and (V _D21 -V _C21 ) until they are written. The operation of writing the voltage (V _D −V _C ) to the liquid crystal cell 6 described above is similarly performed line-sequentially.

As described above, the pixels belonging to the same pixel row are divided into two pixel groups, and the electrodes on the grounded side of the plurality of storage capacitors 7 corresponding to each pixel group are scanned differently for each pixel group. Since it is connected to the bus line 1, the number of the liquid crystal cells 6 which are connected to one scan bus line 1 and at the same time the voltage (V _D −V _C ) write operation is performed is half the conventional number.
become. Therefore, a plurality of storage capacitors 7 flowing in one scan bus line during the voltage (V _D −V _C ) write operation
The charging / discharging current for charging / discharging is reduced to half of the conventional one, and the voltage fluctuation due to the wiring resistance of the scan bus line 1 can be halved compared to the conventional one. As a result, the display quality is improved.

In the active matrix type display device according to the first embodiment of the present invention described above, in order to reduce both the power consumption and the flicker in the drive circuit, a drive method for compressing the amplitude of the data voltage V _D is used. The data inversion driving method is used together. That is, the common electrodes 8 ₁ , 8 ₃ , ... Corresponding to the odd pixel columns and the common electrodes 8 ₂ , 8 ₄ , ... Corresponding to the even pixel columns are shown in FIG.
As shown in (e) and (f), the first common voltage V _C1 and the second common voltage V _C2 whose phases are opposite to each other are applied, respectively, and the address pulses V _S11 , V _S21 , ...
・ Fig. 2 (b)-
As shown in (d), a pulse having the same waveform as the first common voltage V _C1 is applied to the scan bus lines 1 ₁ , 1 ₃ , ... Of the odd pixel columns to scan the scan bus lines 1 ₂ of the even pixel columns. ，
A pulse having the same waveform as the second common voltage V _C2 is applied to 1 ₄ ...

As a result, in the same pixel row, the potentials of the electrodes on the grounded side of the liquid crystal cell 6 and the storage capacitor 7 corresponding to each pixel are the same in polarity between two adjacent pixels. Since the potentials can be different, the data voltage V _D can be compressed and the data inversion driving method can be used. Further, if the striped common electrodes 8 ₁ , 8 ₂ , ... Are arranged so that the electrode gap portions face the data bus lines 2 ₁ , 2 ₂ ,. The parasitic capacitance between each data bus line 2 can be reduced, and the influence of crosstalk or the like caused by this parasitic capacitance on the display screen can be reduced.

Next, a second embodiment of the present invention will be described. FIG. 3 is an equivalent circuit diagram showing a partial configuration example of the active matrix type display device according to the second embodiment of the present invention. In this figure, parts corresponding to the respective parts of FIG. , The description is omitted. In the active matrix type display device shown in this figure, instead of the scan bus lines 1 _-1 , 1 ₀ , storage capacity dedicated bus lines 9 ₀ , 9 ₁ , ... Are newly provided. The storage capacity dedicated bus line 9 ₀ has a storage capacity 7 ₁₁ ,
7 _13, is connected to each grounded by side electrodes ..., storage capacitance dedicated to the bus line 9 _1, the storage capacitor 7 _12,
The electrodes on the grounded side of 7 ₁₄ , ... And the storage capacitors 7 ₂₂ , 7 ₂₄ ,. Similarly, the storage capacity dedicated bus line 9 ₂ is connected to the storage capacity 7 ₂₁ ,
, ₂₃ and storage capacitors 7 ₃₁ , 7 ₃₃ , ... are respectively connected to the grounded electrodes, and the storage capacitor dedicated bus line 9 ₃ is connected to the storage capacitors 7 ₃₂ , 7 ₃₄ ,. .. and the storage capacitors 7 ₄₂ , 7 ₄₄ , ... Are connected to the grounded electrodes.

The structure of the active matrix type display device described above can be expressed more generally as follows. That is, the grounded side electrode of the storage capacitor 7 corresponding to the odd-numbered pixel of the odd-numbered pixel row is connected to the storage-capacitor dedicated bus line 9 of the pixel row one row before, and the even-numbered pixel of the odd-numbered pixel row is connected. The grounded side electrode of the storage capacitor 7 corresponding to is connected to the storage capacitor dedicated bus line 9 of the corresponding pixel row, and the grounded side of the storage capacitor 7 corresponding to the odd-numbered pixel of the even pixel row is connected. The electrode is connected to the bus line 9 dedicated to the storage capacitor of the corresponding pixel row, and the grounded side electrode of the storage capacitor 7 corresponding to the even-numbered pixel of the even pixel row is the storage of the previous pixel row. It is connected to the dedicated capacity bus line 9. In addition, like the first embodiment described above,
Separate common electrodes 8 are provided for each odd pixel column and each even pixel column.

[0031] In such a configuration, first, for example, as shown in FIG. 4 (c), when the scan bus line 1 ₃ at timing T ₃ the address pulse V _S31 is applied, the gate to the scan bus line 1 ₃ Since the TFTs 4 ₃₁ , 4 ₃₂ , ... To which are connected are turned on,
In synchronization with the address pulse V _S31 , for example, the data voltage V _D11 (see FIG. 4A) is applied to the data bus lines 2 ₁ and 2 ₂ .
Reference) and V _D21 (not shown), the data voltage V _D11 and the first common voltage V 1 applied to the common electrode 8 _1.
Voltage (V _D11 -V _C11 ) which is the difference from _C11 (see Fig. 4 (f))
Is written in the liquid crystal cell 6 ₃₁ as a liquid crystal cell voltage and is applied to the common electrode 8 ₂ and the data voltage V _D21 .
The voltage (V _D21 ) which is the difference from the common voltage V _C21 (see FIG. _4G )
-V _C21) is written as a liquid crystal cell voltage to the liquid crystal cell 6 _{3 2.}

At this time, the storage capacitor 7 ₃₁ has a voltage across the data voltage V _D11 and a voltage V _R21 applied to the storage capacitor-dedicated bus line 9 ₂ of the preceding pixel row (see FIG. 4 (d)). )
Applied while being charged to a difference between the voltage (V _D11 -V _R21), the storage capacitor 7 _32, the storage capacitor dedicated bus line 9 ₃ pixel row voltage across correspond to the data voltage V _D21 with It is charged until it reaches a voltage (V _D21 -V _R31 ) which is the difference from the voltage V _R31 (see FIG. 4 (e)) that is stored in the storage capacitor 7.
The charging current of ₃₁ flows into the storage capacitor dedicated bus line 9 ₂ of the preceding pixel row, and the charging current of the storage capacitor 7 ₃₂ flows into the storage capacitor dedicated bus line 9 ₃ of the corresponding pixel row.

Next, the voltage of the scan bus line 1 ₃ becomes 0
When it is returned to V (see FIG. 4 (c)), the TFT4 ₃₁ ,
Since the liquid crystal cells 4 ₃₂ , ... Are turned off, the liquid crystal cells 6 ₃₁ , 6,
_The charges accumulated in ₃₂ and the storage capacitors 7 ₃₁ , 7 ₃₂ are retained, and as a result, the liquid crystal cell voltage applied to the liquid crystal cells 6 ₃₁ , 6 ₃₂ is written until the next address pulse is applied. Voltage (V _D11 −V _C11 ) and (V _D21 −
V _C21 ). The operation of writing the voltage (V _D −V _C ) to the liquid crystal cell 6 described above is similarly performed line-sequentially.

As described above, the pixels belonging to the same pixel row are divided into two pixel groups, and the electrodes on the grounded side of the plurality of storage capacitors 7 corresponding to each pixel group are stored differently for each pixel group. Since it is connected to the capacity dedicated bus line 9, it is connected to one storage capacity dedicated bus line 9 and at the same time the voltage (V _D −
The number of the liquid crystal cells 6 in which the writing operation of V _C ) is performed becomes one half of the conventional one. Therefore, the charging / discharging current for charging / discharging the plurality of storage capacitors 7 flowing in one storage capacitor dedicated bus line 9 during the voltage (V _D −V _C ) write operation becomes half that of the conventional one, and the storage becomes It is possible to reduce the voltage fluctuation due to the wiring resistance of the bus line 9 for exclusive use of the capacity by half as compared with the conventional case. As a result, the display quality is improved.

Further, in the active matrix type display device according to the second embodiment of the present invention described above, in order to reduce both power consumption and flicker in the drive circuit, a drive method for compressing the amplitude of the data voltage V _D is used. The data inversion driving method is used together. That is, the common electrodes 8 ₁ , 8 ₃ , ... Corresponding to the odd pixel columns and the common electrodes 8 ₂ , 8 ₄ , ... Corresponding to the even pixel columns are shown in FIG.
As shown in (f) and (g), the first common voltage V _C1 and the second common voltage V _C2 whose phases are inverted to each other are applied, respectively, and as shown in (d) and (e) of FIG. , Bus lines 9 ₂ , 9 ₄ , dedicated to the storage capacitors of even pixel columns
A pulse having the same waveform as the first common voltage V _C1 is applied to the bus lines 9 ₁ and 9 ₃ dedicated to the storage capacitors of the odd pixel columns.
A pulse having the same waveform as the second common voltage V _C2 is applied to.

As a result, in the same pixel row, the potentials of the electrodes on the grounded side of the liquid crystal cell 6 and the storage capacitor 7 corresponding to each pixel are the same in polarity between two adjacent pixels. Since the potentials can be different, the data voltage V _D can be compressed and the data inversion driving method can be used. Further, similar to the first embodiment described above, the striped common electrodes 8 ₁ , 8 ₂ ,
..., where the electrode gaps are data bus lines 2 ₁ , 2 ₂ ,
, So that the parasitic capacitance between each common electrode 8 and each data bus line 2 can be reduced, and crosstalk or the like generated by this parasitic capacitance to the display screen can be reduced. The effect can also be reduced.

Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments, and the design can be changed without departing from the gist of the present invention. Etc. are included in the present invention. For example, in the above-described first and second embodiments, the example in which the pixels belonging to the same pixel row are divided into two pixel groups is shown, but the present invention is not limited to this, and the pixels belonging to the same pixel row are divided into three groups. The electrodes on the grounded side of the plurality of storage capacitors 7 corresponding to each pixel group are connected to the scan bus line 1 or the storage capacitor dedicated bus line 9 which is different for each pixel group. You may comprise. As a result, the voltage fluctuation due to the wiring resistance of the scan bus line 1 or the storage capacitor dedicated bus line 9 can be further reduced as compared with the conventional case.

Pixels belonging to the same pixel row are preferably divided into an even number of pixel groups. This is because the plurality of pixel groups are divided into a pixel group including only odd-numbered pixel rows and a pixel group including only even-numbered pixel rows, and separate common electrodes 8 are provided for the former and the latter. , The common electrode 8 corresponding to the odd pixel columns and the common electrode 8 corresponding to the even pixel columns
In addition to the application of the first and second common voltages whose phases are inverted to each other, in the modification of the first embodiment, the scan bus of the odd-numbered pixel columns is provided at each timing except when the address pulse V _{S is} applied. A pulse having the same waveform as the first common voltage is applied to the line 1, and a pulse having the same waveform as the second common voltage is applied to the scan bus line 1 of the even-numbered pixel column. In the modification of the second embodiment, the even number is used. A pulse having the same waveform as the first common voltage can be applied to the storage capacitor dedicated bus line 9 of the pixel column, and a pulse having the same waveform as the second common voltage can be applied to the storage capacitor dedicated bus line 9 of the odd pixel column. Is. As a result, in the same pixel row, the potentials of the electrodes of the liquid crystal cell 6 and the storage capacitor 7 corresponding to each pixel on the grounded side are both set to the potentials having different polarities between two adjacent pixels. Since it is possible to compress the data voltage V _D ,
A data inversion driving method can also be used.

Further, in the above-described first and second embodiments, the pixels belonging to the same pixel row are divided into two pixel groups, and the plurality of storage capacitors 7 corresponding to each pixel group are connected to the grounded side. The scan bus line 1, which has different electrodes for each pixel group,
Alternatively, an example has been shown in which the common electrode 8 is connected to the storage capacitor dedicated bus line 9 and is provided separately for each odd pixel column and each even pixel column, but the present invention is not limited to this, and only one of the configurations is provided. In order to obtain only the effect of reducing the voltage fluctuation due to the wiring resistance of the scan bus line 1 or the bus line 9 for exclusive use of the storage capacitor, or the combined effect of the data voltage compression method and the data inversion driving method. Good.

[0040]

As described above, according to the present invention,
There is an effect that the display quality can be improved.
Further, there is an effect that both reduction of power consumption and reduction of flicker can be achieved at the same time. Further, according to the invention described in claims 5 to 8, there is an effect that the parasitic capacitance between each common electrode and each data bus line can be reduced. Therefore, it is possible to reduce the influence on the display screen such as crosstalk caused by the parasitic capacitance.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a partial configuration of an active matrix display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a driving method of the active matrix display device shown in FIG.

FIG. 3 is an equivalent circuit diagram showing a partial configuration of an active matrix display device according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining a driving method of the active matrix display device shown in FIG.

FIG. 5 is an equivalent circuit diagram showing a partial configuration example of a conventional active matrix type display device.

6 is a timing chart for explaining a driving method of the active matrix display device shown in FIG.

[Explanation of symbols]

1 _-1 , 1 ₀ , 1 ₁ , ... scan canvas line 2 ₁ , 2 ₂ , 2 ₃ , ... data bus line 3 ₁₁ , 3 ₁₂ , ..., 3 ₂₁ , 3 ₂₂ , ... , 3 ₃₁ ,
3 ₃₂ , ... Pixel electrodes 4 ₁₁ , 4 ₁₂ , ..., 4 ₂₁ , 4 ₂₂ , ..., 4 ₃₁ ,
4 ₃₂ , ... TFTs 5, 8 ₁ , 8 ₂ , 8 ₃ , ... Common electrodes 6 ₁₁ , 6 ₁₂ , 6, ₂₁ , 6 ₂₂ , 6 ₂₂ , 6 ₃₁ ,
6 ₃₂ , ... Liquid crystal cell 7 ₁₁ , 7 ₁₂ , ..., 7 ₂₁ , 7 ₂₂ , ..., 7 ₃₁ ,
7 ₃₂・ ・ ・ Storage capacity 9 ₁ , 9 ₂ , 9 ₃ , ・ ・ ・ Storage capacity dedicated bus line

Claims (8)

[Claims] 1. A plurality of scan bus lines arranged at predetermined intervals in the pixel row direction on one of the two insulating substrates facing each other, and orthogonal to the plurality of scan bus lines. A plurality of data bus lines arranged at a predetermined interval in the pixel column direction, and each control end provided for each pixel at a matrix intersection of the plurality of scan bus lines and the plurality of data bus lines. A plurality of switching elements connected to corresponding scan bus lines, each input terminal connected to a corresponding data bus line, and a plurality of pixel electrodes connected to output terminals of the switching elements corresponding to each of the pixels; A common electrode disposed on the other insulating substrate of the two insulating substrates and also serving as a counter electrode of the plurality of pixel electrodes; a liquid crystal layer formed between the two insulating substrates; In an active matrix type display device having a plurality of storage capacitors each end of which is connected to an output end of a corresponding switching element for each pixel, a plurality of pixels belonging to the same pixel row is divided into at least two pixel groups, An active matrix display characterized in that the other ends of a plurality of storage capacitors corresponding to each pixel group are connected to different scan bus lines for each pixel group other than the scan bus line of the corresponding pixel row. apparatus. 2. A plurality of scan bus lines arranged at predetermined intervals in the pixel row direction on one of the two insulating substrates facing each other, and orthogonal to the plurality of scan bus lines. A plurality of data bus lines arranged at a predetermined interval in the pixel column direction, and each control end provided for each pixel at a matrix intersection of the plurality of scan bus lines and the plurality of data bus lines. A plurality of switching elements connected to corresponding scan bus lines, each input terminal connected to a corresponding data bus line, and a plurality of pixel electrodes connected to output terminals of the switching elements corresponding to each of the pixels; A common electrode disposed on the other insulating substrate of the two insulating substrates and also serving as a counter electrode of the plurality of pixel electrodes; a liquid crystal layer formed between the two insulating substrates; In an active matrix display device having a plurality of storage capacitors each of which has one end connected to an output terminal of a corresponding switching element, a plurality of storage capacitor dedicated bus lines are provided in parallel with the plurality of scan bus lines. At the same time, a plurality of pixels belonging to the same pixel row are divided into at least two pixel groups, and the other ends of the plurality of storage capacitors corresponding to the pixel groups are connected to different storage capacitor dedicated bus lines for each pixel group. An active matrix display device characterized by the above. 3. The active matrix display device according to claim 1, wherein the common electrode is electrically isolated for each portion corresponding to each pixel group. 4. The active matrix type display device according to claim 2, wherein the common electrode is electrically isolated for each portion corresponding to each pixel group. 5. The electrically separated common electrodes include:
4. The active matrix type display device according to claim 3, wherein each electrode gap portion is arranged so as to face the plurality of data bus lines. 6. The common electrodes, which are electrically separated,
The active matrix type display device according to claim 4, wherein each electrode gap portion is arranged so as to face the plurality of data bus lines. 7. The method for driving an active matrix type display device according to claim 3, wherein the electrically separated common electrodes have two voltage values. A common voltage having a different phase is applied, and a pulse having the same waveform as the common voltage is applied to each of the plurality of scan bus lines at each timing except when an address pulse is applied. Driving method for active matrix display device. 8. The method for driving an active matrix type display device according to claim 4, wherein the electrically separated common electrodes have two voltage values. A method of driving an active matrix display device, characterized in that common voltages having different phases are applied, and a pulse having the same waveform as the common voltage is applied to each of the plurality of storage capacitor dedicated bus lines. .