JP2516462B2 - Active matrix liquid crystal display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] An active matrix type liquid crystal display device of a facing matrix type, which is intended to reduce crosstalk and improve display quality. Two substrates arranged to face each other with a liquid crystal interposed therebetween. On one side, a plurality of scan bus lines, a thin film transistor, a display electrode, and a reference potential supply bus line are formed, the gate of the thin film transistor is the scan bus line, and one of the source and the drain is the display electrode, The other is connected to the reference potential supply bus line,
In an active matrix type liquid crystal display device of the opposed matrix type in which a plurality of stripe-shaped data bus lines facing the display electrodes are formed on the other of the substrates, the liquid crystal display device extends in a direction orthogonal to the data bus lines. First and second scan bus lines having common terminals are arranged in parallel on both sides of the reference potential supply bus line.

[Industrial applications]

The present invention relates to a counter matrix type active matrix liquid crystal display device.

Since the active matrix type liquid crystal display device is thin like the simple matrix type liquid crystal display device, it is widely used as various display devices. Since this active matrix type liquid crystal display device is driven independently for each pixel, even if the number of lines is increased as the display capacity is increased, the drive duty of the simple matrix type liquid crystal display device is increased. There is no problem of reduction in contrast and reduction in viewing angle due to the reduction. Therefore, the active matrix type liquid crystal display device is capable of color display similar to that of a cathode ray tube (CRT), and its application as a flat display device is expanding.

However, the active matrix type liquid crystal display device has a thin film transistor or the like as a switching element provided for each pixel, which complicates the manufacturing process. In the case of manufacturing a large-screen display device, a large-scale manufacturing device is required. Since a device is required, the manufacturing equipment cost is high and the manufacturing yield is low, which is very expensive. Therefore, the current practical panels are limited to relatively small panels.

Further, in order to improve the reduction in manufacturing yield caused by the complexity of the structure of the active matrix type liquid crystal display device, the scan bus line and the data bus line are formed on separate substrates, and the bus on the same substrate is formed. There has been proposed an active matrix type liquid crystal display device of an opposed matrix type in which line intersections are eliminated, and further improvement in display quality is demanded.

[Conventional technology]

A conventional general type active matrix type liquid crystal display device has a structure in which scan bus lines and data bus lines are formed orthogonally on the same substrate, and display electrodes are connected to the intersections thereof via thin film transistors. , For example, can be represented by an equivalent circuit shown in FIG. That is, a scan bus line 71 and a data bus line 72 are formed orthogonally on one of two substrates such as glass which face each other with a liquid crystal interposed therebetween, and their intersections are insulated from each other. The gate 75 of the thin film transistor 73 is connected to the scan bus line 71, the drain 76 is connected to the data bus line 72, the source 77 is connected to the display electrode constituting the liquid crystal cell 74, and the common is shown as ground 78 on the other substrate. The electrodes are formed.

Such an active matrix type liquid crystal display device is
Scan bus line 71 and data bus line on the same board
Since 72 and 72 are formed so as to intersect with each other, insulation failure or short circuit may occur at the intersection, and disconnection may occur in the bus line in the upper layer due to the step at the intersection. Therefore, there is a limit to the thickening of the lower bus line and the insulating layer, so it is not easy to reduce the resistance of the lower bus line, and since the insulating layer cannot be thickened, the short circuit at the crossing point is completely eliminated. It was difficult to prevent.

Therefore, there has been proposed an active matrix type liquid crystal display device of the opposed matrix type in which the scan bus lines and the data bus lines are formed on one and the other of the substrates which are arranged so as to face each other. FIG. 12 shows a schematic exploded perspective view of the opposed matrix type active matrix type liquid crystal display device, and FIG. 13 shows an equivalent circuit thereof. That is, one glass substrate 80 and the other glass substrate 89 are opposed to each other with a liquid crystal interposed therebetween, and stripe-shaped data bus lines 82 are formed on one glass substrate 80 and the other glass substrate 89 is formed. Includes a scan bus line 81, a thin film transistor 83, and a display electrode 84a forming a liquid crystal cell 84.
And a reference potential supply bus line 88 (shown as ground in FIG. 13) are formed.

Liquid crystal is filled between the stripe-shaped data bus line 82 and the display electrode 84a to form a liquid crystal cell 84. The liquid crystal cell 84 is connected between the data bus line 82 and the drain 86 of the thin film transistor 83. The gate 85 of the thin film transistor 83 is connected to the scan bus line 81,
The source 83 of the thin film transistor 83 is connected to the reference potential supply bus line 88.

With such a configuration, the data bus line 82 and the scan bus line 81 are arranged orthogonally via the liquid crystal, but since they do not intersect on the same substrate, there is no need to form an insulating layer at the intersection, Will be easier. Further, since the short circuit does not occur between the data bus line 82 and the scan bus line 81, display defects are reduced and the manufacturing yield can be improved.

[Problems to be Solved by the Invention]

As compared with the conventional general type active matrix type liquid crystal display device, the counter matrix type active matrix type liquid crystal display device has a problem that crosstalk becomes large. That is, the capacitance between the scan bus lines 71, 81 to which the gates of the thin film transistors 73, 83 are connected and the display electrodes constituting the liquid crystal cells 74, 84 is C _gp , and the display electrodes and the data bus lines 72 are Or between the display electrode and the reference potential supply bus line 88, that is, the thin film transistor.
The capacitance between the source and drain of 73 and 83 is C _dp , the capacitance of the liquid crystal cells 74 and 84 is C _LC , and the fluctuation of the liquid crystal cell voltage is Δ.
Let V _{LC be} the fluctuation of the data voltage and ΔV _D be the capacitive coupling ratio α1 (= ΔV _LC
/ ΔV _D ), and the capacitive coupling ratio α in the case of the opposed matrix format
2 is α1 = _Cdp / ( _Cgp + _Cdp + _CLC ) (1) α2 = ( _Cgp + _Cdp ) / ( _Cgp + _Cdp + _CLC ) (2).

Therefore, since α1 <α2, it can be understood that the crosstalk of the active matrix type liquid crystal display device of the opposed matrix type becomes large. That is, in the active matrix type liquid crystal display device of the opposed matrix type, even if the thin film transistor 83 is in the off state, the data voltage sequentially applied to the data bus line 82 is in parallel with the liquid crystal cell 84. Since the voltage is applied via the capacitances C _gp and C _dp , the voltage of the liquid crystal cell changes due to the data voltage for the other liquid crystal cells, and there is a drawback that the display quality deteriorates.

Further, in the conventional general type active matrix type liquid crystal display device, it is possible to add a storage capacitor to reduce the capacitive coupling ratio α1, but in the counter matrix type active matrix type liquid crystal display device, such a storage type is used. Since it is difficult to add capacitance, it is difficult to reduce the capacitive coupling ratio α2. Further, the DC voltage level shift immediately after selecting the scan bus line 81 connected to the gate 85 of the thin film transistor 83 has a drawback that an afterimage phenomenon becomes large because it is difficult to add a storage capacitor, and in particular, a static image is generated. In the case of an image, there is a drawback that the image sticking phenomenon occurs and the display quality is deteriorated.

It is an object of the present invention to reduce crosstalk and compensate for DC voltage level shift to improve display quality.

[Means for solving the problem]

The active matrix type liquid crystal display device of the present invention has a counter-matrix type structure and has a small capacitive coupling ratio, and will be described with reference to FIG.

According to a first aspect of the present invention, a plurality of scan bus lines 1, thin film transistors 2, display electrodes 3, and reference potential supply bus lines 4 are formed on one of two substrates such as glass which are opposed to each other with a liquid crystal interposed therebetween. The gate of the thin film transistor 2 is connected to the scan bus line 1, one of the source and the drain is connected to the display electrode 3, and the other is connected to the reference potential supply bus line 4, and the display electrode 3 is connected to the other of the two substrates. Striped data bus lines 5 facing each other
In the active matrix type liquid crystal display device of the opposed matrix type in which the terminals are formed, the first and second common terminals having common terminals are provided on both sides of the reference potential supply bus line 4 extending in the direction orthogonal to the data bus line 5. Canvas line
1 ₁ and 1 ₂ are arranged in parallel.

In the second invention, the gates of the _first and second thin film transistors 2 ₁ and 2 ₂ each having either the source or the drain connected to the reference potential supply bus line 4 are connected to both sides of the reference potential supply bus line 4. Connected to the first and _second scan bus lines 11 ₁ and 12 respectively, and the other of the source and the drain is connected to the display electrode 3 arranged adjacent to the data bus line 5 in the parallel direction. Is.

The third aspect of the present invention is further the first and second aspects in which the terminals are arranged in parallel on both sides of the reference potential supply bus line 4 and with common terminals.
An extension portion that extends between the display electrodes 3 along the extension direction of the data bus line 5 on the second scan bus line 1 ₂ that is located at the rear of the scan bus lines 1 ₁ and 1 _{2 in} the scan direction. Is formed.

The fourth aspect of the invention is located in the rear of the scanning direction of the first and _second scan bus lines 1 ₁ and 1 ₂ which are arranged in parallel on both sides of the reference potential supply bus line 4 and have common terminals. the distance between the second scan bus lines 1 ₂ and the display electrodes 3,
The distance is narrower than the distance between the display electrode 3 and the _first scan bus line 11 located at the front in the scanning direction.

The fifth invention is, either one city and second of the first thin film transistor 2 ₁ a n-channel and p-channel type in the invention, the second thin film transistor 2 ₂ n-channel type and p
Either of the channel type and the other type.

A sixth aspect of the present invention has a configuration in which the reference potential applied to the reference potential supply bus line 4 is switched and driven so as to alternately have two levels of potential for each horizontal scanning period for sequentially selecting the scan bus lines. It is a thing.

In the seventh invention, when the liquid crystal applied voltage for the brightest display is V _br and the liquid crystal applied voltage for the darkest display is V _dk , the reference potential of the reference potential supply bus line 4 is changed. The difference between the two levels is set in the relationship of V _br + V _dk .

In the eighth invention, the capacitance between the display electrode 3, the second scan bus line 1 _{2 at} the front in the scanning direction and the first scan bus line 1 ₁ at the rear is C ₁ , C ₂ and
The display first scan bus line electrodes 3 in the scanning direction after position 1 ₁ to apply a scan voltage V _g, and the second scan bus lines 1 ₂ in the scanning direction before position, V _g × (C ₂ /
The configuration is such that a negative voltage of the same value or a value close to that of C ₁ ) is applied.

The ninth invention applies the scan voltage V _g to the first scan bus line ₁₁ which is rearward in the scan direction with respect to the display electrode 3, and the second scan electrode which is forward in the scan direction with respect to the display electrode 3. negative scan bus line 1 _2, the first scan bus lines 1 _{1 and, V g × (C 2 /} C 1) and the same or similar values for the other display electrode 3 adjacent to the scanning direction after position It is configured to apply a voltage.

A tenth aspect of the invention is to alternately select scan bus line terminals of odd-numbered rows and even-numbered rows for each field by interlaced scanning and sequentially apply a scan voltage V _g to the scan bus line terminals adjacent to both sides of the scan bus line terminals. The negative voltage having the same value as or a value close to V _g × (C ₂ / C ₁ ) is applied to the scan line terminal.

[Action]

In the first invention, the first on either side of the reference potential supplying bus line 4, by which the second scan bus lines 1 _1, 1 ₂ are arranged, between the reference potential supplying bus line 4 and the display electrodes 3 The cross-talk can be reduced by reducing the electrostatic capacitance of.

The first on either side of the reference potential supplying bus line 4 1, as the second scan bus lines 1 _1, 1 ₂ a _{set, S i, S i + 1} , S i + 2, ·
.. and the liquid crystal cells are P _i , P _{i + 1} , ..., As shown on the right side, the data voltage is applied to the data bus line 5 and the reference potential is applied to the reference potential supply bus line 4. , Scan voltage (address voltage) V _{g on} the scan bus line S _i
The application of the display electrodes 3 of the liquid crystal cell P _i is a state of being connected to the reference potential supply bus line 4 via the second thin film transistor 2 _2, a difference voltage between the data voltage and the reference potential to the liquid crystal cell P _i When a scan voltage V _g is applied to the scan bus line S _{i + 1} next, the display electrode 3 of the liquid crystal cell P _i is applied.
Is in a state of being connected to a reference potential supply bus line 4 via the first thin film transistor 2 _1, the difference voltage between the data voltage and the reference potential is applied to the liquid crystal cell P _i, the liquid crystal cell voltage as shown in the lower right Is retained.

In the second invention, the source or drain is connected to the reference potential supply bus line 4, the drain or source is connected to the display electrode 3, and the first and second scan bus lines 1 ₁ , 1 ₂
The first and second thin film transistors 2 ₁ , whose gates are connected to
By providing 2 ₂ , two thin film transistors 2 ₁ and 2 ₂ are connected to one display electrode 3, and when one thin film transistor is inoperative, the other thin film transistor operates. Is not a display defect,
The manufacturing yield can be improved.

The third invention has provided an extension extending from the second scan bus lines 1 ₂ between the display electrodes 3, a second scan bus lines of the display electrode 3 the scan direction prior position
Capacitance C ₁ between 1 and ₂ is the capacitance between the display electrode 3 and the first scan bus line 1 ₁ which is rearward in the scanning direction.
The compensation voltage can be made smaller by making it larger than C ₂ .

A fourth aspect of the invention is to reduce the distance between the display electrode 3 and the second scan bus line 1 ₂ which precedes the display electrode 3 in the scanning direction by reducing C ₁ > C ₂
The relationship is to be

The fifth invention is the first thin film transistor 2 ₁ is an n-channel transistor, the second thin film transistor 2 ₂ is intended to or with its opposite and p-channel type, positive and negative one polarity scan Scan voltage sequentially bus line
By applying to S _i , S _{i + 1} , ..., One of the first and second thin film transistors 2 ₁ , 2 ₂ is sequentially turned on,
The other is surely turned off. Also, when positive and negative the other one of the polarities sequentially applies a scan voltage, the first, second thin film transistor 2 _1, 2 ₂ of the other one is sequentially turned on, the other is surely turned off. Therefore, by performing the driving as shown in FIG. 6, the writing operation is performed on each display electrode through the two n-channel and p-channel thin film transistors during one horizontal scanning period, and any of the transistors has a defect. Even if it becomes, regular data is written and a complete redundant configuration can be achieved.

According to the sixth aspect of the invention, the reference potential is switched to the potential of two levels in the reference potential supply bus line 4 every horizontal scanning period, and the amplitude of the data voltage can be reduced.

A seventh invention is such that the difference between the two levels of the reference potential in the sixth invention is set to a relationship of V _br + V _dk , and the maximum amplitude of the data voltage is V _br −V over the positive and negative frames.
It can be _dk .

An eighth aspect of the invention is such that, when a scan voltage V _g is applied to the scan bus line S _{i + 1} , a negative voltage −V of V _g × (C ₂ / C ₁ ) is applied to the scan bus line S _i preceding the scan direction. _The DC voltage level shift can be reduced by applying _cg .

A ninth aspect of the invention, first to the display electrodes 3 of the liquid crystal cell P _{i + 1} which further adjacent to the scanning direction after position with respect to the liquid crystal cell P _i 1
To the scan bus line 1 ₁ it is intended to apply a negative voltage -V _cg.

A tenth aspect of the present invention, in the case of performing display driving by interlaced scanning, applies a scan voltage V _g by alternately selecting an odd-row scan bus line terminal and an even-row scan bus line terminal for each field. The above-mentioned voltage −V _cg is applied to the scan bus line terminals adjacent to both sides of the scan bus line terminal to which the scan voltage V _g is applied.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is an explanatory view of the first embodiment of the present invention, showing an example of a pattern on one substrate of an opposed matrix type active matrix type liquid crystal display device, and the reference potential supply bus lines 14 are all common. And is switched to one of two different levels for each horizontal scanning period. Further, first and second scan bus lines 11 ₁ and 11 ₂ are arranged on both sides of each reference potential supply bus line 14 and are connected to terminals so as to surround the reference potential supply bus line 14.
Further, 12 ₁ and 12 ₂ are first and second thin film transistors, 13 is a display electrode, and a gate insulating film and the like of the thin film transistors are not shown.

The first and second scan bus lines 11 ₁ and 11 ₂ on both sides of the reference potential supply bus line 14 are respectively the first and second thin film transistors.
The gate electrodes of 12 ₁ and 12 ₂ are used, and the reference potential supply bus line 14 is used as the drain electrodes of the first and second thin film transistors 12 ₁ and 12 ₂ . In addition, the display electrode 13 and the thin film transistor 12 ₁ , 1
It is connected to a 2 _second source electrode and may be a source electrode by extending a portion of the display electrode 13.

As a set of the first and second scan bus lines 11 ₁ and 11 ₂ on both sides of the reference potential supply bus line 14, S _i , S _{i + 1} , S _{i + 2} ,.
.. and the liquid crystal cell including the display electrode 13 is P _i , P _{i + 1} , ...
When, and applying a scan voltage to the scan bus line S _i, display electrodes 13 of the liquid crystal cell P _i is a state of being connected to a reference potential supply bus line 14 via the second thin film transistor 12 _2, not shown The data voltage applied to the active data bus line is applied to the liquid crystal cell P _i .

Next, when a scan voltage is applied to the scan bus line S _{i + 1} , the display electrode 13 of the liquid crystal cell P _i is connected to the reference potential supply bus line 14 via the first thin film transistor 12 ₁ ,
The display electrode 13 of the liquid crystal cell P _{i + 1} is the second thin film transistor.
It is connected to the reference potential supply bus line 14 via 12 ₂ , and the data voltage applied to the data bus line (not shown) is applied to the liquid crystal cells P _i and P _{i + 1} until the next selection. The data voltage is held in the liquid crystal cell P _i .

Next, when the scan voltage is applied to the scan bus line S _{i + 2} and the data voltage is applied to the data bus line, the data voltage is applied to and held in the liquid crystal cell P _{i + 1} .

Similarly, the scan bus lines S are sequentially selected, and the data voltage is applied to the data bus lines (not shown), so that the display contents are in accordance with the display data.

As described above, the reference potential supply bus line 14 and the display electrode
Since the first and second scan bus lines 11 ₁ and 11 ₂ are arranged between the reference potential supply bus line 14 and the display electrode 13, the capacitance between the reference potential supply bus line 14 and the display electrode 13 can be reduced. Since this electrostatic capacitance corresponds to the electrostatic capacitance C _dp in FIG. 13, it is possible to reduce the capacitive coupling ratio α2, and thereby reduce the crosstalk, as can be seen from the equation (2). You can

Also, the first and second thin film transistors 12 are provided on both sides of the display electrode 13.
_1, 12 ₂ becomes the redundant configuration provided, even if either one of the non-operating state, if the other is to work, since it is possible to repair the defective display, it is possible to improve the production yield. If it is sufficient to reduce the above-mentioned crosstalk, either _one of the first and second thin film transistors 12 ₁ and 12 ₂ can be omitted.

Figure 3 is a schematic cross-sectional view taken along the line A-A 'of FIG. 2, one on the glass substrate 15 of in the two glass substrates were opposed to each other interposing a liquid crystal, a thin film transistor 12 ₂ shows a portion of forming the display electrode 13 and the reference potential supplying bus line 14 and the scan bus line 11 _2, 16 denotes a semiconductor layer such as amorphous silicon, 17 and 18 contact layer 19 is a gate insulating film, 20 is a metal layer Is.

Some source electrodes of the display electrodes 13 in contact with the contact layer 17, a portion of the metal layer 20 in contact with the contact layer 18 becomes the drain electrode, the scan bus line 11 ₂ on the gate insulating film 19 becomes the gate electrode. In this way, the thin film transistor having the source electrode, the drain electrode, and the gate electrode is formed on the opposite side with the reference potential supply bus line 14 interposed therebetween. Further, stripe-shaped data bus lines facing the display electrodes 13 with the liquid crystal interposed are formed on the other glass substrate (not shown).

As shown in FIG. 4, the transmittance characteristic of the liquid crystal cell is such that the transmittance is the smallest when ± V _dk , that is, the darkest display state is displayed, and the transmittance is the largest when ± V _br , that is, the most transmittance is displayed. The display is bright. Therefore, in the case of black and white display, voltages of V _dk or less and V _br or more in absolute value are selected according to the display data and applied to the liquid crystal cell.

FIG. 5 is a drive waveform explanatory diagram of the first embodiment of the present invention, where (a), (b) and (c) are scan voltages applied to the scan bus line, and (d) is a reference potential supply bus line. Is a reference voltage applied to the data bus line, (e) is a data voltage applied to the data bus line, and (f) is a liquid crystal cell voltage.

On the canvas lines S _i , S _{i + 1} , S _{i + 2} , (a),
(B), and V _g = + 20V to (c), the application of a scan voltage of -V _cg = -20 V, one of the data voltage V between 7V and 9.5V shown in the data bus line (e) _{When D} is applied and the reference voltage V _R, which is switched between the two levels of 12 V and 4.5 V shown in (d) for each horizontal scanning period, is applied to the reference potential supply bus line 14, the liquid crystal cell P _i becomes (V _D −V _R ) = 12−7 = 5
The voltage V _P of (V) is applied, and the liquid crystal cell voltage becomes +5 V as shown in (f).

In this embodiment, the liquid crystal having V _dk = 2.5V and V _br = 5V is used. Therefore, the difference between the two levels of the reference potential is V _dk + V _br = 7.5V. Correspondingly, as shown in (d), 12-4.5 = 7.5 (V) is set.

When the reference voltage V _R is 4.5V, the data voltage V _D is 9.5V
Then, the liquid crystal cell voltage becomes −5V, and a bright display is provided by the liquid crystal cell voltage of the negative polarity. Data voltage at that time
When V _D is 7 V, the liquid crystal cell voltage is −2.5 V, and the display is dark.

The magnitude [Delta] V _LC ^N of variation of the liquid crystal cell voltage V _P, ΔV _LC ^N = ^{_{[ΔV D N × (C gp +}} C dp) ÷ (C gp + C dp + C LC) ] _{+ ΔV R × C dp / (} C gp + C _{dp + C LC) = (ΔV} D N + ΔV R) can be represented as _{× C dp / (C gp +} C dp + C LC) + ΔV D N × C gp / (C dp + C dp + C LC) ... (3). It should be noted that ΔV _D ^N and ΔV _R represent changes in the data voltage and the reference potential.

On the other hand, in the counter matrix type active matrix type liquid crystal display device of the conventional example, the liquid crystal cell voltage variation ΔV _LC ^C is ΔV _LC ^C = [ΔV _D ^C × (C _gp + C _dp ) / ( C _gp + C _dp + C _LC )] = (ΔV _D ^C × C _dp / (C _gp + C _dp + C _LC ) + ΔV _D ^C × C _gp / (C _gp + C _dp + C _LC ) ... (4) Incidentally, [Delta] V _D ^C shows a data voltage fluctuations.

In the present invention, the data voltage V _{D is changed} by alternately switching the reference potential between the above-mentioned two potentials of 12V and 4.5V.
The amplitude of can be compressed. Thereby, the fluctuation of the liquid crystal cell voltage can be reduced. For example, the liquid crystal cell voltage V _{P in} FIG. 5 is ± 5 V, but the amplitude of the data voltage is 9.5−7 = 2.5 (V). Further, the reference potential supply bus line 14 is the first and second scan bus lines.
Since it is sandwiched by 11 ₁ and 11 ₂ , the electrostatic capacitance C _dp becomes smaller than that of the conventional example, and the liquid crystal cell voltage fluctuation ΔV _LC can be reduced.

In addition, the first and second connected to the scan bus line S _{i + 1}
The magnitude of the DC voltage level shift generated in the liquid crystal cell P _i at the end of the gate selection of the thin film transistors 12 ₁ and 12 ₂ is expressed as V _g × C ₂ / (C ₁ + C ₂ + C _dp + C _LC ) (5) You can C ₁ is the capacitance between the display electrode 13 and the second scan bus line 12 _2, and C ₂ is the display electrode 1
It is the capacitance between 3 and the first scan bus line 12 ₁ . Therefore, the DC voltage level shift can be compensated by applying the voltage of −V _cg to the other scan bus line S _i adjacent to the liquid crystal cell P _i . In this case, if −V _cg = −V _g × C ₂ / C ₁ (6), the DC voltage level shift can be almost completely compensated. In FIG. 5, the case where C ₁ = C ₂ is shown, and V _cg = V _g .

FIG. 6 is an explanatory diagram of drive waveforms according to the second embodiment of the present invention, in which (a), (b) and (c) are scan bus lines S _i ,
The scan voltage applied to S _{i + 1} and S _{i + 2} is shown. When a voltage of V _g = + 20 V is applied to the scan bus line S _{i + 1} , −V _cg is applied to the scan bus line S _i that is in front of the scan direction. = −20V, and −V _{cg on} the scan bus line S _{i + 2} that is downstream in the scan direction
= By applying a voltage of -20 V, a defect occurs in the thin film transistor 12 ₁ connected to the scan bus line S _{i + 2,} scan bus line S _{i + 1} connected to a thin film transistor 12 ₂ only by the scan bus lines S Even when the display electrode sandwiched between _{i + 1} and S _{i + 2} is driven, the liquid crystal cell P _{i + 1}
It is possible to reduce the DC voltage level shift of

FIG. 7 is an explanatory view of the third embodiment of the present invention,
The same reference numerals as those in the figure indicate the same portions, and 15 is an extension portion, which is formed by extending between the _second scan bus line 112 and the display electrode 13. As a result, the capacitance C ₁ between the display electrode 13 and the second scan bus line 11 ₂ is increased by the capacitance C ₂ between the display electrode 13 and the first scan bus line 11 _1. , Compensation voltage −V _cg shown in equation (6)
Can be reduced.

FIG. 8 is an explanation of the fourth embodiment of the present invention, and the same symbols as in FIG. 2 indicate the same parts. In this example, the display electrode
The distance between the second scan bus line 11 ₂ and the display electrodes 13 in the scanning direction before position relative 13, smaller than the distance between the first scan bus line 11 ₁ and the display electrodes 13 in the scanning direction after position, It is intended to obtain the relationship of C ₁ > C ₂ .

FIG. 9 is an explanatory view of the fifth embodiment of the present invention.
1 ₁ and 21 ₂ are the first and second scan bus lines, and 22n and 22p are n
Reference numeral 23 is a display electrode, 24 is a reference potential supply bus line, and 25 is a data bus line. The connection configuration of each unit is the same as the configuration shown in FIG. 1, but the first scan bus line 21
A thin film transistor whose gate is connected to _one and n-channel type, showing a case where a thin film transistor whose gate is connected to a ₂ second scan bus line 21 and the p-channel type. Note that a thin film transistor can be provided in the opposite relationship.

For example, as shown on the right side, the data voltage V _D is applied to the data bus line 25, and the reference voltage V _R for switching to one of two different levels for each horizontal scanning period is applied to the reference potential supply bus line 24. , The voltage V _{g on the} scan bus line S _{i + 1
Is} applied, and a voltage −V _cg is applied to the scan bus line S _{i located} in the front in the scan direction, the second scan bus line S _i is output.
N-channel thin film transistor in which the gate is connected to the scan bus line 21 ₂ is turned on and the gate is connected to the _first scan bus line 21 ₁ in the scan bus line S _{i + 1} . twenty two
When n is turned on, the display electrode 23 of the liquid crystal cell P _i is connected to the reference potential bus line 24 via the p-channel type thin film transistor 22p and the n-channel type thin film transistor 22n. Therefore, the data voltage V _D and the reference voltage V _R
Will be applied to the liquid crystal cell P _i .

At that time, the display electrode of the liquid crystal cell P _{i + 1 at} the rear of the scanning direction
The p-channel type thin film transistor 22p connected to 23 is turned off, and the data voltage V _D is not applied to the display electrode 23 of the liquid crystal cell P _{i + 1} . Since the voltage V _g is applied to the scan bus line S _{i + 1} in the next horizontal scanning period, the data voltage applied to the data bus line 25 is applied to the liquid crystal cell P _{i + 1} .

FIG. 10 is a drive waveform explanatory view of the sixth embodiment of the present invention, and shows the case of driving by interlaced scanning in the configuration shown in FIG. 2, for example, (a) to (e) Indicates the voltage applied to the scan canvas lines S _{i-1 to} S _{1 + 3.} For example, in the odd field, when the voltage V _g is applied to the scan bus line S _{i + 1} as shown in (c), When a voltage of −V _cg is applied to the front scan bus line S _i and the rear scan bus line S _{i + 2} adjacent to it, the first scan bus line of the scan bus line S _{i + 1} is applied. 11 first the thin film transistor 12 ₁ whose gate is connected to _one, because the second TFT 12 ₂ and the gate is connected to a ₂ second scan bus lines 11 turned on, the data voltage is two rows of liquid crystal Will be applied to the cell.

Then, in the next scanning period, since the interlaced scanning is performed, the voltage V _g is applied to the scan bus line S _{i + 3} , and the voltage −V _cg is applied to the scan bus line adjacent to the scan bus line S _{i + 3.} A data voltage is applied to the two rows of liquid crystal cells located on both sides of S _{i + 3} .

In the even field, the scan bus line S _i
Voltage V _g is applied to the scan bus line S and the voltage −V _cg is applied to the scan bus line adjacent thereto.
_A data voltage is applied to the two rows of liquid crystal cells located on both sides of _i . Then, in the next scanning period, the voltage V _g applied to the scan bus line S _{i + 2,} the scan bus line adjacent thereto, because applying a voltage -V _cg, both sides of the scan bus line S _{i + 2} A data voltage is applied to the two rows of liquid crystal cells located at. That is, the writing is performed every two lines in the odd field and the even field, and the lines are shifted by one line in each field, and the display by the interlaced scanning is performed.

Also in this case, by selecting the voltage −V _cg , it is possible to reduce the DC voltage level shift and eliminate the problem of afterimage.

The present invention is not limited to the above-described embodiments, but may be implemented by combining the embodiments, for example. It is also possible to have a redundant configuration in which thin film transistors are further added.

〔The invention's effect〕

As described above, the present invention provides a reference potential supplying scan bus lines 1 ₁ on each side of the bus line 4, 1 by ₂ to the provided, capacitance between the display electrode 3 and the reference potential supply bus line 4 Can be reduced, crosstalk can be reduced, and display quality can be improved. The first, first, by providing the second thin film transistor 2 _1, 2 ₂ connected to the second scan bus lines 1 _1, 1 _2, respectively gates, the other is alive even if one of the thin film transistor does not work Then, the display quality is such that no display defect occurs, and the manufacturing yield can be improved.

Further, by alternately switching the potential of the reference potential supply bus line 4 between two levels, the amplitude of the data voltage applied to the data bus line 5 can be reduced, which also reduces crosstalk. .

Further, by applying the compensation voltage −V _cg to the scan bus line, the DC voltage level shift can be reduced, so that the phenomenon such as afterimage can be prevented. Therefore, there is an advantage that the display quality can be improved and the life can be extended.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is an explanatory view of a first embodiment of the present invention, and FIG. 3 is taken along the line AA 'in FIG. FIG. 4 is a schematic sectional view, FIG. 4 is an explanatory view of transmittance characteristics, FIG. 5 is an explanatory view of drive waveforms of the first embodiment of the present invention, and FIG. 6 is an explanatory view of drive waveforms of the second embodiment of the present invention. 7 to 9 are explanatory views of the third to fifth embodiments of the present invention, FIG. 10 is a drive waveform explanatory view of the sixth embodiment of the present invention, and FIG. 11 is an equivalent circuit of a conventional example. FIG. 12 is an exploded perspective view of a counter matrix type panel, and FIG. 13 is an equivalent circuit of a counter matrix type panel. 1 ₁ and 1 ₂ are the first and second scan bus lines, and 2 ₁ and 2 ₂ are the first and second scan bus lines.
The second thin film transistor, 3 is a display electrode, 4 is a reference potential supply bus line, and 5 is a data bus line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Oki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) Reference JP-A-1-167915 (JP, A)

Claims (10)

(57) [Claims] 1. A plurality of scan bus lines (1), thin film transistors (2), display electrodes (3), reference potential supply bus lines (4) are provided on one of two substrates which are opposed to each other with a liquid crystal interposed therebetween. Are formed, the gate of the thin film transistor (2) is the scan bus line (1), one of the source and the drain is the display electrode (3), and the other is the reference potential supply bus line (4). In an active matrix type liquid crystal display device of an opposed matrix type in which a plurality of stripe-shaped data bus lines (5) opposed to the display electrodes (3) are formed on the other of the two substrates respectively connected. , The first and second scan bus lines (1 ₁ , 1 ₂ ) having common terminals on both sides of the reference potential supply bus line (4) extending in a direction orthogonal to the data bus line (5) ) Are arranged in parallel, an active matrix type liquid crystal display device. 2. A first and a first of which a source or a drain is connected to the reference potential supply bus line (4), respectively.
The gates of the second thin film transistors (2 ₁ , 2 ₂ ) are arranged on both sides of the reference potential supply bus line (4).
The second scan bus lines (1 ₁ , 1 ₂ ) are connected to each other, and either the source or the drain is connected to the display electrode (3) arranged adjacent to the data bus line (5) in a parallel direction. The active matrix type liquid crystal display device according to claim 1, characterized in that. 3. The first and second terminals, which are arranged in parallel on both sides of the reference potential supply bus line (4) and have a common terminal.
The second scan bus line (1 ₂ ) located at the rear of the scan bus line (1 ₁ , 1 ₂ ) in the scan direction along the extension direction of the data bus line (5). 3. An active matrix type liquid crystal display device according to claim 1, wherein an extended portion is formed so as to be extended between 3). 4. The first and second terminals arranged in parallel with each other on both sides of the reference potential supply bus line (4) and having a common terminal.
Of the second scan bus line (1 ₂ ) located at the rear of the scan bus lines (1 ₁ , 1 ₂ ) in the scan direction and the display electrode (3) at the front of the scan direction. 2. The active matrix type liquid crystal display device according to claim 1, wherein the distance between the first scan bus line (1 ₁ ) located and the display electrode (3) is narrower. 5. The first thin film transistor (2 ₁ ) is _one of an n-channel type and a p-channel type, and the second
3. The active matrix type liquid crystal display device according to claim 2, wherein the thin film transistor (2 ₂ ) is formed of either an n-channel type or a p-channel type. 6. A structure in which the reference potential applied to the reference potential supply bus line (4) is alternately switched and driven so as to have two levels of potential every horizontal scanning period. Item 1. An active matrix type liquid crystal display device according to item 1. 7. A liquid crystal applied voltage which produces the brightest display
V _br is a characteristic that the difference between the reference potentials that are switched so as to alternately have two levels of potential when the voltage applied to the liquid crystal that _produces the darkest display is V _dk is set to the relation of (V _br + V _dk ). The active matrix liquid crystal display device according to claim 6. 8. The display electrode (3), and each of the second scan bus line (1 ₂ ) on the front side in the scanning direction and the first scan bus line (1 ₁ ) on the rear side of the display electrode (3). Capacitances are C ₁ and C ₂ , a scan voltage V _g is applied to the first scan bus line (1 ₁ ) at the rear of the display electrode (3) in the scan direction, and the scan voltage V _g is at the front of the scan electrode. second scan bus lines (1 _{2) V g × (C 2 / C} 1) an active matrix type according to claim 1, characterized in that a configuration of applying a negative voltage of the same or close to that value as the liquid crystal Display device. 9. The scan voltage V _g is applied to a _first scan bus line (1 ₁ ) which is rearward in the scan direction with respect to the display electrode (3), and the scan voltage is applied to the display electrode (3) in the scan direction. In the second scan bus line (1 ₂ ) at the front and the first scan bus line (1 ₁ ) to the other display electrode (3) adjacent to the rear in the scanning direction, the V _g × (C ₂ 9. The active matrix type liquid crystal display device according to claim 8, wherein a negative voltage having a value equal to or close to / C ₁ ) is applied. 10. An odd-numbered scan bus line terminal and an even-numbered scan bus line terminal are alternately selected for each field by interlaced scanning, and the scan voltage is sequentially selected.
V _g is applied, and the scan bus line terminals adjacent to both sides of the scan bus line terminal to which the scan voltage V _g is applied have a negative value that is the same as or close to the value of V _g × (C ₂ / C ₁ ). 9. The structure for applying a voltage, according to claim 8.
The active matrix liquid crystal display device described.