JPS59104804A - Am demodulator - Google Patents

Abstract

PURPOSE:To obtain an AM demodulator possible for operation by using the clock signal not in synchronizing with an AM signal to be demodulated. CONSTITUTION:An amplitude signal 14 to be demodulated is sampled by a clock frequency N times (where, N>=2) the carrier frequency of the signal. The value obtained by dividing the difference between a sample value Xk-1 before one clock and a sample value Xk+1 after one clock by 2sin (2pi/N) is squared and added this value to the squared value of a present sample value Xk. The square root of said summed value, i.e. the value expressed in the figure is outputted. Where Ak is a modulating signal component at a sample point. Thus, it is possible to use a clock signal not in synchronizing with the demodulation of an AM signal, thereby making the constitution of a clock generating circuit 13 easy and enabling an FM signal to be demodulated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to M-channel amplitude modulation/demodulation devices, and particularly to devices for determining the envelope of an input signal by digital calculation.

Conventional configuration and its problems Conventionally, in order to perform AM demodulation, in the case of analog signals,
Diode detection circuits and synchronous detection circuits have often been used. In recent years, the development of digital integrated circuits.

Therefore, functional circuits that were conventionally constructed from analog circuits are increasingly constructed from digital circuits. In order to realize demodulation using a digital circuit, a block diagram of a 71AM demodulator using synchronous sampling is shown as an example.

The demodulated analog oil signal (4) is converted into a digital signal (5) by the A/D converter (1). A/D converter (
The clock signal (7) to 1) is the clock generator circuit (3)
The clock generation circuit (3) is given by the store signal (4)
The clock signal (7) synchronized in phase and frequency with N times the carrier wave frequency fc is output.

FIG. 2 shows the store signal (4) in a vector diagram. (81(9) (If) indicates the sample point in the case of N-4. Now, assuming that the modulation signal is A (t), the oil signal z (t) is expressed as z (t) = (1 + A (t) 1 t
j2"C" t-・Q), the sampled data is expressed as Zk-(1+Ak)If!, where T is the sampling period. j2πfc+kT −
+2).

If T = (1/4) f c.

Zk=(1+AI)εj1茅...(3) It becomes. Since the real part of this 8th equation is the actual data,
As shown in FIG. 2, when the value of k is an odd number, it becomes zero, and when it is an even number, the sign is reversed but the amplitude is the same. Therefore, if the absolute value of this digital signal (5) is taken by the amplitude detection circuit (2) and then averaged, the modulated signal component (6) can be extracted. The absolute value can be obtained by inverting the data depending on the sign bit or by squaring the data.

However, in such conventional methods, the clock signal (7) needs to be synchronized in phase with the carrier frequency of the original signal (4), and the clock generation circuit (3) uses a phase-locked loop, etc., making it complicated. become.

For example, if the phase shifts, the sample point shifts from the real axis and imaginary axis in FIG. 2, which causes an error in the amplitude detection circuit (1).

Also, if the frequency shifts slightly, the sample phase changes and the sample point rotates on the circumference in Figure 2, so the amplitude detection circuit (
2), and the beat component will be output as a low frequency signal.

Furthermore, in demodulation of an FM (frequency modulation) signal, etc., the input signal frequency constantly changes, so the amplitude cannot be detected using the above method.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a demodulator that can operate with a clock signal that is not synchronized with a one-cycle signal to be demodulated.

Structure of the Invention The M (demodulator) of the present invention samples the demodulated amplitude signal at a clock frequency N (8223 times as high as its carrier frequency), and samples the sample value Xk-1 one clock before and the sample value Xk+1 one clock later. The configuration is configured to output the square root of the sum of the square of the difference between 25in (2π/N) and the square of the current sample value xk. The present invention is characterized in that it becomes possible to use the same clock signal, simplifies the configuration of the clock generation circuit, and also enables demodulation of FM signals.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 8 shows a block diagram of a single demodulator according to the present invention. a
℃ is an A/D converter, a is an amplitude detection circuit, and 1 o'clock is a clock generation circuit. Figure 4 shows a vector representation of the sample points of the demodulated signal 04 input to the A/D converter aV.The eyebrow signal a→ and the clock signal αη of the clock generation circuit Ql are not synchronized. Therefore, the phase of the sample point is not constant, but if the sample phase of the sample point (g) at a certain moment is θ.

2πk z=(1000～)εj(01−T−) −Xk+jYk ・・・(5)l+
Ak Koro 7...(6). N is the ratio of the clock frequency to the carrier frequency of the original signal, and AM
is the modulated signal component at the sample point. Normally, the carrier frequency is sufficiently high compared to the modulation signal frequency, so the modulation signal can be considered almost constant at the sample points (g) and C1l (a). Therefore, since Ak'AI<-1 MisakiAk+1 can be obtained, Zk-1-Zk+s-CI+Asc+Bgj(1
i'+VCk-1)], 2π-(1+Ak-t)C1[θ+1(k+1))"v-j
(1+Ak)gj("Hk)sin L'm -j Z
k sin '' - (7) Therefore, the real part of the 7th equation can be found, and the 4th equation can be found from the 8th and 6th equations, and the modulation signal Ak can be found.In particular, if the clock frequency is set to 4 times the carrier frequency ( If N-4), then the fourth equation is obtained, which simplifies the calculation and the circuit configuration.The amplitude detection circuit 04 performs the calculation according to the fourth equation.

FIG. 5 is an overall configuration diagram showing more specifically the amplitude detection circuit (6) of FIG. 8. 3υ(2) is a 1-clock delay circuit, (c) is a subtraction circuit, (c) is a multiplication circuit, (ii) (e)
is a square circuit, @ is an adder circuit, and (c) is a square root circuit.

Clock signal 0? ) does not need to be synchronized with the frequency of the oil signal C1→, and for the sake of simplicity, the operation will be described assuming that it is approximately four times the carrier frequency. The digital signal aθ converted through the A/D converter 0η is sample point data as shown in FIG. (in the subtraction circuit), the difference between the current data and the data delayed by 2T, which is 2 clocks, is found,
The multiplication circuit (product) multiplies 1/2 S In u-1/2, and the squaring circuit (a) squares the result.

Actually, multiplication by 1/2 may be performed by a 1-bit shift, and the squaring circuit (2) is constituted by a ROM table. This Xk
-1-Xk+1 ()2 is obtained as data 09.

The data (to) delayed by IT of 10,000,1 clocks is squared by the square circuit (e) and becomes Xk! The data is (to).

These two data 0υ) are added by the adder circuit (2), the square root is determined by the square root circuit (), and the demodulated amplitude data is output to the output terminal On. Equation (4) is calculated as described above. Square root circuit (2) is also ROM
It is made up of tables.

As described above, according to the present embodiment, if it is realized by hardware, high-speed calculations comparable to those of video signals, for example, are possible.

Note that this can be realized using one existing component circuit. Furthermore, since amplitude data is obtained in synchronization with the clock signal, it is possible to demodulate up to a high modulation signal frequency.

FIG. 6 is a block diagram of another embodiment. This is almost the same as the previous embodiment, but in order to perform time-division operation with one squaring circuit, a one-clock delay circuit selection switch (
), the OI% frequency dividing circuit (b) has been additionally changed. In other words, in order to use the square circuit in a time-division manner, the clock signal αη is divided into two by the frequency divider circuit (b) and the 1 selection switch (2) is used.
The difference signal and the current signal are switched at , and one squaring circuit (c) is used. Since the square of the difference signal (g) and the square of the current signal (to) are output in order, they are added together in the adder circuit (l-clock delay circuit) with the timing adjusted. Since the output of the adder circuit (b) is correct data every other time, the selection switch (to) is set according to the timing.
By closing , correct amplitude data can be obtained from the square root circuit (c) at the output terminal α. Although the output data is output at a frequency of 172 of the clock frequency, there is no problem at all since the modulation signal frequency is sufficiently lower than the clock signal and carrier frequency. In this way, in the embodiment of FIG. 6, the number of squaring circuits is reduced to one, and easy-to-configure selection switches, frequency dividing circuits, l-clock delay circuits, etc. are used.

Costs can be reduced.

In each of the above embodiments, a hardware configuration is shown, but if the signal frequency is low and there is enough calculation time, the calculation of the fourth equation can also be realized by software.

Further, although the above embodiment has been explained using a signal, it goes without saying that it can also be used to detect the amplitude of a single sine wave signal.

Details of the invention According to the store demodulator of the present invention as described.

AM demodulation is possible by sampling at any clock frequency that satisfies the sampling theorem, and especially in the case of N-4, the calculation is simple, so the device can be simplified. Also,
Amplitude detection of any sine wave signal even if the clock is not synchronized with the input signal.

It is particularly useful as an individual demodulator for FM demodulation.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional store demodulator, and Figure 2 is a block diagram of a conventional store demodulator.
8 is a block diagram of the store demodulator of the present invention, FIG. 4 is a vector representation of the sample points, and FIG. 5 is a specific example of meat. Block Diagram FIG. 6 is a block diagram of another embodiment of FIG. 5. aη...A/D converter, (Foundation)...amplitude detection circuit,
(13...clock generation circuit, a...output terminal,
p]) @-...1 clock delay circuit, Q...subtraction circuit, (c)...multiplication circuit, mm-...square circuit, (Foundation)
...addition circuit, (c)...square root circuit agent Yoshihiro Morimoto Figure 1 Chiku 2 Figure 3 Cause Figure 4

Claims (1)

[Claims] 1. The amplitude modulation signal to be demodulated is set to its carrier frequency N (however,
N22) times the clock frequency, and the difference between the sample value l clocks ago and the sample value one clock later is 25
A store demodulator configured to output the square root of the sum of the square of the value divided by in (2π/N) and the square of the current sample value.