JPS5915536B2 - digital phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the digitization of phase-locked loops, such as phase-locked loops and Costas loops.

With the development of digital technology in recent years, circuits that were conventionally constructed using analog circuits have become digital, and some have even been implemented as LSI.

In recent years, research has been progressing on the digitization of phase-locked loops, which are used to extract carriers from amplitude-modulated waves and demodulate frequency-modulated waves.

FIG. 1 shows the configuration of a digital phase-locked loop.

The human force 10 is the sampled sequence x (n).

The output 19 is a sequence y (n) obtained by sampling a sine wave.

The multiplication circuit 11 serves as a phase comparator, and if the sampling interval is T, then the sequence Z (n) of the output 12 of the multiplication circuit 11 is as follows.

The digital low pass filter 13 reduces the double frequency component of the carrier in the above equation and determines the characteristics of the loop.

This filter is for example It can be something as simple as .

(In this case, a large number of 2ωC components are mixed in 14.) The filter output ω(n) is taken as the filter output ω(n).

A sine wave generator 18, which includes an adder 15, a phase designation memory 16, and a sine wave generator 18, and which constitutes a digital VCO, outputs the amplitude value of a sine wave corresponding to the phase 17 designated by the phase designation memory 16.

For example, assume that a phase of 360° is divided into 32 equal parts.

Phase specification memory specified "15" 5 The output of the mule 18 is f direct of cos (360°X-)2 Try to be strong.

The phase designation v(n) of 17 is as follows.

C specifies the center frequency of vCO, and ω(n-1) is vC
This becomes the control signal for O.

For example, if the control signal is always O, the phase designation is C at every time T.
The center frequency F.

Hato becomes.

When the vCO control voltage ω(n) is positive, the phase advances quickly, which corresponds to increasing the oscillation frequency of the vCO.

The opposite is true when ω(n) is negative. Therefore, in equation (1), if θ>0, the DC component is filtered by low-pass filter 3,...! -8
Since inθ is emphasized, the vCO control amount becomes positive, and the output of vCO is controlled in the phase advance direction.

If θ<0, the opposite is true. A Costas loop is a loop that extracts a carrier component from a DSB waveform.

A block diagram of the Costas loop is shown in FIG.

Human power 20 is converted into DSB waveform A(t) cos (ωct+θ
).

If the output 30 of the VCO 29 is sin (ωct), eA(t) of the output 22A of the phase comparator 21A is vCO
The output 30 passes through a 90L' phase shifter 31 to obtain -cos(ωct)' as the output 32.

eB(t) of the output 22B of the phase comparator 1B is the peripheral number 2ωC of the LPF 23A and 23B, which is twice the carrier.
It cuts the modulation component caused by n-power 24A and 25
Since the output g(t) of the multiplication circuit 25 is A(t)2>0, hA(t) and hB(t) of B are proportional to 5in2θ when passed through the LPF 27 → as the vCO control signal 28. Since 9 values can be obtained, the output of vCO can be compared with human power.

The Costas loop has a 180° ambiguity in its phase.

It goes without saying that this Colletas loop can also be digitized like the phase-locked loop shown in FIG.

'113 or Low Pass Funorta (L
PF) is the phi that determines the overall loop characteristics, /1? Become a new person.

In FIG. 1, human power 10 is assumed to be a series of x (n).

Let output 19 be a sequence of y(n).

The output e1(n) of the multiplication circuit 11 includes the gain G. becomes.

Here, a frequency component twice that of human power is included, but for the purpose of operation analysis, we assume that an ideal LPF for subtracting this is located between the multiplication circuit 11 and the digital low-pass filter 13 in Figure 1. , 130 human power e2(n) converts the impulse response series of filter 13 into f (n
), then the signal 14 v(n) is (the arrow indicates convolutional addition).The constant C determines the center frequency of the loop and does not affect the loop characteristics such as transient characteristics, so it can be set as C-0. When analyzed, θ of the output 17 of the phase designation memory.

(n) Therefore, the equation of the loop is θo (n) - θ1 (nK1). F (Z) determines the system function of the loop.

It is generally preferable for F(Z) to have a simple configuration both in terms of hardware and in terms of operation analysis.

For example, consider the following function (a and b are constants) where both the denominator and numerator are linear as F(Z).

The present invention relates to a configuration in which a filter having the above characteristics is used as a loop filter.

In the above filter, if a = 1, then the complete integral term 1-b/1-Z-' is included, so it is a non-locating PLL in which the phase error in the synchronized state is 0.
become.

On the other hand, when a'< 1, the closer a is to 1, the larger the loop operation time constant becomes, but the residual phase error becomes smaller, so it is generally used in the range of a > 0.9. You can say that.

*For the system function in the non-localized form, critical damping occurs when the denominator becomes a double real root.

Therefore, for example, when b = 0.1 (when a bird is actually made, it will have a value of this order), then b = 0.975.

Therefore, b also has a value close to 1.

To work as a low pass filter, 1 〉a ＞
It becomes b.

Now, the configuration of the above-described low pass filter is changed to the configuration shown in FIG.

Reference numeral 40 denotes a filter, and reference numeral 42 denotes a one-sample delay memory that delays the signal of 41 by one sampling period to obtain signal 43.

44 is a multiplier that multiplies 43 by 8 to make 45, and 46 is a multiplier that multiplies 43 by 5 to make 47.

48 is a control signal for vCO, which is reflected in FIG. 14.

Now, the human input signal is at the free running frequency of vCO (
(determined by a constant C), the control signal must constantly assume positive or negative values.

The value of the signal 48 at this time is a constant value V.

Suppose that Since the transfer function from signal 4'IP(z) to V(z) is (1-bZ~1), the gain of the transfer function in direct current becomes a problem in a steady state, so signal 41 becomes steady. .

For example, if b=0.975 becomes.

Therefore, memory 42 must store 40 times the size of control signal 48.

Therefore, at least 6 bits (the number of bits that can represent 40 times more) than the number of bits required for the control signal is required.

For example, if the sampling frequency is 16 KHz and the control signal changes by 1, the phase of the sine wave generator 18 in FIG. It becomes a change.

Therefore, if the human power changes from the free run frequency determined by the constant C (16KHz x C1512 in this example) to 6
If it were off by 2 Hz, the control signal would have to have a value of "2", and therefore FIG. 3 41 would have a value of "80".

Therefore, if it is desired to synchronize up to a human input that is deviated by ±62 Hz from the center frequency, the memory 42 must be able to store values up to ±80.

In this case, the capacity required for memory from the output is determined,
In normal digital filter design, this is determined by human effort.

On the other hand, filters having the same transfer characteristic F (z) can also have a configuration as shown in FIG. 4.

Human power 50E2 (Z), output 58 V (z) and signal 55Q
(z) Therefore, the signal 58 is the steady value V.

If we take , then the steady value q of the signal 55.

becomes, and in the alocated form (a=1), q.

=VQ. Therefore, the memory 56 only needs to store the same number of bits as the number of bits required for the control signal.

Considering the transient state of synchronization pull-in, a slightly larger number of bits will be required, but this is the same in the configuration shown in Figure 3. For example, in the above-mentioned non-localization (a = 1), b = 0.9
75, the memory capacity in Figure 4 is 6 more than in Figure 3.
It requires fewer bits.

Conversely, if the memory capacity is the same, the hold range limited by the number of memory bits in the case shown in FIG. 3 is only 1/64 of that shown in FIG. 4.

(Theoretically, the hold range is infinite in the positionless form.

) The configuration shown in FIG. 4 is more advantageous not only for the non-localization type but also for the localization type where the value of a is close to 1 for the same reason.

When 1 > a > b, for example, a=0.9375 and b=0.875, and the memory capacity is actually smaller than the number of bits required for the control signal.

When the memory capacity is reduced in this way, the signal 58 becomes the signal 57.
This means that there is an overflow for
In order to correctly calculate the overflow bit, signals 50 and 57 must be MSB expanded.

The circuit configuration in this case is as shown in FIG.

It is assumed that the calculation is performed in two's complement representation.

Assume that the human power is constantly at an amplitude of -1 (binary representation 1.00000).

Assuming that the power comes in series from the LSB, the LSB hold 61 is a circuit that continues the polarity of the MSB ("1" or 10) to the following bit.

Therefore, the signal of 61 becomes 11111.00000.

(The above values are written from MSB (jlIl).

) 63 is the DC gain from the human power 60 to the output 69, so 69 should have a steady value of 11110.00000.

63 is the signal of 62 multiplied by b (=0.875),
That is, it is 11111.00100.

Similarly, 64 becomes 11110.00100.

65 is the difference between the two, which is 11111.00000, and the memory only needs to store the 6 bits on the LSB side.

That is, it is 1.00000.

This is because at this time, all bits of digits larger than the MSB are the same as the MSB.

67 is a circuit that expands the MSB of the signal from the memory 66.

As described above, even if the output 69 overflows the bit capacity of the memory, there is no problem as long as the MSBS-Hall path is provided.

At this time, it is only necessary to reinterpret the position of the sign bit.

For example, in the manual input 60, the sign bit is the first bit above the decimal point, and in the output 69, the sign bit is the fifth bit above the decimal point.

In any case, the output of the loop filter must be a large value (e.g., it must be summed with the constant C in Figure 1, so
In a circuit that does not have an MSB hold as shown in Figure 4, an MSBS-Hall path must be connected to the output 58 to perform MSB expansion, but in a circuit that has an MSBS-Hall path as shown in Figure 5, the new There is no need to add an additional MSBS-Hall path.

Above, I explained the loop filter having the form 1-bZ V 1-aZ', but as mentioned above, after the multiplication circuit in Figure 1, there is a low pass filter to remove the double frequency component manually. - A filter may be inserted, but this has a wider band than the loop filter described above (because it does not have a large effect on the loop characteristics, it is used here as #-7'-7 Iltatoha, 1).
-bZ represents only 71-aZ'.

Furthermore, it goes without saying that the same operation can be achieved even if a repetitive wave generating circuit such as a triangular wave is used in place of the sine wave generating circuit.

[Brief explanation of drawings]

Figure 1 shows an example of the circuit configuration of a general digital phase-locked loop, Figure 2 shows an example of the circuit configuration of a Costas loop, and Figure 3 shows an example of a conventional loop filter for explaining the present invention in detail. A configuration example, FIG. 4 is an embodiment of the present invention, FIG.
The figure shows another embodiment of the invention. 11... Multiplication circuit, 13, 23A, 23B. 27...Low pass filter (LPF),
16... Phase designation memory, 21A, 21B...
... Phase comparator, 25 ... Multiplication circuit, 61
, 67...MSB hold.

Claims (1)

[Claims] 1. A circuit that specifies a certain phase, a circuit that outputs the value of a repetitive wave of the specified phase, a circuit that multiplies this output by external human power, and an output of this multiplication circuit. 1-bZ-' In at least a part of the calculation, 1-aZ'' is a digital phase-locked loop having a loop filter having a low-pass characteristic, and the filter output is It has a loop filter that takes the input of a 1-sample delay memory as the result obtained by subtracting the product of the filter power and b from the product of and a, and adds the output of this memory and the filter power as the filter output. A digital phase-locked loop characterized by: 2. A circuit that specifies a certain phase, a circuit that outputs the value of a repetitive wave of the specified phase, a circuit that multiplies this output by an external input, and a circuit that specifies a certain phase. 1-bZ-'' which controls the phase specifying circuit by calculating the output of the multiplication circuit, and has a loop filter having a low-pass characteristic such as 1-aZ' in at least a part of the calculation; In the synchronized loop, the MSB bit of the filter input and this filter input is expanded to obtain the MSB bit.
Obtain the B decompression filter power, subtract the product of the MSB decompression filter power and b from the filter output multiplied by a, set this as the power of 1 sample full delay memory, and expand the MSB bit of the output of this memory. The above MS
A digital phase-locked loop comprising a loop filter that adds B-expansion filter inputs and produces a filter output.