JPS63119306A - Synchronous detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a stable demodulation signal by constituting a digital PLL circuit of an A/D conveter ADC, a digital arithmetic circuit, a digital loop filter, a D/A converter DAC, and voltage controlled oscillator VCO. CONSTITUTION:The digital PLL consists of an ADC 102, an arithmetic circuit 103, a loop filter 104, a DAC 105, and a VCO 106 to generate signal synchronized with the carrier of a modulated signal. This signal is used as a sampling signal to take to modulated signal into the ACD 102, and operation is performed in the arithmetic circuit 103. The output of the arithmetic circuit 103 is inputted to a loop filter 104 and an LPF 108 different in characteristic, and the signal of phase error from the carrier and the demodulation output are obtained from the loop filter 104 and the LPF 108 respectively. Thus, the demodulation signal is stably obtained with reproduction of the synchronous detection phase error or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a detection circuit, and particularly to a synchronous detection circuit that operates stably.

[Conventional technology]

Envelope detection is often used as a detection method for AM signals, but this envelope detection method has the disadvantage that the carrier is suppressed in overmodulation, causing distortion in the output signal, and that the carrier There is a drawback that an error occurs in the output due to the signal of the component orthogonal to the . A method that does not have the above disadvantages is the synchronous detection method, but as a method that has the same effect as this synchronous detection method, as described in Japanese Patent Laid-Open No. 60-105305, in an AM signal demodulation circuit, a voltage controlled oscillator and phase PLL consisting of a comparison circuit and a low-pass filter
A reference signal that is locked to the carrier frequency by a circuit is generated by frequency-dividing the output of the voltage-controlled oscillator, and a signal having a phase difference of 9 points from the carrier wave of the AM signal is generated from the 1-frequency divided wave of the voltage-controlled oscillator. There is a method in which the AM signal is demodulated by sampling the peak point of the carrier wave of the AM signal using a signal obtained by differentiating this signal as a gate signal of a sample-and-hold circuit using an electronic switch.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology has problems with sampling period errors and bridges caused by the sample-and-hold circuit.

No consideration was given to droop, etc., and there were problems such as synchronous detection phase error and demodulated signal distortion.

An object of the present invention is to stably obtain a demodulated signal by reducing synchronous detection phase errors.

[Means for solving problems]

The above objectives include an analog-to-digital converter (hereinafter referred to as ADC) that converts an input signal from analog to digital, a digital arithmetic circuit, a digital loop filter, a digital-to-analog converter (hereinafter referred to as DAC), and a voltage-controlled oscillator (hereinafter referred to as DAC). Digital PL (abbreviated as vCO)
An AD that stably obtains a sampling signal for synchronous detection using an L circuit and performs analog-to-digital conversion using that sampling signal.
This is achieved by processing the output of C to obtain a demodulated output.

[Effect]

The digital PLL circuit, which consists of an ADC, digital calculation circuit, digital loop filter, DAC, and VCO, can stably generate a signal for synchronous detection, so it is possible to obtain a stable demodulated signal with no synchronous detection phase error. can.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
In the figure, 101 is a modulation signal input terminal, 102 is an A
DC, 103 is an arithmetic circuit, 104 is a digital loop filter, 105 is a DAC, 106 is a vCO 110
LPF with 8-day digital configuration, 109 is DACllo
is the output terminal of the demodulated signal. ADC1021 arithmetic circuit 103. Loop filter 104, DAC 105, v
A digital PLL is configured in C0106 to generate a signal synchronized with the carrier wave of the modulation signal. Using this signal as a sampling signal, the ADC 102 takes in the modulation signal, and the arithmetic circuit 103 performs calculations. The output of the arithmetic circuit 103 is passed through two filters with different characteristics, a loop filter 104 and L
Using the PF 108, a phase error signal with respect to the carrier wave is obtained from the loop filter 104, and a demodulated output is obtained from the LPF 108.

FIG. 2 shows an example of an input signal that can be detected by such an operation.

FIG. 2 shows a vector diagram of the modulated signal. In FIG. 2, v ωct represents an AM signal containing a carrier wave component, ■ is a modulated signal, and ωC is the angular frequency of the carrier wave. P-ωct represents PSK signal and P is digital Hi
It takes a value of 1 in the case of gh, and -1 in the case of digital low. For p=ωC1, the carrier wave is suppressed, va)
! There is an orthogonal relationship with ωct.

Next, the operation of the digital PLL shown in FIG. 1 will be explained. FIG. 3 is an explanatory diagram of the operation of the digital PLL. Figure 3 (
(a) represents a carrier wave signal, and (b) represents a sampling signal of the ADC 102. If the carrier signal is converted from analog to digital at two points θ and θ+π as shown in Figure 3 (α) and the difference between them is taken, the offset of the ADC 102 can be canceled and an output proportional to the phase difference θ can be obtained. be able to. To explain using a formula, the output at a point where the phase difference is θ is
is Va = Vl = V3: V5: Vsinθ
+Δv・・・・・・・・・(1) Phase difference is θ+π
The output Vθ+π at the point is Ve+w=V2=V4=−V−θ+Δ■・・・・・・・・・
(2) However, ΔV is the offset of the ADC 102. Here, in the arithmetic circuit 103, from ■θ0K■
Subtracting θ gives Ep/p=Vθ+*-Va=(-Vai
nθ-)-ΔV)-(Vsino+ΔV)=-2Vt
nθ ・・・・・・・・・・・・(31EP/
D indicates the phase detection output. FIG. 4 illustrates the phase detection characteristics of equation (3). Pass the EP/D through a loop filter 104 and convert it into an analog signal using a DAC 105 1.
:ttwoV C010617) fltlJ input toshi,
V C010617) Clock signal A D C102
be the sampling signal of With this configuration, the output of the VCO 106 is synchronized at a frequency twice the carrier frequency.

Based on the phase detection characteristics shown in FIG. 4, the phase difference θ is controlled to be O. At this time, EP/D becomes 0 from equation (3).

Next, FIG. 1 will be explained using FIG. 5. Figure 5 is the first
It is an explanatory diagram of the operation of the figure. (α) is the modulation signal, <b> is V
This is the output of CO106. The area I shown in Figure 5) is only the video signal of vamωct in Figure 2.

Figure 5 (timing of bl, value obtained by converting the modulation signal from analog to digital in 1.2.3.4 El = E2 +
When E3yE4 is calculated by the arithmetic circuit 103 as shown in equation (3), the phase detection output EP/D, I is as follows: EP/D, + = Eta E+□=0
・・・・・・・・・・・・・・・(4) However, when the PCM signal is orthogonally multiplexed, the input signal becomes as shown in the black 2 vector diagram, and when expressed by the formula, the modulation signal vIN is ■! N=vOωct+Pmωct...
・・・・・・・・・・・・・・・(5).

Here, the region (■) shows the modulated signal when P=1, and the region (2) shows the modulated signal when P=-1.

In the region of ■, the phase detection output EP/D, I is (3)
From equation (5), EP/D, I ” El13 EI2=p-(-p
) = 2P ・・・・・・・・・・・・
・・・・・・・・・(6) In the region of ■, the phase detection output E
From formulas (3) and (5), P/D and ri are EP/D, ■: E13-E2=-P-P=-2P...
......(7). As shown in equations (6) and (7), the polarity of the PCM signal appears in the output of the arithmetic circuit 103. Pass this through L P F 108 and D A
When input to C109, a PCM output is obtained from output terminal 110. On the other hand, the output of the arithmetic circuit 103 also outputs the phase detection output of the digital PLL, the demodulated PSK signal is removed by the loop filter 104, and only the phase detection output is converted to an analog signal using the DAC 105, which is then controlled by the vC01060. Signal.

As explained above, according to the present embodiment shown in FIG. 1, one ADC and one arithmetic circuit have two roles of a phase detector and a synchronous detector, and filters with different characteristics are connected to the subsequent stage. By separating the phase detection output and the synchronous detection output, there is an effect that the detection output can be stably obtained.
"FIG. 6 is a block diagram showing a second embodiment of the present invention, and the same reference numerals as in FIG. is an inverting circuit.ADC102゜operation circuit 103.Loop filter 104, DAC105
゜VCO 106 and +frequency divider 107 constitute a digital PLL circuit. The operation is the same as that explained using FIG.
6 is synchronized at a frequency four times that of the carrier wave, and the output of the branching unit 107 becomes as shown in FIG. 3(b).

The synchronous detection circuit shown in FIG. 6 can detect, for example, an AM signal.

The operation shown in FIG. 6 will be explained below using FIG. 7. FIG. 7 is an explanatory diagram of the operation of FIG. 6, where (α) is an AM signal, (h)
(C) is the output of the inverting circuit 603; (d) is) the output of the divider 602.

) The output of the branching unit 107 is synchronized with the timing shown in FIG. 7(b). The output of the inverting circuit 603 has a duty ratio of 50% because the VCO 106 output is sufficiently divided by the frequency divider 107, and becomes a signal that rises at the peak value of the modulated wave. Therefore, the signal obtained by dividing the output of the inverting circuit 603 is the seventh
The result is as shown in Figure (d), and the ADC601 is as shown in Figure 7 (d).
Data is taken in at timing 3 (point number 1 (43+2) in Figure 7 (α): n is an integer). The captured data is simultaneously converted from analog to digital to become a digital value, and the digital value remains as L P F 108
removes unnecessary bands and converts digital data using DAC109.
Analog conversion is performed and the demodulated signal of the AM signal is output to the output terminal 110.
Get more. According to the embodiment shown in FIG. 2, it is possible to stably demodulate an AM signal.

FIG. 8 shows a third embodiment of the present invention, and this figure also shows a synchronous detection circuit for a modulated signal, for example, an M signal, similar to that in FIG. Components with the same reference numerals indicate the same functions, and 801 is an arithmetic circuit. The operation in FIG. 8 is almost the same as that in FIG.
2, the output of the inversion circuit 603 samples the ADC 601 at the timing shown in FIG. 7<c). Here, in Figure 7 (α), the positive side point (mu point 9 number 4
The points on the negative side (points 1 and 4n are integers) differ in phase by 1800, but contain similar demodulated signals. Therefore, by performing the following calculation in the calculation circuit 801, a demodulated signal can be obtained. That is, EDEM= E43+2-E43 ---・
...--(8 digits EDEM is the output of the arithmetic circuit 801, and E4n+2 *E4U are respectively shown in Fig. 7 (α)
This is the sample value of the point indicated by the number in . The output EDEM of the arithmetic circuit 801 is passed through the LPF 108 to remove unnecessary bands, and is digital-to-analog converted by the DAC 109 to obtain a demodulated signal of the AM signal from the output terminal 110. The demodulated signal obtained by the synchronous detection circuit of FIG. 8 has an amplitude approximately twice that of the demodulated signal obtained by the synchronous detection circuit of FIG. 6. In other words, the synchronous detection circuit of FIG. 8 has better detection sensitivity than the synchronous detection circuit of FIG. 6. According to this embodiment, it is possible to perform synchronous detection with superior detection sensitivity compared to the synchronous detection circuit shown in FIG.

FIG. 9 shows a fourth embodiment of the present invention, which is a circuit that detects a PSK signal from the modulated signal shown in FIG. 2 and demodulates a digital signal P, for example. Components with the same symbols as in FIGS. 1 and 6 represent the same functions. In Figure 9,
901 is an analog multiplier; 902 is an analog loop filter; and 903 is an adder. The synchronous detection circuit in Figure 9 is an analog PLL circuit as well as the digital PLL circuit in Figure 1.
It also has an L circuit. This will be explained using FIG. 5.

FIG. 5 (α) is the modulation signal, and (h) is the output of the sufficient frequency divider 107.

(C) is the output of the inversion circuit 603, (d) is the sufficient frequency divider 60
This is the output of 2. The digital PLL operates in the same way as shown in Fig. 1 (however, V C0106 is locked at a frequency four times that of the carrier, and the one corresponding to the output of VCO 106 in Fig. 1 is shown in Fig. 9). output), a phase detection output is obtained from the DAC 105. On the other hand, multiplier 901. Loop filter 902°VC010
6, + frequency divider 1079 inversion circuit 6oa, -) frequency divider 60
An analog PLL is configured with two loops, and the output of the sufficient frequency generator 602 (Fig. 5(d)) and the modulation signal (Fig. 5(d))
α)) is multiplied using a multiplier 901 and the multiplication output is passed through a loop filter 902 to obtain a phase detection output. At this time, the output of the sufficient frequency generator 602 and the modulation signal are synchronized with each other with a 90° shift (see FIG. 5). More than DA
The phase detection output of C105 and the phase detection output of loop filter 9020 are added using adder 903, and the added output is used as the VCO 1060 control signal. The synchronous detection circuit with the configuration shown in FIG.
The LL performs frequency synchronization, and then the digital PLL operates to synchronize the phase. According to this embodiment, there is an effect that stable PLL pull-in can be performed.

FIG. 10 shows a fifth embodiment of the present invention,
This figure also shows a circuit that detects a PSK signal from the modulated signal shown in FIG. 2 and demodulates a digital signal P, for example. The same numbers as in Fig. 9 represent the same functions, 1001, 10
02 is an attenuator, and 1003 is an attenuator control circuit. In FIG. 10, a circuit for controlling the output levels of the phase detection output of the loop filter 902 and the phase detection output of the DAC 105 in FIG. 9 is added. Attenuators 1001 and 1002 respectively control the input and output gains of the attenuators and open/close between the input and output.

The control circuit 1003 uses an attenuator 1001 so that the synchronous detection circuit shown in FIG. 10 quickly synchronizes the PLL.

1002. For example, when the power is turned on or when it is detected that the PLL is out of synchronization,
When it is detected that the frequency deviates from the carrier wave, the attenuator 1002 is opened and the gain of the attenuator 1001 is increased so that only the analog PLL is applied. Attenuator 1001 after analog PLL synchronizes
The gain is lowered, then the attenuator 1002 is closed and the gain is increased, and finally, synchronization is performed using only the digital PLL. This embodiment has the advantage that the PLL synchronizes quickly and the synchronous detection circuit can operate stably. Note that the insertion positions of the attenuators 1001 and 1002 do not have to be the positions shown in FIG. 10 (but can be anywhere as long as the analog/digital phase detection output can be varied). It shows [
, for example, represents a synchronous detection circuit for an AM signal, and the same reference numerals as in FIGS. 6 and 10 represent the same functions. FIG. 11 shows an analog PLL circuit added to the synchronous detection circuit of FIG. 6. To explain using Figure 7, Figure 7 (
at is the modulation signal, (b) is the output of the frequency dividing circuit 107, (C
) is the output of the inverting circuit 603, and (d) is the output of the branching unit 602. ) Multiplier 901 multiplier 602 output and modulation signal
The multiplier output is multiplied using the loop filter 904
to obtain the phase detection output of the analog PLL. Other operations are similar to those in FIG. 10. According to this embodiment, it is possible to synchronize the PLL and stably synchronously detect the AM signal.

FIG. 12 shows a seventh embodiment of the present invention - for example, a circuit that detects a PSK signal from the modulated signal shown in FIG. 2 and demodulates a digital signal P. This figure is the first
This is a simplified version of the synchronous detection circuit in Figure 0, where the same symbols as in Figure 10 represent the same functions, and 1201 is an analog L
It is PF. The difference from FIG. 10 is that the PSK signal is input from the multiplier 901, which is the phase comparator of the analog PLL circuit.
, the circuit configuration is such that the information is extracted through the PF 1201. According to this embodiment, there is an effect that the modulated signal can be synchronously detected with a simple configuration.

FIG. 13 shows a fourth embodiment of the present invention, and represents, for example, a synchronous detection circuit for AM signals. This figure is a simplified version of the synchronous detection circuit shown in Fig. 11.
Items with the same symbols as in Figures and Figure 12 represent the same functions, and 1
301 is an analog multiplier, and 1302 is a + frequency divider. The difference from Fig. 11 is that ADC60 is used in the synchronous detector.
1 in that a multiplier 1301 is used, and this embodiment has the advantage of being able to obtain a demodulated output with a simple configuration.

FIG. 14 shows a ninth embodiment of the present invention, which is a circuit that detects a PSK signal from the modulated signal shown in FIG. 2 and demodulates a digital signal P, for example. Those with the same symbols as in FIG. 1 represent the same functions, and 1401 is the ADC, 1
402 is an arithmetic circuit. FIG. 14 shows the synchronous detection circuit of FIG. 1 in which the digital PLL system and the synchronous detection system are completely separated. ADC 102, arithmetic circuit 104
, DAC 105 and VCO 106 constitute a digital PLL system, ADC 1401, arithmetic circuit 1402 .
LPF 1o8 and DAC 109 constitute a synchronous detection system. In this example, ADC1401, ADC1
02 can have optimal sensitivity and accuracy, which has the effect of further simplifying the design.

Note that in the above drawings, when the modulated signal is digital, it is also possible to skip the DAC 109 and send it directly to the digital signal processing circuit. Also, DAC109 is L P F
It is also possible to place the L P F 108 in front of the L P F 108 in an analog configuration. Furthermore, D A C105°V
DA is a digital vCO that combines the functions of CO106.
It may be used instead of C105 and VCO106~ゝO [Effects of the Invention] According to the present invention, it is possible to obtain a signal synchronized with the carrier wave of a modulated signal using a digital PLL, and use that signal to input Since a modulated signal can be converted into a digital signal by an ADC and processed digitally to stably obtain a demodulated signal, there is an effect that stable detection can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of an embodiment of a modulated signal for implementing the present invention,
Fig. 3 is an explanatory diagram of Fig. 1, Fig. 4 is an explanatory diagram of Fig. 1, Fig. 5 is an explanatory diagram of Figs. 1 and 9, and Fig. 6 is an explanatory diagram of the second embodiment of the present invention. 7 is an explanatory diagram of FIGS. 6, 8, and 11, FIG. 8 is a block diagram showing the third embodiment of the present invention, and FIG. 9 is a block diagram showing the fourth embodiment of the present invention. FIG. 10 is a block diagram showing a fifth embodiment of the present invention, FIG. 11 is a block diagram showing a sixth embodiment of the present invention, and FIG. 12 is a block diagram showing a seventh embodiment of the present invention. FIG. 13 is a block diagram showing a ninth embodiment of the present invention, and FIG. 14 is a block diagram showing a ninth embodiment of the present invention. 102...ADC, 103... Arithmetic circuit, 104...
...Loop filter, 105...D AC, 106...VCO. 108...LPF, 109...DAC
. 601...ADCl 602...) Frequency divider, 6
03... Inverting circuit, 801... Arithmetic circuit, 90
1... Multiplier, 902... Loop filter, 903
...Adder, 1001, 1002...Attenuator, 1003...Control circuit, 1201...
・LPF, 1301... Multiplier, 1302...
・Civil branch unit. 1st μ zo ko 2 ha th j (! 1 man 4 ko 5 bacteria trillion 70

Claims (1)

[Scope of Claims] 1. A synchronous detection circuit characterized by being provided with an analog-to-digital conversion circuit for converting an input signal from analog to digital, a digital signal processing circuit, a digital-to-analog conversion circuit, and a voltage-controlled oscillator. 2. In claim 1, the sampling frequency of the analog-to-digital conversion circuit is twice the frequency of the carrier wave of the input signal, and one data of two consecutive data output from the analog-to-digital conversion circuit is set. A synchronous detection circuit characterized in that the digital signal processing circuit has an operation of subtracting other data from the synchronous detection circuit. 3. The synchronous detection according to claim 1 or 2, characterized in that a second analog-to-digital conversion circuit for converting the input signal from analog to digital is provided separately from the analog-to-digital conversion circuit. circuit. 4. A synchronous detection circuit according to claim 3, characterized in that a second digital signal processing circuit is provided at a subsequent stage of the second analog-to-digital conversion circuit. 5. The synchronous detection circuit according to claim 1 or 2 or 3 or 4, further comprising: an analog multiplier for multiplying the input signal by a reference signal obtained from the output of the voltage controlled oscillator; . A synchronous detection circuit comprising: an adder for adding two phase error signals obtained from the analog multiplier and the analog-to-digital conversion circuit. 6. In claim 5, there is provided a variable gain circuit that varies the gain for each of the phase error signals that are two inputs of the adder, and a control circuit that controls the variable gain circuit. A synchronous detection circuit characterized by: