JPS5897846A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To allow the prevention of reduction of pattern forming region and generation of crystal strain, the improvement of the integration degree and the reduction of the deterioration of withstand voltage, by forming a polycrystalline Si layer only on the side surface of a groove after forming an etching groove, when a buried Si oxide film is formed. CONSTITUTION:B as a P type impurity is added by an ion implantation method. Thereafter, using a thermal oxidation method, a buried Si oxide film 8' is formed. When the thermal oxidation is performed at 900-1,000 deg.C by high pressure oxidation for example, an oxide film can be easily formed. The lower surface of the groove is oxidized when selective oxidation, but the Si substrate itself is not oxidized. Therefore, an Si oxide film is not formed under an Si nitride film 5. A bird head is not formed, the reduction of pattern forming region due to a selective oxidation and the generation of crystal strain can be prevented, high density formation and miniaturization can be performed, the unstability of characteristic due to strains is prevented, and, at the same time as the formation of the buried Si oxide film 8', a channel stopper 15 and the P type region 7'' a region to prevent the deterioration of withstand voltage can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a buried silicon oxide layer for device isolation and a region thereon.

In the manufacturing method of semiconductor devices such as integrated circuits, in order to improve the degree of integration and simplify the manufacturing process, dielectric isolation using a buried oxide film, and furthermore, element formation using self-alignment technology using the buried oxide film has been developed. The most common method for forming this buried oxide film is thermal oxidation using silicone film as the oxidation-resistant film, which is the easiest method to use. Mainly used.

At the same time as this selective oxidation, formation of the channel edge region and the breakdown voltage deterioration prevention region is carried out.

Figure 1 (a)-(C) $? and FIG.
gllg(a) to (e) show examples in which a diffusion method is used to introduce impurities into a channel stopper and a breakdown voltage deterioration prevention region. First, as shown in FIG. Then, the silicon nitride film 5 and silicon oxide 11 [4] on the silicon element region are removed by selective etching using a photo process method, and the exposed silicon substrate surface is etched to form #lI6. (Refer to Figure 1g1 (b)) Then, the boron is diffused by thermal diffusion method and p
11v region 7 is formed. (See FIG. 1C) Next, a buried silicon oxide layer 48 is formed using a thermal oxidation method to fill the trench 6. Through this thermal oxidation), the previously introduced impurities form a channel stopper 9 and a breakdown voltage deterioration prevention region τ under the buried oxide film 8 (see Figure 1 (dJ)). After channel stoppers and the like are formed, desired elements are formed in isolated island regions.

Figure 1(e) is a sectional view of the main part after the element is formed, and 11 is an emitter.
1 ivy region, a space region connected to the 10Fi breakdown voltage deterioration prevention region τ, and 3 Fin type silicon layer, which becomes the collector region of the transistor.

However, when forming a buried silicon oxide film, a channel stopper, and a breakdown voltage deterioration prevention region using this manufacturing method, when a thick oxide film is formed, oxygen will diffuse through the oxide film and under the silicon nitride film. As a result, lateral oxidation occurs, and the silicon substrate under the silicon nitride film is also slightly oxidized, resulting in a so-called bird's head.
) is formed.

This results in a decrease in pattern width. For example, the silicon etch depth is approximately 0.6 μm, and the buried silicon oxide g!
If the film thickness is about 1.2 .mu.m, the pattern width will be reduced by about 2 #m, and such a large reduction in pattern width will result in a large interstitial hearing in improving the sensitivity of the pattern. Furthermore, due to the partial formation of a silicon oxide film under the oxidizing film, a large strain is applied to the silicon substrate.
This is a major drawback in device formation, such as the occurrence of crystal defects. Further, the p-type impurity introduced before forming the thick oxide film forms a channel stopper, but since it is formed in contact with the channel stopper Fi paste layer, there is a drawback that the Cca capacitance increases. Further, although the impurity introduced into the side surface of the groove forms a region for preventing breakdown voltage deterioration, it also has the disadvantage that the CCB surface becomes large because it is connected to the pace region 10 as shown in FIG. 1 (el 1).

In addition, FIGS. 2(1) to (el are cross-sectional views showing each step of the manufacturing method of a buried oxide film-separated semiconductor device equipped with a tunnel stopper by a conventional method. The numbers shown in the figures correspond to those in FIG. 1. In Figure 2 (al to (e)), the impurity for the channel stopper is implanted by ion implantation.In the figure, first, as in the case of Figure 1, n-type impurity is added to the surface of the p-type stack. Form an n-type buried layer on top of the n-type buried layer.
A semiconductor layer 3 is formed, and a silicon oxide film 4 and a silicon nitride film 5 are formed on its surface. (See Figure 2 (a))
However, in Figure 1 (Jl) to IC))'! ! ! ! The semiconductor substrate and buried layer have been omitted from the drawing for convenience.

Next, the silicon nitride film 5 and silicon oxide film 4 on the element isolation region are removed by selective etching using a photo process method, and the exposed silicon substrate surface is etched to form grooves 6.
form. (Refer to Figure 2 (b)) Then, the ciborons are diffused by ion implantation.
: Ru. When ion implantation is performed, impurities are not diffused on the side surfaces of the Fi, and a p-type impurity layer 7 is formed only on the bottom surface. : (See t/g2 diagram (C)) Next, the buried silicon oxide film 8 is removed using a thermal oxidation method.
□ Form and fill tll16. During this thermal oxidation, the impurity introduced into the bottom of #I: diffuses to form a channel stopper 9 under the buried oxidation a8:. At this time, since no impurities were introduced into the side surfaces of the trench, no breakdown voltage deterioration prevention region was formed. (
Figure 2 (dl#fi)
'After that, desired elements are formed in the isolated island-like regions (see FIG. 2 (el)) In the semiconductor device having the buried oxide isolation regions formed in this way, the bird's When a head is formed, the - of the pattern forming area is significantly reduced.At the same time, a large strain occurs in the silicon crystal near the silicon oxide film, which causes defects in the characteristics of the device.

In addition, the channel stopper tends to bury the buried region Kt, which results in a large Ccs valley.In addition, in this dormitory example, a cine composite was introduced by ion implantation, so no region for preventing voltage deterioration was formed. The area between the electric ivy is prone to leaks.

Therefore, the present invention has been made to address the above-mentioned problems, and is intended to suppress lateral oxidation, increase the effective area for forming elements, and eliminate insects at the oxide film-silicon interface in a semiconductor device with element isolation using a buried oxide film. A semiconductor that aims to stabilize the C characteristics as much as possible, and at the same time forms a channel stopper with a small CS capacitance and a breakdown voltage deterioration prevention region that does not increase the CH response and does not cause CE leakage. In other words, the gist of the present invention is to provide a method for manufacturing a device. a step of forming a polycrystalline silicon group only on the side surfaces of the glare groove, a step of adding impurities of the type opposite to the substrate surface region by ion implantation, and a step of forming a buried silicon oxide film by a thermal oxidation method. A method of manufacturing a semiconductor device, comprising the steps of forming a substrate surface region and a conductivity type region opposite to the substrate surface region adjacent to the buried oxide film.

The present invention will now be described in detail with reference to the drawings. Figures 3 (al to U) are cross-sectional views showing each step of a method for manufacturing a bovine gullet body device according to an embodiment of the present invention. The steps will be explained in order.

(1) Diffusing and embedding n-type impurities into p-type semiconductor wood board 1 ~ 2
A semiconductor substrate is prepared by forming an n-type silicon region 3 thereon by vapor phase growth. (See Figure 3(f)) NLM1 Although omitted in the figure, next, a silicon plated film 4 of about 20 OA is formed on the surface of the n-type silicon region 30 formed earlier by thermal oxidation, and the silicon The mouse film 5 is exposed to approximately 100 OA by CVD method (M 31fl
(Refer to aJ) (2) Next, using a photoresist method, the silicon inguinoid gland 5 and silicon oxide 1 [41] on the buried swallow film formation area are selectively etched away, and the silicon substrate surface t-m is exposed. , and then Keide table time t-CCl.

The groove 6 is etched by plasma etching using a gas system, and the groove 6 is etched to 0.
Formed to a depth of 6 μm. (See Figure 3(b)) +s> lJh Then polycrystalline silicon M! I4I 2
The thickness of the polycrystalline silicon film (see figure a, s<C), which is formed at a thickness of 95,000 to 6,000 A by the t-vapor phase growth method, varies depending on the desired thickness of the buried silicon oxide film. If the thickness of the oxide film is approximately 1.2 μm, the silicon film to be deposited is film I! I. A suitable thickness is about 0.5 μm.Next, the polycrystalline silicon film 12 is etched. At this time, the etching is carried out by an anisotropic plasma etching method using CCI gas, and the entire surface of the substrate is exposed to the etching gas. In such a case, since etching is performed only from a direction perpendicular to the substrate surface, the polycrystalline silicon on the sides of the etching groove remains unetched. (See FIG. 3 (di)) After the plasma etching, the silicon substrate may be chemically etched to prepare the surface.

(6) Next, boron is added as a p-type impurity by ion implantation. When appropriate, boron is implanted into the top surface of the sidewalls of the polysilicon and into the bottom surface of the trench from which the polysilicon has been removed to form p-type regions 13 and 14. (Figure 3(e)
(Refer to l) (6) Buried silicon oxidation M using thermal oxidation method
Form l 8/. Thermal oxidation, for example, by high pressure oxidation9
An oxide film can be easily formed if carried out at 00 to 1000"C. During this selective oxidation, the bottom surface of the $6 is conventionally oxidized, but on the @ surface, the polycrystalline silicon film 12 is oxidized and the silicon substrate itself is oxidized. Not oxidized.Therefore, silicon chamber conversion tile 5
A silicon oxide film is not formed under the 0, and therefore no 1's head is formed, making it possible to prevent a reduction in the pattern formation area and generation of crystal distortion due to selective oxidation. Therefore, higher density. It is possible to reduce the size and prevent instability of characteristics due to distortion. Moreover, the channel stopper 15 and the pmlml region of the breakdown voltage deterioration prevention region can be formed simultaneously with the formation of the buried silicon oxide film 8'. Since the channel stopper 15 is formed small and apart from the Fi buried layer 2, the Ccs capacitance can be reduced. (See Figure 3) (7) Next, a desired element is formed in the island-shaped region formed by the buried oxide layer, and a semiconductor device is obtained (See Figure 3 (, ?+)). ) In FIG. 3U), 11 is an emitter region, 12 is a base region, 3 is a collector region, and 7'' is a p-type region for preventing voltage deterioration.The p-type region for preventing voltage deterioration is shown in FIG.
As shown in FIG. 2, since it is not large, the CCB capacity '1k can be made small. Furthermore, since the p-type region for preventing one-pressure deterioration is formed in the part where CEII leakage is most likely to occur, this leakage can be reduced.

As explained above, according to the present invention, when a buried silicon oxide film is formed by the i″t′ selection method, a polycrystalline silicon layer is formed only on the sides of the silicon etching groove hX and the groove is heated. It is possible to prevent lateral oxidation during oxidation, thereby preventing the reduction of the pattern formation area and the occurrence of crystal strain.Therefore, it is possible to improve the concentration f*U and reduce breakdown voltage deterioration due to the occurrence of strain. be able to.

At the same time, since the channel stopper and the breakdown voltage deterioration prevention region can be formed small, they can function without increasing the CCS capacitance and CCB capacity. Therefore, it is possible to achieve high density, stable 9% reduction in size, and improve yield.

[Brief explanation of the drawing]

Figures 1 (Jll to tel) and Figures 2 (a) to (eJ) are cross-sections of main parts by process showing a conventional semiconductor device manufacturing method.
FIG. 1 and FIGS. 3(a) to 3(a) are cross-sectional views of the narrow portion of each step showing a method for manufacturing a hand-only device according to an embodiment of the present invention. 1... Semiconductor base plate, 2... Buried layer, 3...
... Semiconductor substrate surface region, 4 ... Silicon oxide film, 5 ... Mark silicon crab film, 6 ... Tile, 7 ... Formed in tpI part p-type region, 7/
, 7 // shout, , pressure deterioration prevention area, 8. 8'...Embedded silicon oxidation film, 9... Group channel stopper, 10...Base M area, ll
...Group/emitter region, 12...Polysilicon, 13...Polysilicon impurity introduction region, 14
...Harmful bottom impurity introduction region, 15...
・Channel stopper. 74 Figure 3 Figure 3

Claims (1)

[Claims] A step of forming a Kjt oxidation exchange pattern on the surface of the semiconductor substrate, a step of etching the base and surface other than the mosquito pattern to form a groove, a step of forming a polycrystalline silicon film only on the @ side of the substrate, and a step of etching the base and surface other than the mosquito pattern to form a groove. A step of adding an impurity of a conductivity type opposite to that of the substrate surface region by an implantation method, and a step of forming a buried silicon oxide film by a thermal oxidation method, and adding an impurity of a conductivity type opposite to the substrate surface region adjacent to the buried oxide film. A method of manufacturing a semiconductor device, the method comprising: forming a semiconductor device.