JPS5894038A - Storing device of register group - Google Patents

Abstract

PURPOSE:To perform a recovery process at a high speed, by providing the 2nd register stack and have a quick transfer of the contents of a register group to the 1st register stack with each switch of process. CONSTITUTION:The 2nd register stack 62 can store plural register groups of a process which executed previously an instruction, a process which is under execution and a process to be executed next, respectively. In the normal execution mode of instruction, the arithmetic result is written concurrently to the 2nd register stack 62 when a read/write instruction given from the 1st register stack 61 is executed. When a process is switched, the contents of the register group of the next process of the register stack 62 are transferred to the register stack 61 to execute an instruction. At the same time, the contents of the register group corresponding to the next process are written to another area of the stack 62 from the shunt area of a main storage device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION In this invention, a group of registers used for calculations in the central processing iM device of the Needle J1 machine system is defined one set for each process, which is a processing unit of a program, and each register is used as a main memory. A register save area VC save area is provided corresponding to each process in the register, and among multiple processes in an executable state, l@O This invention relates to a register group storage device in an IJ1 machine system that executes a process, and particularly relates to IFIJ# for register I# at the time of process switching.

Conventionally, this building's system #i theory has been configured as shown in Figure 1. That is, the main memory device l stores instructions, operands, and save data for each content of a plurality of register groups. The contents of the above set of registers correspond to one process. Central processing girl 112U
, instruction fetch device 3. It is composed of an instruction execution device 1114, a register group storage device 5, and the like. The register group storage device 5 includes a register stack 51 that stores 91 register groups corresponding to a running process, and an address register 52 that supplies addresses for starting and enriching the register stack 51. It is configured. The register stack 51 normally includes 16 base registers (HRQ to
15) and 16 general-purpose registers ((jkLθ to (jRts)) that hold the main memory addresses and data used in calculations.

The instruction fetch device it3/fi instruction is sent to the main memory device 1.
Fetches and decodes the memory operands and prepares the register operands. A single memory operand means that the contents of the base register and general-purpose register specified by the instruction are retrieved from the register stack 51 via the address register 52, and the contents of the base register and general-purpose register specified by the instruction are retrieved from the register stack 51, and the contents of the three contents and the contents of the displacement field in the instruction are extracted. The main memory address is obtained from K by calculating the data of tik! The goal is to generate access to electricity. Preparation of the register operand means that the contents of the general-purpose register specified by the instruction are read out from the register stack 51 via the address register 52t, and this successive data is received by the Ayu-ryo compensation device 4. be.

The result of the calculation in the area 4 is sent to the instruction fetch device t3.
is stored in the address position of the register stack 51 given via the address register 52.

In the instruction fetch device [3, the process is switched or required due to interrupts from other processors such as turnout + bll # device, or interrupts due to exception detection during execution of instructions, or instruction dissolution d, etc. In this case, first, the contents of the register stack 51, which is a group of registers corresponding to the currently running process (7), are saved to an area in the main memory l that has been designated for the process, and then The contents of the register group corresponding to the new process to be executed are transferred from the I&IL save area in the main device U1 to the register stack 5.
5t- (i.e., recovery) to 1 is a must. The operation of saving and restoring this register group will be explained with reference to the time chart shown in FIG. First, register stack 5xo16 (10 pace regis/(880~BR
I 5) and 16 general-purpose registers (ql 0 to *aI
S>, the contents of the registers totaling 3211I are written and saved in the storage device l. Next, 32 registers (BRO to B
15. GR0 to GR15) are sequentially read and recovered from the save area of the main memory corresponding to the new process. That is, for save processing and recovery processing, there are 32 writes to the main memory and 32 reads of 1.gl from the main memory. #Creation is necessary. That is, using the conventional register group storage device 5 as shown in FIG.
) system has the disadvantage that it takes a lot of time to switch processes. The time required for this process switching KJM is lO~1 compared to the time spent processing basic instructions.
00 times higher, which has the advantage of significantly lowering the performance of the system.

A register group storage device has been proposed which improves the above-mentioned drawbacks and makes it possible to substantially eliminate the time required for register groups to be overused when switching processes. This storage mtilL, 1 corresponding to the running ρ process
a register stutter of M1 that stores the contents of a set of the register groups; a register stutter of M1 that stores the contents of a set of register groups corresponding to the program being executed; and contents of a set of registers that are previously being executed; A second register stutter with two areas that can be used and these #! These operations are performed by receiving the 'γ address information for successive writing to the register stack in logic 1 and logic 2, the evacuation destination area pre-address i'*m, the recovery start instruction signal, etc. from the distribution instruction fetch device. It is equipped with a register group control 1111 circuit to control, and is used to execute instructions. M
WK is issued, and the operation result is simultaneously stored in the corresponding position of the first register stack and one area of the $2 register stack according to the register address information given from the instruction fetch device. When a recovery start instruction No. 16 for process switching processing is given from the instruction 7 etching device, the contents of a corresponding set of register groups successively retrieved from the cough tooth evacuation area of the Itl main memory are stored in the first
and another area different from the above of the second register stack, and in parallel with the execution of the instruction for the new process, the second The contents of a set of registers stored in one area of ``fic'' corresponding to the Metsu9 process during previous execution of the register stack are sequentially sent out and saved to the save area of the ilr owner's storage device. It is configured.

FIG. 3 is a block diagram showing an example of the storage #crit described above. That is, register group storage device 1
1t6 includes a first register stack 61 having 32 registers, a Jig2 register stack 62 having 64 registers, and a save 1 of the contents of these registers.
From the register group control circuit 63 that controls the recovery
will be accomplished. The above-mentioned register stack 61 carries 16 pace registers and 16 general-purpose registers that store the contents of a set of registers corresponding to the running process, and stores 32 words x 4 bytes of data. Can be stored. Also, the second register stack 62Fi, 64
It can store data of word x 4 bytes, and has two areas for storing one set of registers corresponding to the above-mentioned executing process and the contents of 1ffi register group corresponding to the immediately previous executing process. .

The register group control ML path 63#i supplies the read and write addresses of register operands used for instruction execution to these register stacks 61 and 62, and is normally used at the end of process switching processing. In parallel with the processing of the instruction, the contents of the register solution corresponding to the old process stored in the second register stack 62 are controlled to be saved to the main storage device l.

In the above-mentioned storage system tIL, during normal processing, register contents are revealed from the register stack 61 of theory 1, and the first and second register contents are 41 are stored in both register stacks of the register stack. As mentioned above, the second register stack 62 has two areas t and one of the areas # corresponds to the process being executed and has the same contents as the first register stack 61. The contents of the first stack 61 can be written and viewed at the same time. The contents of a group of nine registers corresponding to the process that was being executed one time before Fi are stored in the other area. The above two 1reas are alternately switched every time the process is switched.

FIG. 4 is a time chart showing the operation of the register group storage device during process switching.

At the time of process Kiriso (from ■ to ■ in the same country), the contents of the register group corresponding to the process to be executed in fl1 with main origin t4 are sequentially read from B to O.
The first and second register stacks 61 and 62 (-area of power) tC
Honor is poured out. In other words, (Regis) recovery processing is performed. At this time, the contents of the register group corresponding to the process that was executed immediately before remain in the other area of the second register stack 62.

Then, after the register recovery process is completed at time ■,
In parallel with the authenticity of the instruction, the contents of the register group corresponding to the direct-U process stored in the north area of the second register 6.2 are saved. That is, during times A11 (J~(), the contents of the upper ml area are sequentially transferred from B 0 to the corresponding areas in the main ml interpolation l.

Due to the above-described operation, the time used for process switching processing essentially becomes time contributing to register recovery processing, and
There is no need to consider the time for evacuation. In other words, approximately twice as much linkage as in the conventional example described above is achieved. However, there is still a huge difference in the execution time of the basic edict.
This is a major cause of deterioration in system performance.

It is an object of the present invention to solve the above-mentioned conventional drawbacks, to unify the process switching process and register group recovery process as much as possible, and to store register groups that can minimize the impact on system performance. There is a need to provide equipment.

The storage device of the present invention includes an instruction fetch device, a register group storage device, and a register group storage device to fetch and decode instructions from the main memory, execute the instructions, and execute the instructions. It performs switching processing for processes started by 'ps' or interrupts, and the program's processing is performed 8! The contents of one set of register groups used for operation for each unit of gross processing are stored one after another from the nine register evacuation area provided corresponding to the valley process of the main device, and stored in the register group storage JR device. p and the contents of a set of registers for a previously running process that were stored in the registers storage.
A central processing unit that executes 11 processes at the same time among the plurality of processes that are in the active state by scattering them in the corresponding register save area of the A control device.
! A first register stack for storing the contents of a set of IIU register groups corresponding to an executing process, and a register group corresponding to the executing process, in the register storage unit of the apparatus. a second register stack having a plurality of areas capable of storing the contents of the process, the contents of a set of registers previously being executed, and the contents of a register group corresponding to the process to be executed next; Address instructions are given to the first and second register stacks using the register address information etc. from the instruction fetch device, and the address of the second register stack is given using the execution area address information or transfer address information of the Rika circuit, which will be described later. control the insertion or continuation of a second register stack by instructing an area; and
At the end of the bale movement, send out No. 6 to end v1 and send out the second
A control circuit outputs a transfer end signal 16'@ at the end of transfer from the main memory to the register stack f, and a memory access signal is sent out in response to the recovery end signal from the control circuit, and after the completion of the recovery, the control circuit outputs a transfer end signal 16'@. A next process determining circuit that sends out a next process determining code upon receiving a memory end signal, and a register 11' provided corresponding to a plurality of areas of the second register stack and stored in each of these areas. It incorporates a plurality of stack management registers whose numbers are recorded in the process 4 corresponding to pK, and the process number in the process information from the instruction fetch device or the successive data from the main memory, the contents of the stack location register, and the meeting gross cut. Homare instruction signal or Mayu record next process decision'jt1g
and a management circuit that sends execution address information and a recovery end signal or transfer area address information and transfer instruction signal t to the control circuit according to the result of the comparison between the first register stack and the first register stack during normal instruction execution. The order is executed from the beginning, and the first calculation is completed.
The contents of the register group corresponding to the arrow process stored in one area of the register stack and the second register stack at the same time are stored in one area of the second register stack at the time of process switching.
tt is transferred to the first register stutter to complete the recovery process, and in parallel with the execution of the flk process, the next process code to be executed next is retrieved from the entire storage device and the process 4r. Determine whether or not the stack management registers of the stack management register match, and if they do not match, the contents of the corresponding register group are sequentially read from the save front rear start address of the main memory where the register group of the process is saved. It is assumed that the data is successively stored in another area of the second register stack.

Next, the present invention will be explained in detail with reference to the TM.

FIG. 5 shows one 511 of the present invention! In addition to register storage, Makoto [6, city ordinance fetch narrow 1. f4 Reiko #l
A system that includes $1 and one main unit.
□This is a block diagram of 4 plants. That is, the main storage device 1t
l and Chuojo J! The central processing unit 2 includes a line segment fetch unit 3, an instruction execution unit 4, and a register storage unit 6. Except for the register group storage device 6, the configuration is the same as that of the conventional example shown in FIG. 1 or FIG. 3 described above. The register group storage device 6 stores 1i41 register stacks 61. Second register stack 62. Control circuit 631 Next process determination circuit 65. Management circuit 66, f
It is composed of i selection circuits 601 and 602.

The first register stack 61 is a register that stores a group of registers corresponding to the running process, and is 32 words×
It has a 4-byte structure. Then, the contents of the addresses specified by the control circuit 63 are successively sent to the instruction fetch device 3 and the instruction execution device 4, and selected by the selection path 601 and output from the nine instruction execution device 4 or the second register stack 62. Writes the threading data to the specified address.

The second register stack 62Vi has a capacity four times that of the first register stack 62, that is, 128 words x 4.
It has a byte structure and is divided into four areas.

The storage capacity of each area is 32 words x 4 bytes, and a 2-bit address is assigned to each area. Of the four areas mentioned above, one is an area that stores a group of registers corresponding to the process being executed.
11 is replaced simultaneously with the first register stack.

The other area is the register group storage area for the process that is directly executed by HVC, and the remaining area 9(2') is used to store the register group for the next process to be executed. Ru. The selection circuit 602 selectively selects the output of the instruction execution device 4 or the start-up data from the main memory device 1 and supplies it to the second register stack 62 . Second
The address and area designation to be inserted into the register stack 62 are given from the control circuit 63'. Then, the contents of the register group corresponding to the next vc-dedicated process are transferred from the main memory 1 and stored in one area, and are transferred to the first register via the selection circuit 601 at the time of process switching. stack 6
Transfer to 1. These operations are performed by the control circuit 639 and the next process determining circuit 65. ``#jj I/A &!! 1st route 66 etc. ToK.

Control a circuit 63t'i, address 1itl# for Ml and second register stacks 61 and 62, and a circuit for controlling access to main memory 1 independently of instruction execution, and is shown in FIG. jlE6. K yr<
is configured to do so. That is, the address register 631 stores the register address information 71 from the instruction fetch device 3 in response to the register access instruction signal 72.
9. A good recovery address register 637 that provides the address of the 2000-200 register stack during recovery operations, etc. A selection circuit 632 that selectively selects the outputs of both the registers and supplies them to the first register stack 61. a selection circuit 633 that selects an address to be supplied to the second register stack 62;
Execution area address information 8 given from the management circuit 66
8 or transfer area address information 89 (2 bits)
is selectively outputted to the second register stack 62-4.
A selection circuit 634 for specifying one of the two areas. '!
A recovery instruction register 635 that sets a recovery instruction signal 74 provided from the logic circuit 66. Transfer instruction register b4 that sets the transfer instruction signal 81 given from the management circuit 66
5. [Ouki customary expression] Gara no Sudoku Data 85) ° position 24
Bit 79 and [! 11 constant +m A and "+4'"
2. Next process determination circuit 65
The selection circuit j1643 selectively outputs the upper one signal and supplies it to the memory address register 642 according to the next process number 16 8o given from the next process or the recovery completion r value given via the AND circuit 641. ．． The above memory address register 642゜The contents of the register 642 are +4
All of the circuit 644゜recovery address register 637
@1” is detected and the output is 01 through the AND circuit 641.
ALL@l” Detection 11NI to output end 1g No. 75
640. It is made up of a large number of child circuits and AND circuits, etc., which output various signals for setting, resetting, or directing each virtue register by AND or OR of each value signal. The OR circuit 648 receives the next process determination signal 8o from the next process determination circuit 65.

The output signal 75 of the AND circuit 641 and the output signal 1g of the AND circuit 647 are input by an OR circuit, and these signals are sent to the set terminal 8 of the memory address register 6420. The AND circuit 647ri manually inputs the memory end note 78 from the main memory device ml and the output of the transfer instruction register 645, and sends the output to the OR (b) path 6.
48 and the AND circuit 6500A, the AND circuit 650 connects the output of the AND circuit 647 and the output of the AND circuit 647.
The output of the output circuit 640 is inputted manually, and a transfer end signal 82 is sent to the iIA circuit 66. ! Friend, AND circuit 651 between memory end signal 78 and ALL "l" detection circuit 640
, and the transfer instruction register 645 is reset by its output. The output of the transfer instruction register 645 and the memory access signal 76 from the next process determining circuit 65 are passed through the OR circuit 646 as a memory request No. 46 77 to the main router l.

(9) The output of the transfer instruction register 645 and the output of the Igl finger register 635 are passed through an OR circuit 639 to the switching circuit 633 as a switching @ signal. A> VIm road 6
41 HALL, "1" detection 1t1 circuit 64011!1
The output of the 01 finger register 635 is manually input, and the output is the recovery end r times number 75 mentioned in @. The output of the recovery address register 637 is incremented by +1 by w163gnC and the register internal medicine is incremented by +1.

With the above configuration, the operation of the # control circuit 63 is as follows. Normally, the register address information 71 iI from the instruction fetch device I/1.3 (therefore, it is the write/read address of the first register stack 61, and
The lower 5 bits of the write address of the register stack 62 of The upper two bits of the second register stack 62, that is, the four areas mentioned above, are designated by the execution area address information 88 from the management circuit 66.

Recovery instruction No. 16 7 from the management circuit 66 at the time of process switching
The output of the recovery address register is given to the @l and 2 register stacks 61 and 62 through the selection circuits 632 and 633t, and is sent to the corresponding area indicated by the execution area address information 88 from the management circuit 66. Out of the stored register group, d is sequentially read from the 0th location and transferred to the l-th register stack 61. The initial state of the uom address register 637 is '0' and is sequentially incremented by +1. That is, the contents of the area corresponding to the process to be severely contaminated are stored in the first register stack.

When the output of the recovery address register becomes ALL"]", the output of the AND circuit 641 sends the end of rounding signal 75 to the next process determining circuit 65. Also ALL'''1''-
The output of the output circuit 640 causes the register 63 to
5 will be reset.

The output of the AND circuit 641 is applied to the set input 8 of the memory address register 642 through the OR circuit 648t, and the fixed value A applied through the selection circuit 643t is set in the register 642. Then, the memory access signal 76 from the next process determination circuit 65 becomes the memory request signal 77 to the main kitm scissors 111 via the OR circuit 646, and the Igtl fixed hani A is set as the main memory address 83 to read and access the Oki Gakusou mi. A request is made. At address A in the iJ1 table, as shown in FIG. 9, the process number is stored in the upper 8 bits and the register # save area start address is stored in the lower 24 bits.

Similarly, the number of each process and the next address of the N1 area are stored at addresses A+4, A+8, . . . . It is assumed that these are stored in memory for processes with high priority, and those corresponding to the next process are moved up to address A. Then, when the thread takeout take 85 from address A of the main ela* device is included, the lower 24
A bit (save area first application address) is input to the selection circuit 643, and the above save area first application address is selected and set in the memory address register 642 by the next process determination signal 8o from the long process determination register 65.

Next, when the transfer instruction signal 81 is given from the 'tml path 66 (as will be described later, it is not always given)
, the transfer instruction register 645 is set full, the OR circuit 64
A memory request signal 77 is sent via the main memory iron fl
Output to ltl.

Every time reading of one word from the retirement area prefix address of the main storage device 1 is completed, the memory end number 78 is inputted, and the memory address register 642U+4 circuit increments the memory by 4 and sends out the 9th address. - Force, above memory eaves f
The flip-flop 649 is set by the signal, and the recovery address register 637 outputs the address incremented by 1+11 by the +1m circuit 638 and sends it to the second register stack 62 via the selection circuit 633. Select the 2-bit address!!
At 1wl634, the transfer area address flv information 89 from the 11 salt circuit 66 is selectively output. Therefore, the transfer area of the second register stack 62 is lowered @8.
The contents of the register group corresponding to the next norocess VC are sequentially written into the area added in step 9 starting from the OII location. Posting is finished, ALL @l'' two swords of 640 Ujide Yotsuji @1II
When the memory end f1 fi 878 is transferred from the main storage device l, the transfer instruction register 645 is reset by the output of the AND circuit 651, and the output of the AND circuit Ii & 650 becomes 11'', and the transfer path rIg 82 is managed. circuit 6
Sent to 6.

Meprocess fire constant circuit 66ri, real? This circuit is configured as shown in FIG. 7, and determines whether a process that has been placed in a T-wait state will still have priority. In other words, the injury end/1g given from the control circuit 63
It consists of a register 655 for setting the number 75, and an AND circuit 656 which manually inputs the output of the register 655 and the memory 78 from the main storage device 1. The output of the f register 655 at the end of Q1 of the previous cycle is the output of the circuit 63.
The output of the previous AND circuit 656 is sent to the control circuit 63 and the management circuit 66 as the next process determination signal 8o. In addition, register 6
55ti memory end fjt1 No. 78 is reset. Due to the above-mentioned S configuration, when the memory end f signal 78 is input manually, the next process determination signal 80 is output via the AND circuit 656.
At the same time, the program ends, the register 55 is reset, and the sending of the memory access signal 76 is stopped.

1 [1 path 66ti, determine whether or not it is necessary to fill the storage 1'# of the second register stack 62 and transfer the contents of the register group corresponding to the next process from the main memory 1 w#t
This is a circuit that determines the method of register recovery processing when -L and process cut-off V, and is configured as shown in Figure M8. That is, the upper 8 bits 87 (next process book number) of the start-up data given from the control circuit 63 and the process number information 89 given from the instruction fetch device 3 are input, and the above-mentioned number is changed by the process switching instruction signal 73.
Selection circuit 664 which selects 89' and inputs the process number register 665 manually. and the process number register 665. The OR circuit 663,1! which inputs the process switching instruction signal process determination signal 80 and outputs it to the set terminal of the distal 650! A process switching instruction register 661 that sets the # period process switching instruction signal 73, and a next process determination register 662 that sets the III period process determination signal 80.

An OR circuit 676 inputting the outputs of both registers 661 and 6620 is provided corresponding to each area of the second register stack 62, and indicates the process number and validity corresponding to the register group stored in each area. Stack management register 6 that stores the V bit to be displayed
66-669.

The contents of the registers 666 to 669 and the register 665
Compare the contents of v.
Comparison circuit 670 that outputs “l” when the bit is @l”
~673, a 4-bit execution area display register 678 that holds the output of each of the above comparison circuits, and the above comparison circuit 670
OR circuit 674, which manually outputs the output of ~673, OR circuit 6
inputting the output of 74 and the register 6610 Deba;
An AND circuit 675 that sends the recovery finger unbiased signal 74 to the control circuit 63, the stand power of the OR circuit 674, and the OR circuit w.
5676 and outputs the transfer end signal 81. Encodes the output of the tljJ register 678 and stores 2-bit execution area address information@
Encoder 679 outputting 88, the register 67
Transfer area ay to set by rotating the first order of output of 8 clockwise
s<register 681. An encoder 682 encodes the output of the d register and outputs 2-bit transfer area address information @89.

Input the output of each bit of both registers 681,
It is composed of AND circuits 683 to 686, etc., which perform an AND operation with the transfer end signal 82 and output set signals to the stack management registers 666 to 669, respectively.

The operation of the management circuit-66 is as follows.

During normal instruction execution, the process number information 89't register 665 given from the instruction fetch device 3
It stores a group of registers corresponding to the corresponding process number detected by the comparison circuits 670-673 (
area of the second register stack 62 is held in the active area display register 678. The encoder 679 then sends the area address information 88 being executed to the control circuit 63.

At the time of the process promotion process, the process number t#@s9' and the process promotion signal 73 are given from the joint fetch*. The selection circuit 664 selects the process number information 89' and supplies it to the register 665.

The process switching instruction signal 73 is input to the register 6650 through the OR circuit 663, and then to the register 665.
The process number information 89' is set in . Also,
Register 661 is also set. Comparison circuit 670-67
3 compares the contents of the stack management registers 666 to 669 with the contents of the register 665, and returns the stack 1ftj! ! ! @1 if the V bit of the register is 11
`` is output. When any one comparison path `` is output, a recovery error signal 74 is sent to the control circuit 63 via an OR circuit 674 and an AND circuit 675. At the same time, the corresponding bit of the executing area display register 678 is set to 11". Agreeing to the above, there are nine register groups in the register stack 62 of #I2 (in FIG. 5) corresponding to the process to be executed. If it has already been stored, it sends the decode instruction code 74 to the control circuit 63. Also, the contents of the execution area display register 678 are converted to 2 bits by an encoder 679 and sent as execution area address information 88. be done.

The above-mentioned signal 74 and the execution area address [88] are used to perform the four-barrel processing under the control of the control circuit 63, and after the recovery is completed, the upper eight bits 87 of the successive data successively continued from address A of the main memory ff1l. (next process μ process number) is input to the selection circuit 664, selected by the selection circuit u664, and input to the register 665.

Set up a meeting. Further, the next process determination register 662 is also set. On the other hand, the contents of the register 665 are compared with the contents of the stack management registers 666 to 669, and if no match is detected in any of the comparison circuits 670 to 673, the negative output of the welfare OR circuit 674 becomes @1'''. The transfer fingers 7F and 1N 81 are sent to the control circuit 63 through the comparison circuits 670 to 673.
If a match is detected, the next process is already 17g2
Therefore, the above transfer instruction is unacceptable. The control circuit 63 controls the transfer operation, and when the transfer end signal 82 is sent at the end of the transfer operation, the AND circuits 683 to 686 are opened and the bit 111 of the transfer area display register 681 corresponds to the bit outputting the sound. A set signal is given to the stack management registers 666 to 669, and the register 66
5 output and the V bit is set. That is, the next process number is set. Accordingly, when the process switching instruction signal is issued next, the address information of the corresponding area, that is, the execution area address 88 and the recovery instruction signal 74 can be output as described above.

FIG. 10 is a rounded diagram illustrating the transfer status during process switching processing, next process determination processing, and memory self-answer transfer processing. Next, the operation at each point in time will be explained with reference to FIGS. 5 to 8 and FIG. 1θ.

During normal read execution, register operands are successively fetched from the first register stack 61 to the instruction fetch device 3 and instruction execution Mt4, and the operation results in the instruction execution device 4 are transferred to the register 1 and the second register. stacks 61 and 6
20 are written to both. In this case, the upper two bits of the second register stack are given execution area address information 88 from the logic circuit 66 via the control circuit 63.

Next, in the process switching process, at time ■ in the M2O diagram, the process switching process is performed from the instruction fetch device 3 to the process switching process 4'tj yr
'z Ir1 number 73 and process number information 89' are given to the management circuit 66, and execution area address information @88 indicating the area of the second register stack storing the register group corresponding to the process and recovery instruction are given to the management circuit 66. (−
No. 74 is sent from the management circuit 66 to the control circuit 63. As a result, the control circuit 63 controls the second register stack 6
The corresponding area of No. 2 is sequentially read from the 0th tail and transferred to the first register stack 61 for writing. That is, B
3 from RO to BRI 5 and Gru 0 to GK15
2 words are transferred. When the transfer ends and the process switching process is completed at the time shown in FIG.

The next process determining circuit 65 determines whether the recovery has ended/rO! No. 7 No. 5
Set in return end register 655 and memory access 16
No. 76 is sent to the control circuit 63. The memory access signal?
6t'i, it is sent to the main memory device l as a memory request signal 77 via the OR circuit 646 of the control circuit 63, and -
Then, the address is fixed (IEA is sent out as the main memory address 83) from the memory address register 64 of the input terminal 63. In other words, successive accesses to the main memory device 1 are performed,
Continuation data 85 from the main storage device is returned. The lower 24 bits 79 (register group save area preset address) of the successive data are set in the memory address register 642 via the selection circuit 643 of the control circuit 63. The upper 8 bits 87 (process number) are the management The selection circuit 664 of the circuit 66 is operated manually. When the memory end signal 78 from the main storage device 1 is applied to the next process determining circuit 65, the memory access signal 76 disappears and the next process determining signal 80 is output. The storage circuit 66 receives the signal 8
#) Set the next process determination register 662 to 0,
The above-mentioned continuous output monitor upper 8 bits 87 (next process instruction)
is set in register 665.

When the contents of the register 665 do not match any of the stack management registers, a transfer instruction signal 81 is sent from the management circuit 66 to the control circuit 63. Further, the transfer area address information 89 outputs 2-bit information specifying the next area of the area being executed in the second register stack 62. When the contents of the register 665 match those of any stack management register, the transfer instruction signal 81 is not output. When the transfer instruction signal 81 is input manually, the control circuit 63 transfers the memory request signal 77 to the above [
#e11111 K is sent, and the next process's save area first application address, which has been set in the memory address register 642, is successively acknowledged.

The indulgence data from the upper storage device [1 85 i.e. kl)t
The contents of o are written to second register stack 62 via selection circuit 602. The area of the second register stack 62, that is, the upper two bits, is ! platform circuit 66
The mourning transfer area address information 89 given from . The lower 5 bits are the recovery address register 63.
7 output is selected. The contents of the above BKQ are transferred, and the contents of the memory address register 642 are incremented by 4, and the contents of the recovery address register 637 are incremented by 1, and the contents of the memory address register 642 are incremented by 1.
)415 and the contents of qru0 to qru15 can be transferred (
110 subtime)~■). Transfer is Nr, ALL@l
'''The output of the detection circuit 640 becomes 11, and by ANDing with the memory end signal 78, the personal sending if value number 82 becomes the tube embedded circuit 6.
6, the transfer request register 645 is reset, and the memory request signal 77 disappears. When the management section 66 receives the transfer charge r'tti number 82, it sets the V bit and the process arrival number register 66 in one of the stack management registers 666 to 669 corresponding to the transfer area.
Set the contents of 5 (next process number). After the end of the process switching process m described above, that is, the time R when the recovery is completed (time ■ in FIG. (Time■
~(su) and memory content transfer processing IIC 'jillL
Steps 1 to 2) are performed in parallel with the execution of the instruction. Also, the process switching process (time ■ to ■) is as follows.

By simply transferring the contents of the second register stack to the register stack 1@registor stack, the contents of the m2 register stack are transferred from the main memory 1 to the m2 register stack. The cutting process is done quickly.

Next, rC for process switching is processed in the same manner as described above, and the register group corresponding to the next process is written into the remaining area of the second register stack 62. Furthermore, when the next process is replaced and writing by the 161st process is required, the contents of one area of the register stack b20 of #s2, which corresponds to the very first process and stores the contents of the good register group. It is sufficient to save the register l# of the next process to the main storage area [1, and then store the register l# of the next process in the area.

At the time of process switching processing, if the contents of the register group corresponding to the eaves process do not exist in the register stack 62 of @2, first, the memory contents are transferred from the main memory device l to the second register stack 62 by the transfer instruction signal 81. but(
32 times), the transfer from the second register stack 62 to the register stack 61 of WJl is performed in accordance with the pc N *instruction signal 74. However, in such a case, there is only the aJ symptom that occurs during interrupt processing, and it hardly occurs.

In this embodiment, the second register stack 62 has four registers #P, but it is also possible to further increase the number of valleys and wrinkles. The distribution of the number of processes depending on the environmental conditions under which the processor is used.

It may be designed arbitrarily depending on the switching frequency or required number of nodes.

As described above, in the present invention, e, a plurality of register groups are stored I1. Possible#! 2 register stacks are provided to store the contents of the registers of the process that previously executed an instruction, the registers of the currently executing process, and the registers of the process to be executed next. When executing instructions by reading and writing from the register stack, the operation results are simultaneously written to the second register stack, and when switching processes, the I/O is stored in another area of the second register stack in advance.
The contents of the register group of the next process that is currently running are transferred to the first register stack and the instruction is executed, and in parallel with the execution of the instruction, the contents of the register group corresponding to the next process are transferred to the main memory. Since the configuration is configured such that writing is performed from the corresponding save area to another area of the second register stutter, there is an effect that the contents of the register group are quickly transferred to the register stack of llll1 at the time of process switching. The operation of reading the contents of the register group corresponding to the next process from the main memory and writing them to the second register stack described in llJ and the operation of saving them to the main memory when necessary are performed in parallel with the execution of instructions. Because of this configuration, the time for process switching processing is not substantially extended. That is, the process switching process can be completed quickly without requiring only the transfer time from the second register stack to the register stack of the IEI.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a computer system using the conventional register group storage device, Fig. 2 is a time chart for explaining the operation of the conventional example, and Fig. 3 is another improved register group. A Bona block diagram of a conventional example of a computer system using a storage device, Figure 4 is a time chart for explaining its operation, Figure 5 is a block diagram showing -*mn of the present invention, and Figure 6 is a diagram showing the above implementation. FIG. 7 is a block diagram showing an example of the #l configuration of the control circuit of the example, FIG. 7 is a block diagram showing an example of the configuration of the long process determination circuit of the above embodiment, and FIG. 8 is a block diagram showing an example of the configuration of the management circuit of the above embodiment. A block diagram, FIG. 9 is a diagram showing the storage four-foot of the process number and register group save area address in the main memory, and FIG. 10 is a time chart for explaining the operation of the embodiment shown in FIG. 5. It is. In the figure, l...main storage device, 2... central processing jj
l device, 3... Instruction fetch device, 4... Instruction actualizing device, 5... Register group storage device, 6... Register group storage device [51... Register stutter, 52... Address register, 61...1st register stack, 6
2... IJJ2 register stack, 63... Control circuit, 65... Next process determination circuit, 66...'
t7ta+ circuit, 601°602... selection circuit. Fig. 1 Fig. 2 No. 4 No. 5 No. 6 Fig. 1 Missing Ax 3 1) t

Claims (1)

[Claims] an instruction fetch device, an instruction execution device, and a register group storage device for fetching instructions from the main memory;
It decodes, executes instructions, decodes instructions, and switches processes activated by interrupts, and stores the contents of a set of registers used for performance for each process, which is the processing unit of the program. A register saving area provided corresponding to each process associated with the main origin u1 is successively written and stored in the register si_i_1tt.
1 for previously running processes stored in rc
A central processing unit that simultaneously executes one process out of a plurality of processes in an execution port by saving the contents of a set of register groups to a corresponding register save area of the main storage device. In the register group storage device, a first register stack that stores the contents of the register group of 1ffi corresponding to the executing process, and a set of register groups corresponding to the process that is being distributed. A JI2 register stack having a plurality of areas capable of storing contents, contents of a set of registers currently being executed, and contents of a register group corresponding to a process to be executed next; The cocoon branch command is sent to the -1Ml and jK2 register stacks using the register address information from the device, and the execution area address information or transfer address f' from the t logic circuit, which will be described later, is executed.
# information F (Therefore, specify the area of the second register stack in Ii + 7 to perform priority access or continuous output of the second register stack, and from the second register stack to the eiJ1 first register stack. recovery - a control circuit which sends out a 4r signal for the transfer when the transfer from the main memory device to the second register stutter is completed by sending out the Ensai Termination Bond by @r of the work, and a circuit from the control circuit; Temporary end r partial code I/C sends memory access 1 month meeting; after the above recovery P and r, memory end r1d is received from the main storage device, next process decision 11i is sent out. , which is provided corresponding to a plurality of areas of the second register stack, and has a plurality of built-in stack layer registers for registering process numbers corresponding to register groups stored in each of these areas, and has a built-in plurality of stack layer registers for registering process numbers corresponding to a group of registers stored in each of these areas. The process information or the process number in the successive data from the main U1 device is compared with the contents of the stack layer register using the process switching instruction signal or the next process determination signal, and the process information and the address information being executed are an 'f logic circuit that sends a recovery instruction signal or transfer area address information and a transfer instruction signal to the control circuit, and during normal instruction execution, instructions are executed one after another from the first register stutter, and the operation is performed. The results are stored simultaneously in one area of the first register stack and the $2 register stack, and are stored in the second register stack at the time of process switching.
The contents of the register group corresponding to the next process stored in one area of the register stutter of are transferred to the first register stack to complete the recovery process, and then, in parallel with the execution of the process, the contents of the register group corresponding to the next process are transferred to the first register stack. The next process code to be executed is retrieved from the main memory, and the presence or absence of the corresponding process number -1 and one of the plurality of stack registers is detected, and if both are invalid, the process is executed. The contents of the corresponding register group are sequentially generated from the address of the first application in the main storage area where the registers have been saved.
A register group storage device whose special value is to store data in another area of the register stack.