JP2794782B2 - Instruction fetch device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an instruction fetching device in a high-speed information processing device.

2. Description of the Related Art In recent years, in a high-speed information processing apparatus, an instruction buffer subsequent to an instruction sequence being executed is read from a cache memory in parallel with execution of an instruction, and an instruction buffer for temporarily storing the instruction sequence is read. Often have. A series of processing stages corresponding to the steps of fetching an instruction from an instruction buffer, decoding an instruction, and preparing an operand; pipeline processing for sequentially flowing instructions to the series of stages at the cycle of a machine cycle for processing; Is often performed.

Conventionally, as one of the instruction fetching methods in a processor dedicated to scientific and technical calculations, the capacity of an instruction buffer is, for example, several K
The instruction word is enlarged to about a byte, divided into a plurality of blocks, and the instruction word being executed in the instruction word area of the storage device is transferred to the block on the instruction buffer in block units. At the same time, means for holding the instruction address of the instruction word held in each block of the instruction buffer is provided, and the address of the address holding means is searched by the address of the instruction word to be decoded. In this method, an instruction is sequentially fetched from the block to the decode stage. The address in the instruction buffer is different from the address in the main memory, and is composed of a block number and a word number in a block in the instruction buffer, and sometimes a word number in a word.

When reading to the end of a block and reading the first instruction of another block, or when reading the branch destination instruction specified by a branch instruction, a predetermined instruction word is not in the instruction buffer (instruction buffer miss In the case of (1), an area on the storage device including a predetermined instruction word is transferred to one of the plurality of blocks. This is called rewriting the block of the instruction buffer.

[Problems to be Solved by the Invention] However, the conventional instruction fetching apparatus described above has a disadvantage that block rewriting frequently occurs when branch instructions are consecutive. In other words, if there is a loop that jumps one block after another from the number of blocks held by the instruction buffer one after another, the number of instructions executed in one block is small, but mishit often occurs, and the instruction buffer is stored in the storage device. Loss time due to transfer to the server increases.

Accordingly, a technical object of the present invention is to provide an instruction fetching device that reduces the number of instruction buffer misses in view of the above-mentioned drawbacks.

[Means for Solving the Problems] According to the present invention, an instruction buffer that holds instruction words read from a storage device in block units, and an instruction buffer that holds the instruction words in the block group corresponding to the number of blocks in the instruction buffer Address holding means for holding a head address of an instruction word to be read, an instruction counter for holding upper bits of the address of the instruction word read from the instruction buffer, and a block number of the instruction word read from the instruction buffer An instruction pointer indicating an address in the block; and a frequency measuring means for counting how many times a case where the instruction word to be read does not exist in the instruction buffer occurs within a predetermined time. When the frequency indicated by the measuring means exceeds a predetermined number, the block size of the instruction buffer is reduced and the number of blocks is increased. An instruction fetching device characterized by the following.

Example Next, an example of the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 is a block diagram of an instruction fetching device according to a first embodiment of the present invention. In this embodiment, the instruction length is 4 bytes, that is, 32 bits, and the logical address of the instruction is a 30-bit byte address.

In FIG. 1, the instruction buffer 3 has a configuration of 32 bytes × 64 words, and is realized by a storage element capable of simultaneously reading and writing. Block 0, block 16 every 16 words
Modes used as 1,2,3 (hereinafter referred to as 4-block mode) and blocks 00,01,10,11,20,21,3 every 8 words
There is a mode used as 0, 31 (hereinafter referred to as an 8-block mode).

First, the operation in the 4-block mode will be described. In each block of the instruction buffer 3, one block of instruction word information in the cache memory, that is, starting from a 512-byte boundary
12 bytes of information are loaded. Write data register 2
Is a register for receiving the response information from the cache memory once at the time of loading and rewriting it in the instruction buffer, and is 32 bytes. The selector 4 selects one of the eight words read out from the instruction buffer 3, and its output is strobed into a 4-byte instruction register 5.

Start address registers 21 and 25 are in instruction buffer 3
This register is for holding the upper 24 bits of the address of the instruction word held in the first 256 bytes of the blocks 0 to 3 of FIG.

Start address registers 31 and 35 are in instruction buffer 3
This register holds the upper 24 bits of the address of the instruction word held in the latter 256 bytes of blocks 0 to 3.

Although a part is omitted in FIG. 1, a total of eight head address registers are prepared for each block of the instruction buffer 3. However, the main address registers 21 and 25 are mainly used in the 4-block mode.

The instruction counter 18 stores the upper 24 bits of the address of the instruction word read from the instruction buffer 3 in the storage device and the initial value of an instruction counter (not shown).
It is a register in which the upper 24 bits of the initial IC) and the upper 24 bits of the address of the instruction word at the branch destination specified by the branch instruction are set. The value of the instruction counter 18 is compared with the start address registers 21 and 25 by the comparators 22 and 26.
The block number and the destination of the instruction word at the branch destination and the crossover destination (the sequence in which the instruction word to be read moves from the last instruction word of a block to the first instruction word of another block) The block number where the instruction word is called is obtained.

Here, two counters input to the instruction buffer 3 will be described.

FIG. 3A shows the read address of the instruction buffer 3.
FIG. 3 is a diagram showing a format of a counter (hereinafter, referred to as an “instruction pointer”) 6. Bits 0 and 1 are block numbers, bits 2
5 indicates the word number in the block, and bits 6 to 8 indicate the word number in the word. When an instruction word is sequentially read from the instruction buffer 3, the lower 7 bits of the bits 2 to 8 are incremented by 1 in the circuit of the +1 adder 11 and the selectors 9 and 10. Bit 2
Indicates a word number in the 4-block mode and a block number in the block mode. The selector 8 selects the input to the block number portion of the instruction pointer 6, and supplies the input data to the signal lines 202 for the bits 0 and 1 and the signal line 204 for the bits 2. The selector 9 selects the input to the word number part and the word number part of the instruction pointer 6, and selects the bit 2
, And the input data of the signal line 201 is supplied to the bits 3 to 8. The selector 10 finally selects the input data of bit 2 via the signal line 203. That is, the signal line 205 is selected in the 4-block mode, and the signal line 204 is selected in the 8-block mode.

FIG. 3B shows the format of the counter 1 for the write address for the instruction buffer 3, which is the same as FIG. When the instruction word information is being loaded from the main memory or the cache memory into the instruction buffer 3, bits 2 to 5 are incremented by one, and the instruction word information is sequentially written into the instruction buffer.

A round robin (hereinafter referred to as RR) 12 is a register indicating the block number of a load destination when the instruction word information is loaded from the main memory or the cache memory to the instruction buffer 3, and has a format shown in FIG. ). The block number of the load destination is carried around from block 0 to block 3 in sequence regardless of the past access history. Therefore, every time a block load request is issued, RR12 is +2.
(Note that bit 4 of RR12 is meaningless in 4-block mode).

The control circuit 38 is a circuit for generating signals for reading and writing the above-mentioned instruction in the buffer 3, register strobe, and register input / output switching.

Next, the operation in the 4-block mode will be described with reference to FIGS. Upon receiving the instruction fetch start instruction, the control circuit 38 sets the upper 24 bits of the initial IC in the instruction counter 18 via the selector 17, and sets the lower 7 bits of the initial IC in the word number part of the instruction pointer 6 in the block. Set to word number part in word. In the 4-block mode, the LSB of the instruction counter 18 and the M of the word number part of the instruction pointer 6
It overlaps with SB (bit 2).

At the time when the start instruction is received, a valid instruction word has not been loaded in the instruction buffer 3 and the start address register
The validity indication bits (hereinafter referred to as V bits) 20, 24, 30, and 34 provided for 21, 25, 31, and 35 are all in a reset state. Therefore, none of blocks 0 to 3 hit, and the value of the instruction counter 18 is used as an access address.
A block load request is sent to a cache memory (not shown). Since the block number of the load destination selects the block indicated by RR12, block 0 is initially selected.

When the control circuit 38 receives the response signal from the cache memory, the control circuit 38 transmits 32 bytes × 1 transmitted through the data line 600.
The response information of six times is written into each word of the block 0 of the instruction buffer 3. Information includes request address information
Sent 16 times, starting with 32 bytes.

When the control circuit 38 receives the response signal, the control circuit 38
18 to the start address register 21 and the instruction counter 18
Is set in the start address register 31 (the selector 29 selects the signal line 400), and the V bits 20, 30 corresponding to this register are set. As a result, the output of the comparator 22 becomes “1”, and the hit signal 501 and the block signal 500 are output from the encoder 27. Although the block number signal 500 is a 3-bit signal line, the LSB has no meaning in the 4-block mode. The outputs of the comparators 32 and 36 are always "0" in the 4-block mode, and the comparison result is enabled by the 8-block mode 600.

The control circuit 38 sends the block number signal 500 to the instruction pointer 6
, And then the lower 7 bits of the counter are sequentially incremented by +1 (referred to earlier in the description of FIG. 3A). As a result, predetermined instruction words are sequentially read out to the first register 5.

When the lower 7 bits of the instruction pointer 6 indicate all "1", that is, when the instruction word address at the end of the block is set, the detection circuit 7 generates a +2 select signal 200,
As a result, the value of the instruction counter 18 becomes + through the selector 17.
+2 is added by the two adder 19. Using the comparators 22 and 26, the value of the +2 incremented instruction counter 18 is
Compared with the registers 21 and 25, the block number with the instruction word of the block destination is obtained by the coincidence output.

As a result of the search described on the left, when the block beyond the block exists in the instruction buffer 3 (called a hit), the output 500 of the encoder 27 becomes the block beyond the block, and is set to the upper 2 bits of the instruction pointer 6. The instruction word beyond the block is read. When a block-priority block does not exist in the instruction buffer 3 (called a miss hit)
After reading all the instruction words of block 0, a block load request is issued to the cache memory.

As described above, the block indicated by RR12 is the control of the block load. The output 100 of RR12 is supplied to the write address counter 1 and the instruction pointer 6 via the selector 8.
Is set to the upper two bits of The value of the instruction counter 18 and the value of the instruction counter 18 are further increased by +1 in the head address registers 25 and 35 corresponding to the block indicated by RR12 (for example, block 3) by the trobe signal 103.
Is set, and V bits 24 and 34 are set.
The rest is the same as the sequence when the start instruction is received.

When the instruction word read from the instruction buffer 3 is a branch instruction and the branch instruction 201 is issued from the execution stage of the pipeline, the upper 24 bits of the branch destination address output from the address operation unit are stored in the instruction counter 18. And the lower 7 bits of the branch destination address are set in the word number part and word number part of the instruction pointer 6. Next, the value of the instruction counter 18 is compared with the start address registers 21 and 25 using the comparators 22 and 26, and the block number having the instruction word at the branch destination is obtained by the coincidence output. As a result of the search on the left, if a hit is found, the output 500 of the encoder 27 is set in the upper two bits of the instruction pointer 6, and the instruction word at the branch destination is continued. If the search result is a mishit, a block load request is issued. The subsequent sequence is the same as the case of a block crossing miss.

Next, the operation in the 8-block mode will be described. In the 8-block mode, each block (blocks 00, 01, to 31) of the instruction buffer 3 stores one block of instruction word information in the cache memory, that is, 256 blocks starting from a 256-byte boundary.
The byte information is loaded. Start address register 21
And 25 are registers for respectively holding the upper 24 bits of the address of the instruction word held in blocks 00, 10, 20, and 30 of the instruction buffer 3. The start address registers 31 and 35 are registers for storing the upper 24 bits of the address of the instruction word held in the blocks 01, 11, 21, and 31.

The outputs of the comparators 32 and 36 for comparing the instruction counter 18 with the start address registers 31 and 35 are enabled by the 8-block mode signal supplied from the mishit frequency measuring circuit 39. The transition from the 4-block mode to the 8-block mode occurs when the number of miss hits occurring within a certain time exceeds a prescribed value. The miss / hit frequency measurement circuit 39 is a circuit that counts the number of miss hits, and has a mode bit indicating which block mode the instruction fetch device is currently operating.

FIG. 2 shows the details of the mishit frequency measuring circuit 39. When a mishit occurs due to block crossing or branching, the mishit counter 60 is counted up by the mishit signal 502. After a certain time has elapsed, the timer 62
The mishit counter 60 is cleared by the reset signal 64. The decoder 61 sets an eight-block mode bit via the set signal line 65 when the value of the mishit counter 60 exceeds a specified value. Once the 8 block mode bit is set, its output is sent to each selector and cache memory of the instruction fetch device, and thereafter, the instruction fetch device 8
Operate in block mode.

FIG. 4 shows an example of a program in which a miss hit frequently occurs during operation in the 4-block mode. In this example, LBL1 to LB
Branch instructions are consecutive up to L5, and each branch instruction is 512B
It is distributed over five blocks of units. Therefore, when trying to execute from LBL1 to LBL4, four blocks of 512B unit shown in FIG. 4 are mapped to blocks # 0 to # 3 of the instruction buffer 3, respectively. When executing LBL5, the contents of block # 0 (512B including LBL1) include LBL5.
Replaced by 2B. LBL1 to LBL5 form a loop of 100 times, and after executing LBL5, LBL1 must be executed again.

However, since the block containing LBL1 has been replaced with the block containing LBL5 immediately before, an instruction buffer miss occurs. This time, block # 1 (512B containing LBL2 is loaded) is replaced with the block containing LBL1. . Similarly, when any of the branch instructions in the loop is executed 100 times, an instruction buffer miss occurs, and a block load is performed. That is, the instruction fetch is performed not on the instruction buffer 3 but on the cache memory, and the existence of the instruction buffer 3 is lost. The reason for the occurrence of the state shown on the left is that the number of blocks in the instruction buffer 3 is fixed at four.

As shown in the example of FIG. 4, when a mishit occurs frequently, the instruction fetching device shifts to the 8-block mode by the mishit frequency measuring circuit 39.

FIG. 5 shows the transition of the mapping state of the instruction buffer 3 when shifting from the 4-block mode to the 8-block mode.
In the state of FIG. 5 (a), the mode shifts to the 8-block mode, and (b)
(The block load that caused the block mode to shift from 4 to 8 is a 512B load including LBL4 to block # 3). When the branch instruction of LBL4 of block # 30 is executed, the instruction counter 18
, The upper 24 bits of the address of the branch destination LBL5 are set, and the lower 7 bits are set in the word number portion (bits 3 to 5) and the word number portion (bits 6 to 8) of the instruction pointer 6. Next, the value of the instruction counter 18 is compared with the values of the comparators 22 and 2
Using 6,32,36, start address register 21,25,31,35
Then, the block number of the branch instruction word is obtained by the match output. In the case of a hit in the case of the search on the left, the output 500 of the encoder 27 is set in the upper three bits of the instruction pointer 6, and the instruction word at the branch destination is read. In the example of FIG. 5, since the branch destination LBL5 is not in the instruction buffer, a miss occurs. Since the block load target immediately before was block # 3, the round robin 12 is all 0 including bit 2.

Therefore, the replacement target is block # 00, and the output of the round robin 12 is set to the upper bits of the instruction counter 6 via the selectors 8 and 10. On the other hand, the decoder 16 receives the output of the round robin 12, and receives the strobe signal 103 of the head address register 21 corresponding to the block to be replaced.
Generate The value of the instruction counter 18 is set in the start address register 21 by the strobe signal 103. When the start address register is updated, round robin 12
Is incremented by one. Since the cache memory is notified that the mode has shifted to the 8-block mode when the 8-block mode bit is set, the block size sent by block load is 256B, which is half of the 4-block mode. I have. The load data is loaded into the block # 00 via the write data register 2, and the instruction buffer 3 is mapped as shown in FIG.

When the LBL 5 is read and executed, the upper 24 bits of the address of the branch destination LBL 1 are set in the instruction counter 18, and the lower 7 bits are set in the lower 6 bits of the instruction pointer 6. Since the block (256B) containing LBL1 has been replaced immediately before, it becomes a misset again. The value “001” (binary representation) of the round robin 12 is set in the upper 3 bits of the instruction pointer 6 again. The start address register 31 is strobed by the strobe signal 103, and the value of the instruction counter 18 is set via the selector 29. selector
29 faces the signal line 300. Subsequent sequence is L
This is the same as the block load of BL5, whereby the instruction buffer 3 is mapped as shown in FIG.

As a result, all the branch instructions appearing in the loop program of FIG. 4 are mapped on the instruction buffer 3, and no mishit occurs until the processing exits from the subsequent loop. When the process exits from the loop, in the example of FIG. 5 (d), LBL5 is the last instruction of block # 00, so that block over occurs. In the 8-block mode, if the lower 6 bits of the instruction pointer 6 indicate all “1”, the detection circuit 7 outputs a +1 select signal 200
Which causes the instruction counter via selector 17
The value of 18 is incremented by 1 by the +1 adder 23. The value of the incremented instruction counter 18 is compared with the start address registers 21, 25, 31, and 35 using the comparators 22, 26, 32, and 36, and the block number of the instruction word at the block destination is obtained from the match output. . The subsequent sequence is the same as the sequence when a branch instruction is received regardless of whether it is a hit or a mishit.

The opportunity to return from 8-block mode to 4-block mode is provided by software. That is, only when the cache clear instruction is issued by software and the cache memory is invalidated, the 8-block mode bit is reset and the mode returns to the 4-block mode. When the cache clear instruction is executed, the instruction buffer 3 also
The V bits 20, 24, 30, and 34 of each block are all reset and invalidated. Therefore, the block loading in the 4-block mode is started again from the instruction following the cache clear instruction.

Second Embodiment Next, a second embodiment according to the present invention will be described with reference to FIG.

The second embodiment differs from the first embodiment in the method of enabling the outputs of the comparators 32 and 36.

That is, the instruction counter 18 and the start address registers 31, 35
The outputs of the comparators 32 and 36 for comparing with the 8 block mode signal 70 supplied from the 8 block mode bit 70
Enabled by 600. The transition from the 4-block mode to the 8-block mode is based on software instructions. That is, the 4-block to 8-block mode conversion instruction is supported by hardware, and when the software issues the instruction on the left, the instruction fetch device functions in the 8-block mode. More specifically, when a block-to-8 block mode conversion instruction is set in the instruction register 5, the decoder 61 detects this and sets an 8-block mode bit.
Set 70. Once the 8-block mode bit is set, its output is sent to each selector or cache memory of the instruction fetch device, and thereafter, the present instruction fetch device operates in the 8-block mode.

FIG. 4 shows an example of a program in which a miss hit frequently occurs during operation in the 4-block mode. In this example, LBL1 to LB
Branch instructions are consecutive up to L5, and each branch instruction is 512B
It is distributed over five blocks of units. Therefore from LBL1
When trying to execute up to LBL4, the four blocks in 512B units shown in FIG.
Mapped to 0-3. When LBL5 is executed, the content of block # 0 (512B including LBL1) is changed to 512B including LBL5.
Is replaced by LBL1 to LBL5 form a loop of 100 times, and after executing LBL5, LBL1 must be executed again. However, since the block containing LBL1 has been replaced with the block containing LBL5 immediately before, an instruction buffer miss occurs, and this time, block # 1 (512B containing LBL2 is loaded) is replaced with a block containing LBL1.
Similarly, when any branch instruction is executed in the loop 100 times, an instruction buffer mishit occurs and block loading is performed. That is, instruction fetch is performed to the cache memory in the instruction buffer 3, and the existence of the instruction buffer 3 is lost. The reason for the occurrence of the state shown on the left is that the number of blocks in the instruction buffer 3 is fixed at four.

As in the case of the example shown in FIG. 4, in the case where frequent mishits occur, the programmer previously executes a 4-block to 8-block mode conversion instruction 100 times immediately before the loop to shift to the 8-block mode. Fig. 5 shows 8 from 4 block mode.
7 shows a transition of a mapping state of the instruction buffer 3 when shifting to the block mode. In the state shown in FIG. 5A, the mode is shifted to the 8-block mode, and the mapping state shown in FIG.
(It is assumed that LBL1 to LBL4 have already been loaded into the instruction buffer 3 before 100 loops have started). Block # 30
When the LBL4 branch instruction is executed, the upper 24 bits of the address of the branch destination LBL5 are set in the instruction counter 18, and
The lower 7 bits are set in the word number part (bits 3 to 5) and word number part (bits 6 to 8) from the instruction pointer. Next, the value of the instruction counter 18 is compared with the comparators 22, 26, 3
If the result of the left search to find the block number of the branch target instruction word based on the match output by comparing with the start address registers 21, 25, 31, and 35 using 2,36,
The output 500 of 27 is set in the upper 3 bits of the instruction pointer 6, and the instruction word at the branch destination is read. Hereinafter, it is the same as the first embodiment, and the description is omitted.

[Effects of the Invention] As described above, according to the present invention, when the number of instruction buffer misses occurring within a predetermined time exceeds a specified value, the block size of the instruction buffer is halved, By doubling the number of blocks, there is an effect of reducing the number of instruction buffer misses even in the case where branch instructions are consecutive and jumping one block after another in the instruction buffer.

Further, according to the present invention, since the number of blocks in the instruction buffer can be changed by software, even in a case where branch instructions are consecutive and jumping one block after the number of original blocks in the instruction buffer one after another, an instruction buffer miss hit can be prevented. The effect is that programming can be performed to reduce the number of times.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an instruction fetching device according to the present invention, FIG. 2 is a detailed block diagram of a mishit frequency measuring circuit shown in FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing the format of data set in the instruction pointer register, write address register, and round robin counter shown in FIG. 4. FIG. 4 shows an example in which branch instructions are consecutive and instruction buffer mishit frequently occurs. FIG. FIG. 5 is an explanatory diagram showing a transition of mapping of an instruction buffer when shifting from a 4-block mode to an 8-block mode, and FIG. 6 is a block diagram showing a second embodiment of the present invention. 1 ... Instruction buffer write address register, 2 ... Instruction buffer write data register, 3 ... Instruction buffer, 4, 8, 9, 10, 13, 17, 29, 33 ... Switching circuit, 5 ... Instruction Register, 6 ... Instruction pointer, 7 ... Detection circuit, 11, 14, 23 ...
… + 1 adder, 15,19 …… + 2 adder, 12 …… Round
Robin counter, 16, 61… Decoder, 18… Instruction counter, 20, 24, 30, 34… Instruction buffer block validity indication bit (V bit), 21, 25, 31, 35… Start address Register, 22, 26, 32, 36 Comparator, 27 Encoder, 38 Control circuit, 39 Mishit frequency measurement circuit, 60 Mishit counter, 62 Timer, 63, 70 ......
8 block mode bits, 100-103,200-205,300-30
4,400 to 404,500 to 502,600,64,65 ... signal lines.

Claims (1)

(57) [Claims] An instruction buffer (3) for holding an instruction word read from a storage device in block units, and an instruction word held in the block group corresponding to the number of blocks in the instruction buffer (3). Address holding means (21, 61, 28, 35) for holding the start address of the instruction; an instruction counter (18) for holding the upper bits of the address of the instruction word read from the instruction buffer (3); The instruction pointer (6) indicating the block number and the address in the block of the instruction word read from the buffer (3), and the case where the instruction word to be read does not exist in the instruction buffer (3) are determined for a predetermined time. An instruction fetching device having frequency number measuring means (39) for counting how many times the number of occurrences occurs in the instruction buffer, wherein when the frequency indicated by the measuring means (39) exceeds a predetermined number, the instruction buffer is provided. (3) of the block by reducing the size, instruction fetch apparatus characterized by increasing the number of blocks.