JPS5892202A - Method of forming gold indium thin film resistance element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a gold-indium thin film resistor collector suitable for use in a lead alloy superconducting integrated circuit.

Conventionally, the all-indium intermetallic compound thin film constituting this type of resistance element is formed by the general Kl1 deposition method, but the resistivity of the formed thin film depends on the thickness of the thin film and the all-indium intermetallic compound forming the thin film. 3, depending on the particle size of the compound;
This situation is shown in Figure 1 of the building! As shown in Figure 2.

That is, FIG. 1 is a graph showing the film thickness dependence of the sheet resistance value of an all-indium dimetallic compound thin film. In the figure, (1) shows the results when the substrate temperature was kept at 75°C for deposition, and (2) shows the results when the substrate temperature was also kept at room temperature. In both cases, the sheet resistance value strongly depends on the film thickness. I know what you're doing. Note that % (11).

α2) , (13) and (21) , (22)
, (23) indicate each fixed point.

On the other hand, in the 1s1 diagram, the difference in wf between (1) and (to) reflects the difference in the diameter of the thin film 0I12 based on the difference in substrate temperature during vaporization. That is, Diagram 2 is a graph showing the dependence of resistivity on grain size. In the same figure, % (11), (
B).

(13) are both when the substrate temperature is [75°C, (21),
(22) and (23) also show the results at room temperature, and each point corresponds to the same case as the point with the same number in FIG. 1, respectively. As is clear from the figure, there is a certain relationship between grain size and resistivity, and in order to realize a resistive element with good precision, it is essential to form thin IIO with uniform grain sizes. However, in the region where the -1 grain size is small, the resistivity varies greatly and is unstable due to a slight reduction in grain size.
There is a possibility that the grain size will decrease due to recrystallization.

Therefore, in order to obtain a resistive element with good characteristics, a thin film deposited by heating the substrate and having a large particle size is preferable to a thin film deposited in a chamber 8M having a fine particle size.

However, the particle size is extremely sensitive to the substrate temperature fK, and in substrate heating evaporation, it is difficult to accurately measure the temperature and control the substrate temperature. However, the disadvantages include that it takes a long time to hold the substrate temperature constant and perform the in-person process, and a correspondingly long time is required for one evaporation process.

The present invention was developed in view of the above circumstances, and its purpose is to make it possible to efficiently produce a chemically stable gold-indium thin-film resistive element with high accuracy and high reproducibility. The purpose is to provide a method for forming the material.

In order to achieve such an object, the present invention forms an all-indium intermetallic compound thin film resistor by vapor deposition at room temperature, and then performs heat treatment at at least 100°C or higher to sufficiently grow the crystal grains of the thin film resistor. This is to make the particle sizes uniform. The present invention will be explained below using actual examples.

FIG. 3 is a cross-sectional view showing a resistance element portion of a conductive integrated circuit formed using an embodiment of the present invention.

That is, using a silicon wafer 31 as a substrate which was thermally oxidized to form a silicon dioxide film 32 on its surface, a circuit was formed according to the procedure shown below.

First of all, silicon dioxide on the board! Niobium film 33 on a320
A niobium oxide film 34 is formed by vapor-depositing and anodizing the portion that will become the ground plane. Next, this is divided into a ground plane portion 33m and a pad portion 33b by etching. Thereafter, silicon monoxide J135 is formed as an interlayer insulating film by a lift-off method.

Next, the resistor 36 is formed. This K is, first of all, the above −
Silicon oxide@,,J[Resist (MuZ14' on M2S)
After coating Jt) (trade name), a resist stencil pattern is formed by subjecting it to miscellaneous light and bromobenzene ring development.

Next, gold and indium are sequentially deposited thereon at room temperature at an OH deposition rate of 1 to 2 μm/me, respectively.
After forming the alloy thin film, step 7) form a resistor 36 having a desired OA tan.

Next, this was heat-treated at 100° C. for 4 hours in a constant temperature bath filled with nitrogen at a flow rate of 5”min.

FIG. 4 shows the relationship between the heat treatment and the sheet resistance value of the formed resistance element in this case. That is, the figure shows the dependence of the sheet resistance value on the heat treatment time using the heat treatment temperature as a parameter, (1) in the figure.

(Odor, (3) are each heat treated at 100°C.
, 140℃.

The results for the case of 180°C are shown. As is clear from the figure, the higher the heat treatment temperature, the shorter the time required to obtain a constant saturated resistance value. Therefore, in order to obtain a desired resistance value in a short time, that is, to shorten the time required for the process, the higher the heat treatment temperature, the more effective it is. However, if the heat treatment temperature is too high, it not only deteriorates the superconductivity of niobium [133 but also damages the resistor 36 itself, as shown in (3) in Figure 4. The variation in resistance value increases. Conversely, 1 heat treatment 11
If & is too low, it will take too long to reach a constant saturated resistance value. For example, in the case of 100° C., heat treatment for 20 hours or more is required until K is saturated and a constant resistance value is obtained, as shown in (1) K in the figure.

Therefore, practical KFi, this heat treatment I! degree tf120℃
It is desirable that it is above. For example, at a heat treatment temperature of 140° C., the resistance value is saturated after 4 hours of O+EA treatment, as shown in (2) K in the figure. In addition, it was found that even when heat treatment was applied at a moderate temperature for 8 hours, there was no damage to the resistor body, and the variation in resistance value was small.

In this example, as a result of O heat treatment at 140°C for 4 hours as described above, the variation in resistance value between the three production lofts was suppressed to ±10s% i9, and the variation within a lot was suppressed to within ±7cm. It was possible to greatly improve the variation between lofts of ±5° and within a loft of ±15° when room temperature deposition was performed. It was also revealed that heat treatment can chemically stabilize the thin film and suppress changes in resistance over time.

After the resistor 36 has been heat-treated in this way, a dry layer 37 is formed using the same lift-off method as the resistor 36 described above, which is made of 84% by weight of lead, 121% by weight of indium, and 4% by weight of gold. Next, a lead electrode 38 made of 84% by weight of button, 12% by weight of indium, and 4% by weight of gold was wired, thereby creating a wire that constitutes a circuit as shown in Figure 3.

In this case, since the lead alloy used for the contact layer 3T and the lead electrode 38 is a low melting point metal, heat treatment of 100°C or higher is impossible, but the resistor 36 is
As mentioned above, the antibody 36 that forms the
can be heat-treated at 100°C or higher.

As explained above, according to the present invention, all indium 2
A thin film made of an interalloy compound is formed by vapor deposition at room temperature, and then heat treated at 100°C or higher to grow sufficiently large crystal grains and chemically stabilized, making it possible to create highly precise thin film resistive elements that are dust-resistant. It has the excellent effect of being able to be manufactured easily and efficiently.

[Brief explanation of the drawing]

Figure 1 is a graph showing the film thickness dependence of the sheet resistance value of an all-indium diinteralloy compound thin film, Figure 2 is a graph showing the grain size dependence of the resistivity, and Figure 3 is an example of the present invention. Cross-sectional view showing the resistance element part of a superconducting integrated circuit to which J
The Id diagram is a graph showing the heat treatment time dependence of the sheet resistance value of the gold-indium thin film resistance element formed according to the present invention. 31... silicon wafer, 32...- silicon oxide purple film, 33... niobium film, 34... niobium oxide film, 35...- silicon oxide film, 36... ...Resistor, 37...Contact layer, 38...Lead electrode. Patent applicant: Masaki Yamakawa, agent of Nippon Telegraph and Telephone Public Corporation Figure 1: % 4 (nm) Figure 2 Figure 3

Claims (1)

[Claims] Lead alloy superconducting integrated circuit manufacturing engineer 1! In this step, there is a step of forming a 7th to 7th period of baton on the substrate, and a process of forming a gold-indium alloy on the second baton. ! ! A process of forming a thin film resistor having a desired pattern by depositing it to a desired thickness with 7 to 7; 1. A method for forming a gold-indium thin film resistive element, comprising the step of heat-treating a resistor at at least 4100° C. or higher in an inert gas atmosphere.