JPS5885569A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the growing speed of an insulating film on a gate electrode by forming an insulating film after removing the part, to which ions of the gate electrode is implanted. CONSTITUTION:An N type active layer 3 is formed on a semi-insulating GaAs substrate 1, and a conductor film 4 made of high melting point metal silicide is then formed. A mask 5 is formed, a gate electrode 6 and wiring pattern 7 of the first layer are formed. After the mask 5 is removed, the etching is again performed, thereby shaping the sectional shape. With the electrode 6 and a mask 8 as masks a source high density region 9 and a drain high density region 10 are formed, the mask 8 is removed, the electrode 6 and the pattern 7 are etched, and electodes 11, 12 are then formed. An interlayer insulating film 13 is formed, the conductor film of the second layer is formed, the prescribed patterning is performed, thereby obtaining the wiring pattern 16 of the second layer.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to processing of a gate electrode of a semiconductor device including a field effect transistor in which ions are implanted using the gate electrode as a mask.

(2) Background of the technology In semiconductor devices, especially integrated circuits, the wiring pattern that connects all the 'electrodes or lead-out' electrodes of transistors, diodes, etc. is formed from the same conductive film as some of the electrodes, or These − wiring are other! ! It is often necessary to intersect the conductor film l[', but in this case, the electrode wiring pattern is usually formed using two or more layers of conductive films.

That is, first, the first layer of the conductor film is subjected to the required patterning to form the first layer of the electrode wiring pattern, and then, for example, silicon dioxide (Sin2) and silicon nitride (Sis) are deposited on top of the first layer of the electrode wiring pattern.
After forming an insulating film made of N+), etc., a required opening is formed in this, a second layer of conductive film is provided, and the required patterning is performed to form the second layer of the electrode wiring pattern. An electrode wiring pattern is formed in which intersecting wiring lines are insulated by the insulating film and required connections are made through openings in the insulating film.

(3) Prior art and problems When the electrode wiring patterns intersect as described above, the first electrode wiring causes a step in the insulating film formed on top of it, and the second layer wiring pattern generally Since the shape crosses this step, the second layer wiring pattern is likely to be disconnected at the edge of the step. As a countermeasure against this disconnection, a method called the Braun-American resin film coating method has been implemented, in which the irregularities are buried with an insulating film and a long high temperature heat treatment is applied to eliminate the steps, thereby making the shape clear.

These already known methods involving high-temperature heat treatment can be easily utilized when the semiconductor material is silicon (Si), which can relatively withstand high-temperature heat treatment, but? 1j In the manufacturing process of semiconductor devices using compound semicircular materials such as gallium ablation (GaAs), high-temperature heat treatment at temperatures of about 450°C or higher is required for long periods of time, which may cause deterioration of crystal properties.
Since it is very difficult to apply koji, a new manufacturing method is needed to replace the above method.

However, for example, in the process of manufacturing an integrated circuit called an electric field infant transistor using a GaAs semiconductor, the impurity implanted as a gate and body mask is St.
5-inch diaphragm film installed on the polar wiring pattern
In the case of form 2, when there is an excess of St resulting from ion implantation on the gate electrode, the growth rate of 5iOz on that surface is faster than normal, the step is enlarged, and the Because the shoulder of the step bulges, the second layer conductor film may not grow sufficiently at this step, or it may not be possible to perform patterning, which may result in problems such as the reliability of the second layer wiring pattern. significantly lowers the level of

(4) Purpose of the Invention The present invention provides a method for manufacturing a semiconductor device including a field effect transistor in which all ion implantation is performed using the gate electrode as a mask, in which the growth rate of an insulating film on the gate electrode after the ion implantation is reduced. purpose.

(5) Structure of the Invention The object of the present invention is achieved by removing the ion-implanted portion of the cathode electrode.

(6)% EXAMPLES The present invention will now be described in detail by way of examples with reference to the first page.

=3= Figs. 1 to 9 show a first embodiment of the present invention in a GaAs integrated circuit, Figs. 10 to 14 show a second embodiment partially modified from the first embodiment, and Figs. Figures 15 to 17 are diagrams showing a third embodiment that is a partial modification of the second embodiment, and the same target portions are shown in each figure.

As shown in FIG. 1, on a semi-insulating GaAs-M-machine 1,
5i02 was provided with a strip 2, and after selectively implanting ions such as Si, heat treatment was performed for 15 minutes in an oxygen-free atmosphere H1 at a temperature of 700°C to 900°C. A sexual layer 3 is formed.

Next, as shown in FIG. 2, the mask 2 used for the selective ion implantation is removed, and a gate electrode and a low melting point metal silicide, such as titanium/tungsten, which will be the first layer wiring material, are deposited on the surface of the substrate 10. The conductor film 4 made of silicide has a thickness of 600 mm.
It is formed by a CVD method or the like to a thickness of about nm.

Next, as shown in FIG. 3, a mask 5 for patterning the conductor film 4 is used.

4- Next, as shown in FIG. 4, the conductive film 4 is etched by using an elachantra containing fluorine-based hydrochloride substituted with carbon tetrafluoride (CF4) or by active ion etching. , a gate electrode 6 and a first layer wiring pattern 7 are formed.

Self-alignment (sea alignment) method for implanting impurities to form source and drain regions on electrodes as a mask
In this case, it is ideal that the side end surfaces of the gate electrode be formed perpendicularly to the substrate surface by 1 m.

However, the cross section of the actually obtained Kate' electrode has a narrow flat top even when dry etching is used, which is better than wet etching. In the first row of eyebrows where impurity implantation was performed using a gate with such a cross-sectional shape as a mask, an incomplete mask effect in which a portion of the impurity was transmitted was formed continuously in the intended impurity implantation region.
The source high-density region and the drain high-density region are not defined clearly, resulting in a reduction in the gate withstand voltage after the semiconductor device is completed.

As a first means of dealing with this problem, the gas pressure conditions for etching the etched U 111 surface are selected as low as possible.

Next, as shown in FIG. 5, after removing the mask 5, the gate electrode 6 and the wiring pattern 7 are etched to shape their cross-sectional shape. This shaping of the cross-sectional shape removes or reduces the incomplete area of the mask effect at the foot of the side end face of the gate electrode 6, and also removes or reduces the area where the mask effect is incomplete at the bottom of the side end face of the gate electrode 6. This method removes sharp edges or corners to create a rounded and smooth shape.

This etching was carried out by reactive ion etching in the same way as the etching for the previous pattern formation, but the gas pressure conditions etc. were adjusted as necessary.

Next, as shown in FIG. 6, a high bE degree 1 degree resistance region for the source and drain is formed. In other words, a resist is applied, patterning is performed to provide an opening in the area where ions are to be implanted, and a mask 8 is formed. A gate electrode 6 is formed on the
Then, using the mask 8 as a mask, selective ion implantation of Si or the like is performed, and the same heat treatment as described above is performed, so that the carrier-concentrated MC is on the surface with a source high concentration region 9 and a drain high concentration of about 3×IQI7 (m−3). A concentrated region 10 is formed.

Next, as shown in FIG. 7, after removing the mask 8, the gate electrode 6 and the wiring pattern 7 are etched, and then the electrodes @L11 and 12 which are in ohmic contact with the high concentration source region 9 and the drain 4m region 10 are etched. Form.

The etching applied to the gate electrode &6 after this ion implantation is as follows:
A feature of the present invention is to remove the portion where excess St resulting from the ion implantation is present. That is,
When an insulating film is provided on the gate electrode 6 using 5 in 2 water by CVD method, when excess St exists on the gate electrode 6, the growth rate of Sin on the surface is faster than in the normal case. This prevents the shoulder of the step from bulging as the step becomes larger and the step becomes larger.

Furthermore, this etching has the effect of removing sharp edges or corners of the etched portion formed by the upper end surface and both side end surfaces of the gate electrode 6, and giving it a rounded, smooth shape. Especially like this example? When etching a single layer wiring pattern 7 in the same way, this wiring pattern 7 is etched.
Ruin electrode 12 medium, for example gold, kermanium,
Consists of money.

Next, as shown in FIG. 8, Hatoma Zetsumozoku 13 is established. This I Soma loquat family 13 is made of, for example, a 5-in2 film made by CVD method and has a thickness of about 600 nm.
The edges are rounded and shaped into a smooth shape,
Since the portion of the gate electrode 6 where oil-permeable Si is present is removed, this IsoIi:lI insulating crotch 13 can be removed even in the step part on the gate electrode 6 or 8- or the self-e line pattern 7. It becomes a smooth shape.

Next, as shown in FIG. 9, after forming required openings, e.g. 14 and 15, in the interlayer insulating film 13 by phosphorography, a second layer of conductive film is formed and the required patterning is performed. Then, a second layer wiring pattern 16 is obtained. The formation of this second) pattern 16 can be carried out in accordance with the method of forming the second-increase winning pattern 7 described with reference to FIG. Furthermore, the wiring pattern 16 of the second layer, such as providing a second layer wiring pattern! If p-type is required, the etching described with reference to FIG. 5 is carried out after the second layer wiring pattern 16 is removed from the mask.

A second embodiment, which is a partial modification of the above-described embodiment, will be explained with reference to FIGS. 10 to 14.

After the formation of the gate electrode 6 and the paddy distribution pattern 7 of the first layer described with reference to FIG. 4, the mask 5 of the gate lJ At least a portion of the mask 5 of pattern 7 is left over. With respect to the wafer in this state, as shown in FIG. 10, the cross-sectional shape of the gate electrode 6 is shaped in the same manner as in the first embodiment. At this time, the wiring pattern 7 is hardly etched.

Next, as shown in FIG. 11, after applying a resist and applying lead to remove ions and buttering to form an opening in the surrounding area to form a mask 8i, the gate electrodes 6 and i5 and the mask 8 are used as a mask. , perform selective ion implantation of Si, etc.
After heat treatment with previous i [:, 1 carrier daughter degree is shown ■
As a result, a source roughness region 9 and a drain roughness region 10 of about 3×10 m11 are formed.

Next, as shown in FIG. 12, after removing the ion implantation mask 8 and the etching mask 5 of the wiring pattern 7,
Etching is performed on the substrate and wiring pattern 7 to form a source electrode 11 and a drain electrode 12 thereon.

The effect of the etching performed here is that for the gate electrode 6, it is similar to that of the first embodiment; it removes the portion where excess Si, which was caused by the residue of the coordination ion implantation, is present, and then The objective is to suppress the growth of successive layers of the 5in2 film formed in the 5in2 film, and to make the edges of the film into a rounded and ragged shape.

On the other hand, the pattern 7 in the arrangement 14 has the effect of making its edges rounded and smooth. In this example, there is almost no decrease in the B+ area of the wiring pattern 7 due to the etching process explained with reference to FIG. A wiring pattern 7 whose area is inclined at the side end surface is obtained.

Next, as shown in FIGS. 13 and 14, the insulating film 13. A second layer wiring pattern 16 is formed.

A third embodiment, which is a partial modification of the second embodiment, will be described with reference to FIGS. 15 to 17.

Hatake i who explained the second embodiment with reference to FIG.
Condensation source (ii'+ region 9 and drain high concentration region 10
After the formation of ion 7 king's mask 8 as shown in FIG.
The remaining etching mask 5 of the self-assembled pattern 7 is used to etch the gate electrode 6 and the wiring pattern 7, and then the base electrode 11 and the drain electrode 12 are formed.

The effect of the etching performed here is the same as in the above-mentioned embodiment for the gate electrode 6, but the etching after ion implantation in this embodiment is such that the upper end surface of the wiring pattern 7 is coated with pigment against the substrate 1. This is done by setting the conditions before the gas pressure so that the edge part becomes an obtuse angle. Wiring pattern 7 like this
By performing the etching while leaving the mask 5,
The pattern after etching is larger than that of the second embodiment, and the increase in wiring resistance is suppressed.
- Remove the layer 5, shape the PR film 13, and form the second layer wiring pattern 16.

(7) Effects of the Invention As explained above, the present invention provides that the ions of the gate electrode are implanted in the manufacturing process of a semi-integrated device including a field effect transistor which performs ion implantation as a gate electrode or mask. By forming an insulating film with the portion removed, the gradual growth of the insulating film on the gate electrode can be suppressed, and the noise on the substrate can be equivalent to 15 minutes (7〈 is less than that, and It has the effect of smoothing the steps that occur in the insulating film and eliminating failures such as disconnections in the second layer of the electrode wiring pattern formed on the insulating film, and has the effect of eliminating problems such as disconnections at high temperatures unlike the conventional technology for the same purpose. It has the excellent feature of not requiring heat treatment.

[Brief explanation of the drawing]

FIGS. 1 to 9 are cross-sectional views showing one embodiment of the present invention, FIGS. 10 to 141 are embodiments of 11u, and FIGS. It is a diagram. Sex layer, 4th layer, 5th gemaster, 6th gecate army, etc. 7trl arrangement, solid pattern, 8 is a mask, 9 is a source high concentration region, 10 is a drain high concentration region, 11 is a source type rod, 12 is a drain electrode, a pole, 13 is an insulating film, 14 is an opening,
15 shows the wiring pattern, and 16 shows the wiring pattern of the second layer. 15-295- Procedural amendment (voluntary) 1. Display of the case 1983 Patent Application No. 183396 3 Person making the amendment Relationship with the case Patent applicant address 1-71-Tanaka 1015 (522), Nakahara-ku, Yozaki City, Kanagawa Prefecture Name Fujitsu Corporation 4, Agent Address: 1015-1-Odanaka, Nakahara-ku, Kawasaki City, Nagawa Prefecture, 711 Kawasaki (0
44) 777-1111 (Extension 2630) 5 Amendment Order No. 11 A None Showa Year Month 1゜6 Amended and Increased Number of Items Ill-D Light None No. 5 of Particulars
On the 17th line of the page, the phrase "The grade and name are formed by CVD method, etc." is corrected to "It is formed by sputtering method, VD method, etc.".

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device including a one field effect transistor in which ions are implanted using a gate electrode as a mask, the method comprising removing a portion of the gate electrode into which the ions have been implanted.