JPS63169765A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having an LDD structure without danger of causing device characteristics based on the irregularity of a frame size to vary in an extremely simple step of merely utilizing a side etching at the time of forming a gate insulating film, a gate electrode. CONSTITUTION:A thermal oxide film is first formed on the main surface of a silicon semiconductor substrate 1, a polycrystalline silicon film containing phosphorus in high concentration is deposited, a resist pattern 7 for forming a gate electrode is patterned by a photoresist working technique, sidewisely etched to desired degree by plasma etching, and a gate insulating film 2 and a gate electrode 3 are selectively formed with an HF etchant. A desired overetch is performed after so-called just etching in the step of etching the film 2 and the electrode 3, a desired undercutting amount 9 is set by controlling the sidewisely etching amount, thereby obtaining an object device configuration, i.e., a desired LDD structure.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device, and more particularly, to
n) relates to a method of forming an impurity region in a semiconductor device having a structure.

[Conventional technology]

FIGS. 2(a) and 2(a) show an outline of a conventional method for forming the LI structure in this type of semiconductor device.
The steps are shown in order.

That is, in the conventional method shown in FIG. 2, a thermal oxide film is first formed on the main surface of the silicon semiconductor substrate 1, and a polycrystalline silicon film containing a high concentration of phosphorus is formed on the main surface of the silicon semiconductor substrate 1. After depositing, each of these films is sequentially and selectively shaped and removed using photoresist processing technology to form gate insulating film 2. By forming a gate electrode 3 and using this gate electrode 3 as a mask, ion-implanting an impurity (for example, phosphorus in this case) and heat treatment, a relatively shallow impurity region, in this case, is formed. Low concentration diffusion layer regions 4a and 4b which become source or drain regions
((a) in the same figure).

Next, after forming each of the low concentration diffusion M9R regions 4a and 4b, high temperature oxidation of 1% (High Tes+pe) is applied thereon.
(hereinafter referred to as ITO) 5 is grown over the entire surface (FIG. 2(b)).

Furthermore, by etching the entire surface of the above-mentioned ITO 5 using an anisotropic etching means, "wax portions" 5a, 5b of the HTO 5 at both ends of the gate electrode 3 are etched.
Then, successively, both of these hollow parts 5a,
Using the gate electrode 3 containing 5b as a mask, impurity (in this case, for example, arsenic) is ion-implanted and heat-treated again, so that it overlaps the respective low concentration diffusion layer regions 4a and 4b. Then, an impurity region, in this case a highly concentrated diffusion layer region 8a Jb, is formed deeper than this (see FIG.
)) In this way, the desired device configuration, that is, the desired LDD structure is obtained.

[Problem that the invention seeks to solve]

However, when forming an LDD structure using the conventional method described above, extra steps such as depositing the HTO5 and leaving hollow portions 5a and 5b using the anisotropic etching are increased, and the thickness of the HTO5 film is increased. For example, variations in device characteristics due to variations in the dimensions of the cracks 5a, 5b due to peeling of the cracks 5a, 5b, and non-uniformity in the dimensions of the cracks 5a, 5b due to instability of the etching rate in anisotropic etching
There have been various undesirable problems, such as the habit of causing fluctuations in the threshold voltage vth due to short channel effects.

This invention was made to solve these conventional problems, and its purpose is to improve HTO
It has an LDD structure that does not require extra steps such as deposition and anisotropic etching, and there is no risk of variations in device characteristics due to non-uniformity of the cavity dimensions.
An object of the present invention is to provide a method for manufacturing this type of semiconductor device.

[Means for solving problems]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes, after patterning a resist pattern in a gate step, side-etching a gate insulating film and a gate electrode by a predetermined undercut amount with respect to this resist pattern. Then, using the resist pattern as a mask, a first impurity is ion-implanted at a high concentration onto the main surface of the semiconductor substrate to form a first impurity region, and further,
Thereafter, after removing the resist pattern, using the gate electrode as a mask, a second impurity is doped on the main surface of the semiconductor substrate including the first impurity region at a lower concentration and shallower than the first impurity region. A source or drain region made of this second impurity region is formed by ion implantation.

[For production]

That is, in the method of the present invention, a double diffusion region of low concentration and high concentration can be formed by an extremely simple process that utilizes side etching when forming the gate insulating film and the gate electrode.

〔Example〕

Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIG.

1(a) to 1(c) are cross-sectional views showing the outline of the method for forming an LDD structure in a semiconductor device in a semiconductor device to which the method of this embodiment is applied. 2, the same reference numerals as in the conventional method shown in FIG. 2 indicate the same or corresponding parts.

Here, also in the embodiment method shown in FIG. After the film is deposited, a resist pattern 7 for forming a gate electrode is patterned using a photoresist processing technique, and side etching is performed to a desired degree using plasma etching. ．． Then, using the resist pattern 7 as a mask, relatively deep high-concentration ion implantation regions 8a and 8b are formed by ion implantation of impurities (FIG. 4(a)).

Subsequently, the resist pattern 7 is removed, and then a heat treatment process is performed to form first impurity regions, here high concentration diffusion layer regions 8a and 8b (FIG. 4(b)).

After forming the high concentration diffusion layer regions 8a and 8b, using the gate electrode 3 as a mask, the high concentration diffusion layer is applied to the portion including the high concentration diffusion layer regions 8a and 8b, which are the first impurity regions. A second impurity is ion-implanted at a lower concentration and shallower than the regions 11a and 8b, and after a heat treatment process,
a source or drain region consisting of a second impurity region;
In this process, low concentration diffusion layer regions 4a and 4b are formed (FIG. 3(C)).

In this case, the gate insulating film 2.
In the etching process of the gate electrode 3, a desired undercut amount 9 can be set by performing a desired overetch after so-called just etching and controlling the amount of side etching. composition.

In other words, the desired LDD structure can be obtained.

In the above embodiment method, a single layer polycrystalline silicon film containing phosphorus at a high concentration was used as the gate electrode 3, but other materials such as a single layer of a high melting point metal film or a silicide film thereof, Generally called polycide. Two layers of molybdenum silicide (MoSi) H and polycrystalline silicon (I7) film, tungsten silicide (WS i) film and polycrystalline silicon (
Electrode films that can be side-etched by plasma etching can be used, such as a double layer with Polr Si) H or a double layer with another high melting point metal silicide film and a polycrystalline silicon (Poly Si) film. You can get the desired action and effect.

〔Effect of the invention〕

As described in detail above, when using the method of the present invention, side etching is used when forming the gate insulating film and the gate electrode to form double diffusion regions of low concentration and high concentration. Unlike the case of the example method, such as the formation of HTO.

Wapping of HTO can omit extra steps such as etching, making it easy to obtain the LtllD structure with extremely simple means, and even with miniaturization, short channel effects are less likely to occur, and high breakdown voltage is possible. It has excellent features such as:

[Brief explanation of the drawing]

FIGS. 1(a) to 1(c) are cross-sectional views showing the outline of a method for forming an LDD structure in a semiconductor device to which an embodiment of the present invention is applied, sequentially showing the process order, and FIG. ) to c) are sectional views illustrating the outline of a method for forming an LDD structure in a semiconductor device according to the conventional example as above, sequentially showing the process order. 1...◆Silicon semiconductor substrate, 2...gate insulating film, 3...gate electrode, 4a, 4b...low concentration diffusion layer region (second impurity region), 13a, 8b.
...High concentration diffusion layer region (first impurity region), 7...
...Resist pattern, 9...Undercut amount. Agent Masuo Oiwa Figure 1 2: Ke'-) Tht Book 1 Ambiguous 3 Nige-) 1 Sacrifice 6a, 6b: Island-like dispersion 4a, 4b: Mr. I) On the shop, 1a dispersion 414 Figure 2 Procedural amendment (voluntary) 2. Name of the invention: Method for manufacturing semiconductor devices 3. Relationship with the person making the amendment Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo. Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent address 2-2-3-6 Marunouchi, Chiyoda-ku, Tokyo
, Details of the amendment (1) Amend "intended" on page 4, line 3 of the specification to "desired" (2) Change rMosfJ on page 8, line 13 of the same document to rMosi2J
and correct it. (3) Correct "WSl" in line 14 of the same page of the same book to rwstzJ. that's all

Claims (3)

[Claims] (1) First, after patterning a resist pattern in the gate process, the gate insulating film and gate electrode are side-etched by a predetermined amount of undercut with respect to this resist pattern, and then, using the resist pattern as a mask, the semiconductor substrate is etched. A first impurity is ion-implanted at a high concentration onto the main surface of the main surface to form a first impurity region, and then, after removing the resist pattern, the gate electrode is used as a mask to form a first impurity region. A second impurity is ion-implanted onto the main surface of the semiconductor substrate including the first impurity region at a lower concentration and shallower than the first impurity region to form a source or drain region made of the second impurity region. A method of manufacturing a semiconductor device, characterized by: (2) The method of manufacturing a semiconductor device according to claim 1, wherein the gate electrode is a polycrystalline silicon film into which impurities are ion-implanted or doped. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the gate electrode is a high melting point metal film, a high melting point metal silicide film, or a polycide film.