JPS5879768A - Schottky gate field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce resistance between a gate and a source, and to improve a high-frequency characteristic by making the thickness of an operating layer in the vicinity of a source electrode and a drain thicker than the thickness of the operating layer just under a gate electrode. CONSTITUTION:The N type operating layer 22, the source electrode 23, a drain electrode 24, the high heat-resistant Schottky gate electrode 25 and an insulating compound film 26 are formed onto a semi-insulating semiconductor substrate 21 made of GaAs, etc. The surface of the operating layer 22 is flattened, and the thickness of the operating layer 22'' of the source-drain is made thicker than the thickness of the operating layer 22' just under the gate. The operating layer 22 is manufactured in such a manner that Si<+> ions are implanted in the surface of the substrate 21 and an operating layer with uniform thickness is shaped, the gate electrode 25 is formed, and the thick operating layer is molded through the second ion implantation while using the gate electrode 25 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Schottky gate field effect transistor that has good microwave characteristics and is easy to manufacture.

The present invention is not limited in any way to materials (
The present invention can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as , Si, and compound semiconductors, but the following explanation will be given using GaAs as an example of compound semiconductors that have the advantage of high operating speed as a semiconductor material.

The general structure of a conventional Schottky gate field effect transistor is GaA, as illustrated in the cross-sectional view of FIG.
After forming an n-type active layer IB with a uniform thickness on the surface of the semi-insulating semiconductor substrate 11 by epitaxial growth or ion implantation, the source electrode 18 is formed by depositing metal on the surface of this active layer. , train electrode 14
and a Schottky gate electrode 15 are formed.

In such a conventional Schottky gate field effect transistor, if the gate-source resistance is large,
It is known that the microwave characteristics, particularly the noise characteristics, of this transistor deteriorate. To improve microwave characteristics, it is necessary to lower the gate-source resistance.
To achieve this objective, it is necessary to increase the carrier concentration in the active layer 12 or to increase the thickness of the active layer, but either method causes the problem that the pinch-off voltage becomes excessive. Further, when the carrier concentration is increased, another problem arises in that the breakdown voltage of the gate decreases.

In order to solve this problem, as illustrated in FIG.
A structure has been proposed in which the thickness of the active layer 12' near the source electrode is increased while maintaining the thickness of the active layer 12' at a desired value. In this structure, first, an active layer with a uniform thickness corresponding to the thickness directly under the source electrode 18 and drain electrode 14 is formed, and then only the portion 12' that should be directly under the gate electrode 15 is thinned by etching or the like. Each electric wire 18, 14 and 15 is formed.

However, in such a structure, not only is it difficult to perform fine photolithography for electrode formation because the surface of the active layer is not flat, but also the yield is low because extremely strict precision is required to control the etching of the active layer. There is a drawback that it becomes.

That is, in order to improve the high frequency characteristics of the MESFET, it is necessary to reduce the gate length as much as possible, which requires extremely fine precision machining in device fabrication. However, in the conventional manufacturing method, when the pattern of the gate electrode 15 is formed in a resist, a step due to the source electrode 18 and the drain electrode 14 is created in the vicinity of the gate pattern in addition to the step in the operating region 12. Due to the existence of these particles, the resolution of the photoresist pattern is lower than that on a flat surface, making it difficult to reliably form a gate pattern as short as about 1 μm. In particular, in compound semiconductors such as GaAs, it is common practice to perform alloy treatment on the source electrode 8 and drain electrode 4 before forming the gate electrode 5 in order to reduce their contact resistance.
If alloying is performed at a sufficiently high temperature and for a long time in order to reduce the contact resistance sufficiently, the source and drain electrode metals will agglomerate, resulting in extremely large steps, which will also reduce the resolution of the gate photoresist pattern. It's causing it to get worse.

Further, the gate electrode 5 is replaced with the source electrode 8 which has already been formed.
It is necessary to form it between the electrode 4 and the drain electrode 4 with a positional accuracy of ±0.2 μm or less. Furthermore, the distance between the source electrode 3 and the gate electrode 50 is in the electrical characteristics of the MESFET and directly affects the parasitic resistance and capacitance between the source and gate.
The distance between the two electrodes needs to be as small as possible and controlled with high precision, and the above-mentioned positional accuracy is also required in terms of the distance between the electrodes. However, it is extremely difficult to form such fine patterns with high precision using conventional techniques, and therefore there is a problem in that the manufacturing yield is extremely low.

The present invention has been made in view of the above-mentioned conventional problems, and its object is to provide a Schottky gate field effect transistor with good microwave characteristics and good yield.

The details of the present invention will be explained below with reference to Examples.

FIG. 8(5) and FIG. 8(B) are cross-sectional views of a Schottky gate field effect transistor according to an embodiment of the present invention1)
, 21 is a semi-insulating semiconductor substrate such as GaAs, 22
28 is an n-type active layer, 28 is a source electrode, 24 is a do L'47 electrode, 25 is a highly heat-resistant Schottky gate electrode, and 26 is an insulating compound film consisting of the gate electrode itself. The field effect transistor of the present invention is shown in FIG. 3 (4) and FIG. 8 (g)).
As illustrated in FIG.
The active layer 22'' between the source and drain is formed using the gate electrode 25 as a mask, and the source and drain electrodes are formed via an insulating compound film 26, which is a so-called self-contained structure. An alignment method is used. Therefore, the positional relationship between the source electrode IQ, the drain electrode 24, the gate electrode 25, and the second active layer portion 22' is automatically determined. Therefore, according to the present invention, the manufacturing process can be It has advantages such as being simple, improving yield, and enabling fine processing.

FIG. 4 is a cross-sectional view showing an example of a method for manufacturing the field effect transistor shown in FIG. 3(5).

First, as shown in FIG. 4(4), ions of Jll, 51+ are implanted into the surface of a GaAs semi-insulating substrate 21 to form an active layer 22' having a uniform thickness. The thickness and carrier concentration of this active layer are selected to achieve the desired pinch-off voltage. For example, in order to achieve a pinch-off voltage of 0.2V, the carrier concentration IQ"m-8 or so and the thickness 0.
．． It is necessary to form an active layer of about 1 μm, and the conditions for ion implantation are: implantation energy: 120KeV, implantation amount: 2×10” dose/cIn2 (however, the activation rate is 100%).
shall be. ) is selected. The theoretical value of the carrier concentration distribution obtained under these conditions is shown by the dashed-dotted line 81 in Figure 6.
Indicated by

As illustrated in No. 4N0), the operating layer 22 has a uniform thickness.
After forming ', a gate electrode 25 made of a highly heat-resistant metal is formed thereon. A second ion implantation is performed using this gate electrode 25 as a mask to form a new active layer 22' in the unmasked area. The conditions for the second ion implantation are that the implantation energy is higher than the first one in order to implant deeper than the first surface, and the implantation amount is such that the final peak carrier concentration is excessive compared to the first peak carrier concentration. The value is selected such that the

This is to prevent dielectric breakdown from occurring due to the voltage applied to the gate. As an example of such a forward input condition, the theoretical value of the carrier density distribution when the implantation energy is selected to be 400 KeV1 and the injection amount is selected to a value of 3.9xH)lit dose/Cm'' is illustrated by a dotted line 82 in FIG. The concentration of the unmasked portion 22'' in the active layer 22 is 2 times the concentration of the first ion implantation.
This value is obtained by adding the concentration due to the second ion implantation, and its distribution is illustrated by the solid line 88 in FIG.

As is clear from FIG. 6, the total number of carriers in the active layer 22' near the source electrode 28 is about eight times larger than the total number of carriers in the active layer 22' directly under the gate electrode 25. The interlayer resistance is reduced to about one-eighth compared to when the active layer 22' is formed uniformly. on the other hand,
Since the maximum carrier concentration in the active layer 22'' has increased by only about 13% compared to the value in the active layer 22', the associated increase in reverse breakdown voltage and gate capacitance of the gate is extremely small. Stay in quantity.

In this embodiment, a Ti--W alloy was used as the gate electrode 25. A Ti-W film with a thickness of 1.2 μm was formed using a sputtering method, and a resist pattern formed on the film was masked to remove carbon.
The gate electrode 25 shown in FIG. 4(B) was obtained by plasma etching with F410s (5%) mixed gas.

In this way, the second electrode is implanted by ion implantation using the same electrode as a mask.
After forming the active layer 22', the implanted elements are activated by annealing.

Next, as illustrated in FIG. 4(C), the gate electrode 25
An insulating compound film 26 whose base material is the gate metal itself is formed on the entire surface of the gate metal. In this example, the gate electrode itself was insulated by plasma anodic oxidation, and an insulating compound film having a thickness of goooX was formed.

At this time, the semiconductor substrate itself is also oxidized, but it is easy to selectively remove the GaAs oxide film with respect to the insulating compound film 26 on the gate electrode.

Subsequently, as shown in FIG. 4), an ohmic metal film is formed on the active layer 22 by vacuum evaporation or the like, and a source electrode 28 and a drain electrode 24 are formed. This completes the manufacturing process.

Next, another example of the method for manufacturing the field effect transistor shown in FIG. 3 [F]) is shown in FIG.

First, the gate electrode 25 is formed as shown in FIGS. ,
Activate the implanted element. In one embodiment, 1500X SiOWK formed by vacuum evaporation was used. Here, these two
As for the material 7, any insulating compound film that does not cause unnecessary reactions with the semiconductor substrate 22 and the gate electrode 25 during annealing satisfies the requirements of the present invention, and there are no restrictions on the material or formation method. It is not something that can be done.

After this, when plasma anodic oxidation is performed as illustrated in Figure 5), an inorganic compound is formed! Plasma oxidation progresses only on both sides of the gate electrode 25 that are not covered with I27, and an insulating compound layer 2 made of itself is formed on both sides of the gate electrode 25.
6 is formed.

Next, as illustrated in FIG. 5(C), the inorganic compound film 27
After removing, an ohmic metal is deposited by vacuum evaporation or the like to form the source electrode 28 and drain electrode 24, and the manufacturing process is completed.

After ion-implanting the second active layer 22'' in the step shown in FIG. 4(B), it is also possible to form a high concentration layer of about 101s/α8 only in the vicinity of the surface, so-called n+ layer. It should be added that this is an effective means for improving the ohmic characteristics of electrodes and drain electrodes.

Further, the requirements of the present invention are satisfied if the gate electrode 25 serves as a mask for ion implantation and thermal diffusion, and is resistant to high temperature processes such as annealing.

Therefore, the material is not limited to the Ti-W alloy, but any material with excellent heat resistance that does not cause unnecessary reactions with semiconductors even at temperatures of about 800°C may be used.In addition, Ta,
Metals such as Nb and VtMo are applicable. The surface insulation of the gate electrode is not limited to the plasma oxidation shown in this example, but it is also possible to form an oxide film by anodic oxidation, thermal oxidation, etc., or to form a nitride film by plasma nitridation. .

Although the example in which the field effect transistor having the structure illustrated in FIGS. 8(4) and 8(B) is manufactured by the ion implantation method has been described above, it can also be manufactured by the thermal diffusion method. That is, first, by bringing a dopant with a small diffusion constant into contact with the substrate surface and performing thermal diffusion, a shallow diffusion layer corresponding to the active layer 22' of FIG. 4 is formed. Next, using the mask pattern 27 as a shield, a dopant with a large diffusion constant is brought into contact with a region other than the region directly under the gate and thermally diffused, thereby forming the active layer 22 of FIG. 4(6).
A hybrid diffusion layer consisting of a shallow diffusion layer and a deep diffusion layer corresponding to ' is formed, and finally the electrodes 28, 24 and 25 are formed according to the previous embodiment. Alternatively, a dopant with a small diffusion constant is deposited in the gate region, a dopant with a large diffusion constant is deposited between the gate and the source, and then simultaneous thermal diffusion is performed in each region.
The structures shown in FIG. 4 and FIG. 8B may also be realized.

The shorter the length of the active layer 22' in FIGS. 8(4) and 8(B), the smaller the series resistance between the gate and the source becomes, which is advantageous in terms of characteristics. However, shortening this length is necessary for the mask 27 in the manufacturing method illustrated in FIG.
It is only limited by the limitations of microfabrication technology, such as the difficulty of reducing the length of the microfabrication technology.

Next, to explain the relationship between the length of the active layer 22' and the length of the gate electrode 25, in the normally-on type where the active layer 22' is relatively thick, the length of the active layer 22' is the same as that of the gate electrode 25.
Practically sufficient characteristics can be obtained even if the length is slightly longer than .

This is because the active layer 22' is relatively thick, so the thickness of the depletion layer that spreads from the surface into the inside of the device does not account for the entire thickness of the active layer 22'. This is because the problem of extremely increasing source-to-source resistance does not occur. On the other hand, in a normally-off type in which the depletion layer thickness from the surface occupies the entire layer thickness of the active layer 22', the active layer 22' is If the length is longer than the length of the electrode 25, a depletion layer is formed in the entire thickness direction in the portion of the active layer 22' excluding the area directly below the gate, and as a result, the gate-source resistance becomes significantly large. In extreme cases the problem arises that the current is completely blocked.

Therefore, in the normally-off type, the length of the gate electrode 25 must be longer than the operating layer 22'. However, the overlapping portion of the gate electrode 25 and the active layer 22', that is, the portion of the gate electrode 25 that is longer than the active layer 22', simply increases the capacitance and does not have an effective effect. Therefore, it is effective to shorten this excessive portion as much as possible in order to increase the operating speed of the element. That is, ideally, as illustrated in FIG. 8 and FIG. 8(B), it is effective to form the length of the gate electrode 25 and the length of the active layer 22' to be equal, especially in the normally-off type. It is a means.

In the present invention, the length of the gate electrode 25 is made equal to the length of the gate electrode 25 by the self-line, and is formed at the same position, so that the normally-off characteristics are significantly improved.

In the above embodiments, GaAs is used as the semiconductor crystal, but if necessary, InP or other I
Any semiconductor such as a -V group compound semiconductor or St 2 can be used.

As explained in detail above, the Schottky gate field effect transistor of the present invention has a thick active layer between the gate and source, the carrier concentration is almost constant throughout the entire active layer, and moreover, the active layer directly below the gate electrode and the gate electrode are thick. Because the source and drain electrodes are formed at the same location and in close contact with the gate electrode, Schottky gate field effect transistors with good high frequency characteristics, high gate reverse breakdown voltage, and good yield can be manufactured more easily than conventional Schottky gate field effect transistors. This can be achieved through a simple process.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views of the conventional example, Figures 8 and 8N.
0) is a sectional view of one embodiment of the present invention, and FIGS. 4(4) to 4(b) and FIGS. 5 to 5(c) are lines, respectively. FIG. 6 is a cross-sectional view showing an example of the manufacturing method of FIG. 21... Semi-insulating semiconductor substrate, 22... Operating layer, 2
2'... First part of the first active layer, 22'... Second part of the active layer, 28... Source electrode, 24... Drain electrode, 25... Gate electrode, 27... ... Inorganic compound film, 26... Insulating compound film. Agent: Patent Attorney, Tetsu Shiro: ``View'' (Cμm)

Claims (1)

[Claims] (1) In a Schottky gate field effect transistor comprising a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, a source electrode, a drain wire, and a Schottky gate electrode formed on the active layer, the above-mentioned operation The layer has a thickness that provides a predetermined pinch-off voltage and is formed directly under the gate electrode, and has an impurity concentration that is approximately equal to the impurity concentration in the first portion, and and a second part having a thickness greater than the thickness of the first part, and both sides or the entire surface of the gate electrode made of a highly heat-resistant metal are covered with an insulating compound film made of itself. A Schottky gate field effect transistor characterized in that a source electrode and a drain electrode are formed in close contact with each other via the insulating compound film.