JPS587815A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS587815A
JPS587815A JP10533081A JP10533081A JPS587815A JP S587815 A JPS587815 A JP S587815A JP 10533081 A JP10533081 A JP 10533081A JP 10533081 A JP10533081 A JP 10533081A JP S587815 A JPS587815 A JP S587815A
Authority
JP
Japan
Prior art keywords
semiconductor device
substrate
fringe
insulator
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10533081A
Other languages
Japanese (ja)
Inventor
Yoichi Araki
洋一 荒木
Toshio Ogawa
敏夫 小川
Shuzo Saeki
佐伯 修三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10533081A priority Critical patent/JPS587815A/en
Publication of JPS587815A publication Critical patent/JPS587815A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To strengthen the mechanical strength of the fringe of a substrate, by thickening the fringe of the semiconductor substrate more than the other part. CONSTITUTION:The N type Si substrate 21 is formed thicker in the fringe on the lower surface thereof than the other part with the upper surface thereof in a negative beveled structure, and a P type region 22, an N<+> type region 23 and an insulator 24 constituted of silicon rubber are formed as illustrated. Thus, the fringe of the Si substrate 21 is strengthened mechanically more than the other part resulting in the restriction of increase of the power loss in the element by making the thickness of the part for an essential current flow the same as the conventional one.

Description

【発明の詳細な説明】 この発明は半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device.

従来、補強板を備えた半導体装置として、例えば鮪1図
に示す構造のものがある。同図において、1はシリコン
基板(ダイオード)、2はアルミニウム(ムt)で形成
された電極、3はシリコン基板と補強材とを接着するろ
う材、4d補強板としてのタングステン板、5はシリコ
ン基板等の絶縁物である。
2. Description of the Related Art Conventionally, there is a semiconductor device having a structure shown in FIG. 1, for example, as a semiconductor device equipped with a reinforcing plate. In the figure, 1 is a silicon substrate (diode), 2 is an electrode made of aluminum (mut), 3 is a brazing material for bonding the silicon substrate and the reinforcing material, 4d is a tungsten plate as a reinforcing plate, and 5 is silicon. It is an insulating material such as a substrate.

第2図はこの半導体装置のタングステン板4が高価であ
ることから、このタングステン板40代りにシリコンリ
ングを備えた半導体装置を示すものである。
FIG. 2 shows a semiconductor device in which a silicon ring is provided in place of the tungsten plate 40 since the tungsten plate 4 of this semiconductor device is expensive.

この装置は、まず周知の技術によシ例えばシリコンのP
N接合6をウェハ内に形成し、その後ウェハ周囲を電界
強度を弱めるため、角度加工を行いベベル構造とする。
This device is first manufactured using well-known technology, for example, P of silicon.
An N-junction 6 is formed within the wafer, and then angle processing is performed to reduce the electric field strength around the wafer to form a bevel structure.

その後、既に用意されている補強材としてのシリコンリ
ング1をアルミニウム8によりてろう付けし、両面にA
t電極9.10を低抵抗接触させる。そして、角度加工
したPN接合6の露出表面を例えば弗酸−硝酸系のエツ
チング液によシ化学工、チングして、例えばシリコンが
ムの絶縁物11を塗着する。しかる後、容器内に気密封
止し、これKより半導体部品が完成する。
After that, the already prepared silicon ring 1 as a reinforcing material is brazed with aluminum 8, and A
Make a low resistance contact with the t-electrode 9.10. Then, the exposed surface of the angularly processed PN junction 6 is chemically etched using, for example, a hydrofluoric acid-nitric acid based etching solution, and an insulator 11 made of, for example, silicone is applied. Thereafter, the container is hermetically sealed and the semiconductor component is completed.

しかしながら、この半導体装置によれば、第1図に示し
喪装置に比較し、高価なタングステンを使用していない
ため安価になるが次の欠点を有する。
However, although this semiconductor device is less expensive than the semiconductor device shown in FIG. 1 because it does not use expensive tungsten, it has the following drawbacks.

■ シリコンとシリコンリング1のろう付けの工程があ
るため製造工程が長くなる。
■ The manufacturing process is longer because there is a process of brazing the silicone and silicone ring 1.

■ 2つの材料を組合せるため位置合せが必要である(
容器に入れる場合、シリコンリングrの外径で案内する
と仮定すればろう付は精度が要求される)。
■ Positioning is required to combine two materials (
When placing it in a container, precision is required for brazing, assuming that it is guided by the outer diameter of the silicon ring r).

■ シリコンとシリコンリング7をろう付けする材料と
して、第2図に示したようにアルミニウム1が考えられ
るが、PN接合6の保饅に絶縁物1ノとしてシリコンゴ
ムの他にガラス材を用い九場合、ガラス焼成時にアルミ
ニウム8が溶解した後、再び固まるとガラスに歪を与え
、ガラスクラ、りを生じさせる。
■ Aluminum 1 can be considered as a material for brazing silicon and silicon ring 7, as shown in Fig. 2, but it is also possible to use glass material in addition to silicone rubber as insulator 1 for the PN junction 6. In this case, when the aluminum 8 melts during glass firing and then hardens again, it gives distortion to the glass and causes glass cracking.

■ PNli%合の表面加工後にシリコンリング1のろ
う付けなどの工程がらり、傷をつけやすい。
■ Processes such as brazing silicone ring 1 after surface processing of PNli% are easy to damage.

この発明は上記実情に鑑みてなされたもので、その目的
は、基板周縁部の機械的強度が強く、簡単な製造工程で
得られる安価な半導体装置を提供することにある。
The present invention has been made in view of the above-mentioned circumstances, and its purpose is to provide an inexpensive semiconductor device that has strong mechanical strength at the peripheral edge of the substrate and that can be obtained through a simple manufacturing process.

以下、図面を参照してこの発明の一実施例を説明する。Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第3図において、21はN形シリコン基板で、このシリ
コン基板21はその下面の周縁部が他の部分より厚く形
成され、かつその上面が負ベベル構造となっている。ま
た、22はこのシリコン基板21に形成されたP影領域
、23は同じく1形領域、z4は例えばシリコンゴムの
絶縁物である。
In FIG. 3, reference numeral 21 denotes an N-type silicon substrate, and this silicon substrate 21 has a lower peripheral edge portion thicker than other portions, and an upper surface having a negative bevel structure. Further, 22 is a P shadow region formed on this silicon substrate 21, 23 is a type 1 region, and z4 is an insulator such as silicon rubber.

すなわち、この半導体装置(ダイオード)においては、
シリコン基板21の周縁部を他の部分より厚くすること
によシ、機械的な破壊を防ぎ、実質的に電流の流れる部
分の厚さを従来と同じにすることKよりて、素子内の電
力損失の増加をおさえるものである。
That is, in this semiconductor device (diode),
By making the periphery of the silicon substrate 21 thicker than the other parts, mechanical damage can be prevented, and by making the thickness of the part where current flows substantially the same as before, the power inside the element can be reduced. This is to suppress the increase in losses.

第3図の半導体装置は負ベベル構造であるが、高耐圧半
導体装置の場合には第4図に示すような正ベベル構造が
多く使用されている。同図において、31は第3図に示
したシリコン基板21と同形状のN形シリコン基板、3
2はP影領域、3sは1形領域、J4は7ノード電極、
−35はカソード電極、S6はシリコン基板J1の厚肉
部分に形成された溝、31はこの擲s6に塗着された絶
縁物である。
Although the semiconductor device shown in FIG. 3 has a negative bevel structure, a positive bevel structure as shown in FIG. 4 is often used in high voltage semiconductor devices. In the figure, reference numeral 31 denotes an N-type silicon substrate having the same shape as the silicon substrate 21 shown in FIG.
2 is the P shadow area, 3s is the 1 type area, J4 is the 7 node electrode,
-35 is a cathode electrode, S6 is a groove formed in the thick portion of the silicon substrate J1, and 31 is an insulating material coated on this spool s6.

以下、第5図(1)〜(・)を参照してこの半導体装置
の製造工程を説明する。まず、第5図(1)に示すよう
に比抵抗が1000・α、厚さ1.5■、直径40−の
N形シリコン基板S1を用意する。
Hereinafter, the manufacturing process of this semiconductor device will be explained with reference to FIGS. 5(1) to (). First, as shown in FIG. 5(1), an N-type silicon substrate S1 having a resistivity of 1000.alpha., a thickness of 1.5 mm, and a diameter of 40 mm is prepared.

そして、このシリコン基板31を化学的あるいは機械的
に加工し、第5図(b)に示すように深さ1−1直径3
0φ■の開孔部38を設ける0次に、第5図(−)K示
すように周知の選択拡散技術により例えば&DンのP形
不純物を拡散しP影領域32を形成し、さらに例えばリ
ンのN形不純物を拡散し1形領域Jjを形成する0次に
1第5図(1) K示すように、例えばアル1=ウムの
電極材料を両面に低抵抗接触させ、アノード電極J4及
びカソード電極inを形成させる0次に、第5図(・)
に示すようにシリコン基板S1の厚内部分に対応するよ
うに溝3#を形成し、弗酸−硝酸系のエツチング液など
により破砕層を除去してシリコンf A 勢O絶縁物3
1を塗着すると第4図に示した構造が得られる。
Then, this silicon substrate 31 is chemically or mechanically processed to have a depth of 1-1 diameter of 3 as shown in FIG. 5(b).
Next, as shown in FIG. 5(-)K, a P-type impurity of, for example, &D is diffused to form a P-type impurity 32, and then, as shown in FIG. As shown in Figure 5 (1) K, an electrode material of, for example, aluminum is brought into low-resistance contact with both surfaces of the anode electrode J4 and cathode electrode J4. Figure 5 (-)
As shown in FIG. 3, a groove 3# is formed corresponding to the inner thickness of the silicon substrate S1, and the fractured layer is removed using a hydrofluoric acid-nitric acid based etching solution to remove the silicon f A and O insulator 3.
1, the structure shown in FIG. 4 is obtained.

こOようにこの半導体装置においては、従来のようなろ
う付は工程が不要であるため前述の■〜■のような欠点
がなくなる。
In this way, in this semiconductor device, the conventional brazing process is unnecessary, so that the drawbacks such as the above-mentioned points 1 to 2 are eliminated.

第6図乃至第10図はそれぞれこの発明の他の実施例を
示すもので、以下上記実施例と同一構成部分は同一符号
を付してその説明は省略する。第6図は第5図に示した
半導体装置において、ベベル用の溝3#を基板31の裏
面に設は絶縁物39を塗着したものである。第7図は負
ベベル構造で基板31(D上面の周縁部KIIL部40
を設け、絶縁物41を塗着しやすくしたものである。ま
た、wIiB図は半導体装置がサイリスタの場合であり
、基板4zの両面から正ベベル構造としたものである。
6 to 10 respectively show other embodiments of the present invention, and hereinafter, the same components as in the above embodiments will be given the same reference numerals and their explanation will be omitted. FIG. 6 shows a semiconductor device shown in FIG. 5 in which a bevel groove 3# is provided on the back surface of a substrate 31 and an insulator 39 is applied. FIG. 7 shows a negative bevel structure with a substrate 31 (peripheral KIIL portion 40 on the upper surface of D).
is provided to make it easier to apply the insulator 41. Further, the diagram wIiB shows a case where the semiconductor device is a thyristor, and the substrate 4z has a positive bevel structure from both sides.

同図において、43はP影領域、44は1形領域、46
はP影領域、46はカソード電極、41はダート電極、
48はアノード電極、49〜52はベベル用の溝、53
〜5#はガラス材でなる絶縁物である。第P影領域、6
0はカソード電極、61はアノード電極、61はベベル
用の溝、63はシリコンゴムでなる絶縁物を示す。
In the figure, 43 is a P shadow area, 44 is a 1-shape area, and 46
is the P shadow area, 46 is the cathode electrode, 41 is the dirt electrode,
48 is an anode electrode, 49 to 52 are bevel grooves, 53
~5# is an insulator made of glass material. Pth shadow area, 6
0 indicates a cathode electrode, 61 an anode electrode, 61 a bevel groove, and 63 an insulator made of silicone rubber.

上記実施例においては基板の形状を整えてから各領域を
拡散形成するようにしたが、第10図に示すように拡散
後にシリコン基板64を電極、6#はアノード電極、σ
9は絶縁物である。
In the above embodiment, each region was formed by diffusion after adjusting the shape of the substrate, but as shown in FIG. 10, after diffusion, the silicon substrate 64 was used as an electrode, 6# was an anode electrode, and σ
9 is an insulator.

以上のようKこの発明によれば、同一材料からなる半導
体基板の周縁部を他の部分より厚くするようにし九ので
、基板周縁部の機械的強度が増加し、簡単な製造工程で
得られる安価な半導体装置を提供できる。
As described above, according to the present invention, the peripheral edge of the semiconductor substrate made of the same material is made thicker than the other parts, so the mechanical strength of the peripheral edge of the substrate is increased, and the manufacturing process is simple and inexpensive. This makes it possible to provide a semiconductor device with excellent performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図はそれぞれ従来の半導体装置の断面図
、第3図はこの発明の一実施例に係る半導体装置の断面
図、第4図はこの発明の他の実施例を示す断面図、第5
図(a)〜(・)は第4図の装置の製造工程を示す断面
図、第6図乃至第10図はそれぞれこの発明の他の実施
例を示す断面図である。 21・・・N形シリコン基板、22・・・P影領域、2
3・・・N影領域、24・・・絶縁物。 出願人代理人  弁理士 鈴 江 武 彦jIl 図 l3ff m; 第4図 第5図 第8図 第9図 特許庁長官  島 1)春 樹 殿 1、事件の表示 特願昭56−105330号′ 2、発明の名称 半導体装置 3、補正をする者 事件との関係 特許出願人 (307)  東京芝浦電気株式会社 昭和56年11月24日 6、補正の対象 図面 7、補正の内容 別紙に未配して示す通り1図面第2葉中に「第 図」を
加入して第5図(1)〜(dlとする。
1 and 2 are sectional views of a conventional semiconductor device, FIG. 3 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a sectional view of another embodiment of the invention. , 5th
Figures (a) to (•) are cross-sectional views showing the manufacturing process of the device shown in Figure 4, and Figures 6 to 10 are cross-sectional views showing other embodiments of the present invention. 21...N type silicon substrate, 22...P shadow area, 2
3...N shadow area, 24...Insulator. Applicant's representative Patent attorney Takehiko Suzue Figure 13ff m; Figure 4 Figure 5 Figure 8 Figure 9 Commissioner of the Patent Office Shima 1) Haruki Tono 1, Case Indication Patent Application No. 105330'1983' 2 , Name of the invention Semiconductor device 3, Relationship with the case of the person making the amendment Patent applicant (307) Tokyo Shibaura Electric Co., Ltd. November 24, 1981 6, Drawing subject to the amendment 7, Contents of the amendment Not included in the attached sheet As shown in Figure 5, ``Figure'' is added to the second page of one drawing to form Figure 5 (1) to (dl).

Claims (2)

【特許請求の範囲】[Claims] (1)同一材料からなる半導体基板の周縁部が他の部分
より厚(なっていることを特徴とする半導体装置。
(1) A semiconductor device characterized in that a peripheral portion of a semiconductor substrate made of the same material is thicker than other portions.
(2)前記周縁部の厚い部分に少々くとも一方の面から
表面加工が施されている特許請求の範囲第1項記載の半
導体装置。
(2) The semiconductor device according to claim 1, wherein the thick portion of the peripheral edge portion is slightly surface-treated from at least one side.
JP10533081A 1981-07-06 1981-07-06 Semiconductor device Pending JPS587815A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10533081A JPS587815A (en) 1981-07-06 1981-07-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10533081A JPS587815A (en) 1981-07-06 1981-07-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS587815A true JPS587815A (en) 1983-01-17

Family

ID=14404707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10533081A Pending JPS587815A (en) 1981-07-06 1981-07-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS587815A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51123072A (en) * 1975-04-21 1976-10-27 Hitachi Ltd Fabrication technigue of highly pressure-resistant semiconductor devic es
JPS5224874B1 (en) * 1971-01-25 1977-07-04
JPS53135568A (en) * 1977-04-30 1978-11-27 Mitsubishi Electric Corp Manufacture for semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5224874B1 (en) * 1971-01-25 1977-07-04
JPS51123072A (en) * 1975-04-21 1976-10-27 Hitachi Ltd Fabrication technigue of highly pressure-resistant semiconductor devic es
JPS53135568A (en) * 1977-04-30 1978-11-27 Mitsubishi Electric Corp Manufacture for semiconductor device

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