JPS6066469A - Semiconductor device - Google Patents

Abstract

PURPOSE:To check damage during the process of production, and to enhance manufacturing yield and reliability of a semiconductor device by a method wherein aslant processed surfaces are formed to the peripheral edge parts of a substrate, and inorganic material insulating films are formed on the surfaces. CONSTITUTION:A P type emitter layer 32 and a P type base layer 33 are formed respectively on both the surfaces of an N type semiconductor substrate 30, and an N type emitter region 34 is formed. The sides of the substrate 30 are scraped by a grinder to form respectively negative bevel faces B1, B2 making an angle of 3 deg. or less (the bevel angle theta) with P-N junction faces PN1, PN2. Thermal oxidation is performed to form oxide films as surface covering films 41, and metal films such as aluminum, etc. are evaporated to be patterned to form an anode electrode 35, a cathode electrode 36 and a gate electrode 37. Because there exists no part cut out making an acute angle with the substrate 30 by the bevel process, mechanical strength is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device such as a large power device such as a thyristor.

[Technical background of the invention]

Figure 1 shows an example of the structure of a conventional Cyrisk. In the figure, an N-type silicon semiconductor substrate 1 serving as an N pace region is shown.
A P-type P emitter layer 2 is formed on the back surface of the P-type P emitter layer 2, and a P-type P base layer 3 is formed on the top surface of the P-type P base layer 3.
An N0-shaped N emitter region 4 is formed in the surface region.

An anode electrode 5 is placed on the surface of the P emitter layer 2 on the back surface of the substrate, a cathode electrode 6 is placed on the N emitter region 4 on the top surface of the substrate, and a cathode electrode 6 is placed on the exposed surface of the P base layer 3 where the N emitter region 4 is not formed. Dirt electrodes 7 are formed respectively.

By the way, in high-voltage devices such as SiRisk, the device breakdown voltage is often determined by electric field concentration on the side surface of the substrate where the PN junction is exposed. Therefore, in order to provide pressure resistance on this surface, a bevel structure is adopted in which the shape of the bonding surface is inclined.

In the figure, the inclined surface 8 is the first bevel applied to the first PN junction surface PN1 formed by the P emitter layer 2 and the N type substrate 1, and the groove 9 is the first bevel applied to the first PN junction surface PN1 formed by the P emitter layer 2 and the N type substrate 1. base 3
This is the second bevel applied to the second PN joint surface PN2, which has a special shape IlX.

There are two types of such bevel surfaces: positive bevel surfaces and negative bevel surfaces. That is, in FIG. 2, the first impurity layer 21 of the first conductivity type and the impurity vIJ
The second impurity layer 22 with high concentration ( i
If the angle θ formed at ilj exceeds 90', it is a positive bevel.
A case where the angle is less than 90° is called a negative bevel. Figure 2 shows the case of a negative bevel, and the device in Figure 1 has a higher impurity concentration in the P emitter layer 2 and the P base layer 3 than in the N type substrate 1, and the positive R' bevel surface. was formed.

[Problems with background technology]

Here, among the peripheral edge processing portions applied to the substrate, the corner portion (■) of the P emitter layer 2 on the first bevel surface 8 and the opening portion (■) on the second bevel surface 9 are cut out at an acute angle. It is easily damaged during the process. Damage to these parts leads to a deterioration of the withstand voltage, so it is necessary to pay sufficient attention during the manufacturing process, and the manufacturing yield is also low.

Further, as shown in the figure, on such beveled surfaces 8 and 9, a surface covering material 1o, for example 7. , ,'y'n rubber,
Apply a layer type material such as Solicon varnish.

However, when applying such a coating material, air bubbles remained particularly in the grooves of the second bevel surface 9, making it difficult to obtain stable device characteristics.

Further, such resin-based surface covering materials have insufficient reliability, and in order to compensate for the reliability, it is necessary to use an expensive hermetically sealed package as an envelope for the device.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor device that can prevent damage during the manufacturing process and has a high manufacturing yield and reliability without the need for expensive hermetic sealing and sealing. This is what I am trying to do.

[Summary of the invention]

That is, in the semiconductor device according to the present invention, a negative bevel inclined surface forming an angle of 3° or less with respect to the PN junction surface is formed as a bevel processing on the peripheral edge of the substrate, and the surface of this inclined processed surface is coated with silicon oxide, for example. A highly reliable inorganic insulating film made of a film, a semi-insulating polycrystalline silicon film, or a laminated film of these films is formed.

[Embodiments of the invention]

An embodiment of the present invention will be explained below with reference to the drawings.

In FIG. 3, a P-type impurity is diffused on the back surface of an N-type semiconductor substrate 30 to form a P-type P emitter layer 32,
Similarly, P type impurities are completely diffused from the upper surface side of the substrate 30 to form a P type P base layer 33. ' Thereafter, an N-type impurity is selectively diffused almost in the center of the upper surface of the substrate 30 to form an N emitter region 34 in the P space layer 33. In addition, the P emitter layer 3 of the two-layer half-layer substrate 30
2 and l) The N-type region sandwiched between the base layers 33 becomes the N base layer 3.

Next, a protective film such as a resist film is applied to the entire upper and lower surfaces of the substrate in advance, and the side surface of the substrate 30 is ground by a polishing device having a cutting edge having a cross-sectional shape as shown at 40, for example. This allows the first PN to be formed by the N base layer 3 and the P emitter layer 32 on the back side of the substrate 3υ.
A negative bevel surface Bl forming an angle (bevel angle θ) of 3° or less with respect to the bonding surface PN is formed on the upper surface side of the substrate and the JO with a second PN formed by an N base layer 3 and a P base layer 33. Negative bevel surface B2 forming an angle of 3° or less with respect to the joint surface PN2
form each. In the device shown in FIG. 3, the N base layer 3 has a lower impurity concentration than the P emitter layer 32 and the P base layer 33.

Thereafter, the crushed layer (rough surface after grinding) of the negative bevel surfaces B1+B2 is removed using a mixed acid (a mixed solution of nitric acid, hydrofluoric acid, etc.).

Next, as shown in FIG. 4, this substrate 3o is thermally oxidized, for example, to form an oxide film covering the entire surface of the substrate 30 on the surface of the substrate 30, thereby forming an anode electrode, a cathode electrode and a dirt electrode. The anode electrode 3 is formed on the P emitter layer 32 by removing the oxide film in the region where the P emitter layer 32 is to be formed, and then depositing a metal film such as aluminum and turning it slightly.
5. A cathode electrode 36 is formed on the N emitter region 34, and a cathode electrode 37 is formed on the P-E2 layer 33 on which the N emitter layer is not formed.

Here, the negative pezzle planes B and B2 are each PN
This is done in order to alleviate the electric field concentration near the portion where the junction output IPN, PN, is exposed on the substrate 3o. Therefore, as shown in FIG. 5, slope processing is performed only near the exposed portions of the first PN bonding surface PN and the second PN bonding surface PN to form a negative bevel surface HI+83. Good too.

FIG. 6 shows the substrate 3 of the device having the structure shown in FIG.
The results of investigating the relationship between the height δ of the machined part from the flat part of the zero surface to the end of the inclined machined surface and the element breakdown voltage for various bevel angles θ are shown.

Here, the thicknesses of the N base layer 3, the P emitter layer 32, and the P base layer 330 in the target device are each 500 mm.
fim, 120 μm, and 120 μm.

As shown in the graph of FIG. 6, the bevel angle θ between the bevel surface and the PN junction surface is preferably about 1°, and it is sufficient to form the bevel surface with a bevel angle of 3° or less. -1: /ko, if the bevel angle θ is small, the substrate 30
(Although it can be handled in almost the same way as the flat wafer in the 3-way block, if the bevel angle θ is increased, sufficient device breakdown voltage cannot be obtained. Instead of 9, the protective film 4) is formed This is not preferable because it may complicate the process.

As described above, in the device shown in Fig. 4, the mechanical strength is improved because there is no part cut out at an acute angle in the substrate 30 due to the bevel processing. In the apparatus shown in FIG.
is formed, but this step is very small, and this step is sufficiently far away from the PN junction surfaces PN, PN2, so there is almost no problem of breakdown voltage deterioration due to damage.

In the device shown in Figure 4, the board 30 is BI+.
An oxide film was formed as the a-coat film 47 over B2 and the side surface of the substrate 30, but since the distance t from the PN junction surface to the substrate center is, for example, several meters, as shown in FIG. Even if the coating film 41 is not formed on the side surface of the substrate 30, there is no problem in terms of the withstand voltage of the element.

Furthermore, in the device shown in Figure 4, a thermal oxide film was used as the coating on the PN junction. It is extremely reliable compared to other methods.

Further, as the coating film 41, in addition to a silicon oxide film formed by thermal oxidation, CVD (Chemical Vapor
It may also be formed by depositing the activated film on the beveled surface BI+B2 by a method (rDeposition). Furthermore, semi-insulating polycrystalline silicon (5
For example, a highly reliable device can be obtained by forming a semiconductor device (rpos). Furthermore, the silicon oxide film and the semi-insulating polycrystalline silicon may be entirely laminated, or the above/
A coating film of silica rubber, varnish, polyimide resin, or the like may be laminated and deposited on the silicon oxide film or the semi-insulating polycrystalline silicon coating film.

Incidentally, a conventional element having a positive bevel surface can be used as an MO. Here, since the aluminum-silicon alloy has a low heat cutting temperature, it cannot be subjected to a process involving still temperature treatment such as thermal oxidation. Therefore, it is impossible to form an oxide film on the beveled surface of the conventionally structured device.

〔Effect of the invention〕

In the above manner, we prototyped an element with the structure shown in Figure 5, which had a full shoulder structure.As a result, damage to the Venlicon board was reduced by about 10% compared to the conventional element shown in Figure 1. We were able to improve yield.

- In addition, when the device according to the present invention was installed in a hermetically sealed/4' cage with a leak rate of 10'-' (ATM cc/see: l) and was subjected to high temperature and humidity tests, it was found that it was different from the conventional device. Although it was not possible to confirm the difference in the reliability of the
When installed in a 168-hour high-temperature, high-humidity test, an increase in leakage current and forward voltage drop was observed in approximately half of the conventional equipment. No leakage current or fluctuation in forward voltage drop was observed in all devices tested in accordance with the present invention.

As described above, according to the present invention, it is possible to provide a semiconductor device f: which is less susceptible to damage during the manufacturing process, has a high manufacturing yield, and is also excellent in reliability.

It should be noted that the present invention is not limited to the above embodiment, and for example, the 4-electrode type of each part may be configured in reverse to the above embodiment.
Furthermore, if there are many devices that require bevel processing on the exposed PN junction m1, the F=J function can be applied to other devices such as triacs.

[Brief explanation of the drawings] Figure 1 is a cross-sectional view of the 4KJ structure of a conventional four-body device, Figure 2 is a cross-sectional view of the bevel structure, and Figures 3 and 4 are respectively FIG. 5 is a sectional view showing a semiconductor device according to another embodiment of the present invention; FIG. 6 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention; FIG. 3 is a graph showing the relationship between the withstand pressure and the height δ of the processed portion, and the bevel angle θ as parameters. 30... Semiconductor substrate, 3... N paste layer, 32...
...P emitter layer, 33...P pace layer, 34...
N emitter region, 35... anode electrode, 36...
Cathode electrode, 37...Dart electrode, B1, B2...
- Beveled surface, 41... forward curved coating membrane. Applicant's representative Patent attorney Takehiko Suzue Figure 4 Figure 6 Riki 2 vP height

Claims (4)

[Claims] (1) In a semiconductor device in which a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type forming a PN junction surface are stacked, and the PN junction surface is exposed on a side surface of a semiconductor substrate. . A semiconductor device, wherein a side surface of the semiconductor substrate has a sloped surface forming an angle of 3 degrees or less with respect to the PN junction surface, and an inorganic protective film is formed on the sloped surface. (2) The semiconductor device according to claim 1, wherein the inorganic protective film is a silicon oxide film. (3) The semiconductor device according to claim 1, wherein the inorganic protective film is a semi-insulating silicon polycrystalline film. (4) The semiconductor device according to claim 1, wherein the inorganic protective film is a laminated film of a silicon oxide film and a semi-insulating silicon polycrystalline film.