JPS5877928U - Digital input noise removal circuit - Google Patents
Digital input noise removal circuitInfo
- Publication number
- JPS5877928U JPS5877928U JP17207281U JP17207281U JPS5877928U JP S5877928 U JPS5877928 U JP S5877928U JP 17207281 U JP17207281 U JP 17207281U JP 17207281 U JP17207281 U JP 17207281U JP S5877928 U JPS5877928 U JP S5877928U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- digital input
- noise removal
- input
- input noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例を示すブロック図、第2図は
第1図の各部のタイムスケジュール図である。
1・・・・・・入力端、2・・・・・・遅延回路、3・
・曲ワンショット回路、4・・・・・・論理積回路、5
・・・・・・出力端、・ 6・・・・・・ディジタル入
力信号、7・・・・・・2の出力信号、8・・・・・・
3の出力信号、9・・・・・・4の出力信号、TS・・
・・・・正常信号のパルス巾、TN・・曲雑音のパルス
巾、TD・・・・・・遅延回路の遅延時間、To・・・
・・・ワンショット回路の否定出力パルス巾、Td・・
・・・・ワンショット回路の応答時間、A・・曲正常信
号入力時、−B・・・・・・誘導等の雑音入力時、C・
・曲チャタリング等の雑音入力時。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time schedule diagram of each part of FIG. 1. 1...Input terminal, 2...Delay circuit, 3.
・Song one-shot circuit, 4...AND circuit, 5
...Output end, 6...Digital input signal, 7...Output signal of 2, 8...
3 output signal, 9...4 output signal, TS...
...Pulse width of normal signal, TN...Pulse width of music noise, TD...Delay time of delay circuit, To...
...Negation output pulse width of one-shot circuit, Td...
...Response time of one-shot circuit, A...When a normal song signal is input, -B......When noise such as induction is input, C.
・When inputting noise such as song chattering.
Claims (1)
路の出力等のディジタル出力信号を入力とするディジタ
ル入力回路において、前記各種出力信号を入力とする遅
延回路と、前記各種出力信号を入力とし、この信号の前
端で動作するワンショット回路と、遅延回路の出力信号
とワンショット回路の否定出力信号とを入力きする論理
積回路とを備えた事を特徴とするディジタル入力の雑音
除去回路。In a digital input circuit that receives digital output signals such as relay contact outputs, transistor outputs, and outputs of digital integrated circuits, there is a delay circuit that receives the various output signals as input, and a delay circuit that receives the various output signals as input, and a front end of this signal. What is claimed is: 1. A digital input noise removal circuit comprising: a one-shot circuit operating at 100 nm; and an AND circuit inputting an output signal of a delay circuit and a negative output signal of the one-shot circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17207281U JPS5877928U (en) | 1981-11-20 | 1981-11-20 | Digital input noise removal circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17207281U JPS5877928U (en) | 1981-11-20 | 1981-11-20 | Digital input noise removal circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5877928U true JPS5877928U (en) | 1983-05-26 |
Family
ID=29963978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17207281U Pending JPS5877928U (en) | 1981-11-20 | 1981-11-20 | Digital input noise removal circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5877928U (en) |
-
1981
- 1981-11-20 JP JP17207281U patent/JPS5877928U/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5877928U (en) | Digital input noise removal circuit | |
JPS591239U (en) | solid state relay | |
JPS60127100U (en) | Sound addition device | |
JPS60101832U (en) | Complementary MOS integrated circuit | |
JPS59149792U (en) | eco-addition device | |
JPS59122689U (en) | Acoustic stop circuit | |
JPS60158332U (en) | reset circuit | |
JPS60116501U (en) | Control signal switching circuit | |
JPS59180208U (en) | Emphasis switching circuit | |
JPS60127099U (en) | Sound addition device | |
JPS5830332U (en) | Schmitt circuit | |
JPS60636U (en) | multiplication circuit | |
JPS61334U (en) | Tri-state gate element chip | |
JPS58119300U (en) | Speaker switching device | |
JPS59187225U (en) | Delay adjustment circuit | |
JPS5876215U (en) | audio amplifier | |
JPS6020098U (en) | Output circuit | |
JPS58178724U (en) | Gain switching circuit in amplifier | |
JPS5996610U (en) | Bus abnormality detection circuit | |
JPS59152856U (en) | Multi-charging test circuit for public telephones | |
JPS58147334U (en) | Contact chatter removal circuit | |
JPS60193599U (en) | Noise removal device in echo circuit | |
JPS6072016U (en) | noise reduction device | |
JPS5876219U (en) | Frequency characteristic variable circuit | |
JPH02120942U (en) |