JPS5877928U - Digital input noise removal circuit - Google Patents

Digital input noise removal circuit

Info

Publication number
JPS5877928U
JPS5877928U JP17207281U JP17207281U JPS5877928U JP S5877928 U JPS5877928 U JP S5877928U JP 17207281 U JP17207281 U JP 17207281U JP 17207281 U JP17207281 U JP 17207281U JP S5877928 U JPS5877928 U JP S5877928U
Authority
JP
Japan
Prior art keywords
circuit
digital input
noise removal
input
input noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17207281U
Other languages
Japanese (ja)
Inventor
黒木 邦彦
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP17207281U priority Critical patent/JPS5877928U/en
Publication of JPS5877928U publication Critical patent/JPS5877928U/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すブロック図、第2図は
第1図の各部のタイムスケジュール図である。 1・・・・・・入力端、2・・・・・・遅延回路、3・
・曲ワンショット回路、4・・・・・・論理積回路、5
・・・・・・出力端、・ 6・・・・・・ディジタル入
力信号、7・・・・・・2の出力信号、8・・・・・・
3の出力信号、9・・・・・・4の出力信号、TS・・
・・・・正常信号のパルス巾、TN・・曲雑音のパルス
巾、TD・・・・・・遅延回路の遅延時間、To・・・
・・・ワンショット回路の否定出力パルス巾、Td・・
・・・・ワンショット回路の応答時間、A・・曲正常信
号入力時、−B・・・・・・誘導等の雑音入力時、C・
・曲チャタリング等の雑音入力時。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time schedule diagram of each part of FIG. 1. 1...Input terminal, 2...Delay circuit, 3.
・Song one-shot circuit, 4...AND circuit, 5
...Output end, 6...Digital input signal, 7...Output signal of 2, 8...
3 output signal, 9...4 output signal, TS...
...Pulse width of normal signal, TN...Pulse width of music noise, TD...Delay time of delay circuit, To...
...Negation output pulse width of one-shot circuit, Td...
...Response time of one-shot circuit, A...When a normal song signal is input, -B......When noise such as induction is input, C.
・When inputting noise such as song chattering.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] リレー接点出力、トランジスタ出力、ディジタル集積回
路の出力等のディジタル出力信号を入力とするディジタ
ル入力回路において、前記各種出力信号を入力とする遅
延回路と、前記各種出力信号を入力とし、この信号の前
端で動作するワンショット回路と、遅延回路の出力信号
とワンショット回路の否定出力信号とを入力きする論理
積回路とを備えた事を特徴とするディジタル入力の雑音
除去回路。
In a digital input circuit that receives digital output signals such as relay contact outputs, transistor outputs, and outputs of digital integrated circuits, there is a delay circuit that receives the various output signals as input, and a delay circuit that receives the various output signals as input, and a front end of this signal. What is claimed is: 1. A digital input noise removal circuit comprising: a one-shot circuit operating at 100 nm; and an AND circuit inputting an output signal of a delay circuit and a negative output signal of the one-shot circuit.
JP17207281U 1981-11-20 1981-11-20 Digital input noise removal circuit Pending JPS5877928U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17207281U JPS5877928U (en) 1981-11-20 1981-11-20 Digital input noise removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17207281U JPS5877928U (en) 1981-11-20 1981-11-20 Digital input noise removal circuit

Publications (1)

Publication Number Publication Date
JPS5877928U true JPS5877928U (en) 1983-05-26

Family

ID=29963978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17207281U Pending JPS5877928U (en) 1981-11-20 1981-11-20 Digital input noise removal circuit

Country Status (1)

Country Link
JP (1) JPS5877928U (en)

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