JPS5877250A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5877250A
JPS5877250A JP56176039A JP17603981A JPS5877250A JP S5877250 A JPS5877250 A JP S5877250A JP 56176039 A JP56176039 A JP 56176039A JP 17603981 A JP17603981 A JP 17603981A JP S5877250 A JPS5877250 A JP S5877250A
Authority
JP
Japan
Prior art keywords
pellet
chip
polyimide resin
alpha rays
mo8ic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56176039A
Other languages
Japanese (ja)
Inventor
Masahide Ozawa
小澤 雅英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56176039A priority Critical patent/JPS5877250A/en
Publication of JPS5877250A publication Critical patent/JPS5877250A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556Protection against radiation, e.g. light or electromagnetic waves against alpha rays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To obtain a plastic sealed high integrated MOSIC having no soft error by a method wherein an Si chip is adhered on a pellet using polyimide resin as an adhesive. CONSTITUTION:An Si chip 7 is adhered on an insulating film 3 for protection of element using polyimide resin 6. By this constitution, the connecting parts of a pellet 1 and fine metal wires 5 are not covered with resin 6, the Si chip 7 contains no element to generate alpha rays, and because the chip having thickness of 100mum or more can be obtained easily, it has the sufficiently screening effect to alpha rays of high energy, and a high reliable plastic sealed MOSIC can be obtained.

Description

【発明の詳細な説明】 本発明はプラスチック封止された半導体集積回路装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a plastic-encapsulated semiconductor integrated circuit device.

半導体集積回路装置、特に、電界効果型半導体集積回路
装置(以下、MOS  ICと称す)に於ける高集積度
化は目ざましく、それに伴う微細パターン化技術の進歩
も著しいものがある。MO8ICの高集積度化は、MO
8I01個のもつ機能を複雑し、その応用分野も年々広
くなってきている。このような高集積度、多機能化によ
って、素子の設計技術を含めた製造上の問題点が増加し
てきたことはもちろんであるが、その他にα線によるソ
フトエラーという信頼性上の問題が発生し、微細パター
ン化が進むにつれてクローズアップされて睡でいる。
BACKGROUND ART The degree of integration in semiconductor integrated circuit devices, particularly field-effect semiconductor integrated circuit devices (hereinafter referred to as MOS IC), has been increasing rapidly, and the progress in fine patterning technology has also been remarkable. The high integration of MO8IC is
The functions of 8I01 are becoming more and more complex, and the fields of their application are becoming broader year by year. Such high integration and multifunctionality have not only led to an increase in manufacturing problems including element design technology, but also reliability problems such as soft errors caused by alpha rays. However, as micropatterning progresses, it is being looked at closely.

α線によるソフトエラーの問題は、特にダイナミックM
O8メモリー(以下DRAMと呼ぶ)において顕著であ
l)、15Kb i tDRAMに於て゛発見されs 
64 K D RA Mの製品化によって、避けること
のできない大きな問題となった。DRAMに於けるα線
によるソフトエラーは次のように説明されている。一般
にMOBのDRAMは、薄い酸化膜をはさんで多結晶シ
リコンと基板中導体を配置し、その間にで粘る容量を利
用し、そこに蓄えられる電荷を情報として、書込み・続
出しを行っている。所謂α線によるソフトエラーは、上
記容量を形成している部分にα線が入射した場合に、基
板半導体内でα線による電子・正孔ペアが発生し、それ
が原因となって蓄えられていた情報を反転又は消去する
為に発生するものであ為。
The problem of soft errors caused by α rays is particularly important for dynamic M
It is noticeable in O8 memory (hereinafter referred to as DRAM), and is found in 15Kbit DRAM.
With the commercialization of 64K DRAM, this has become a major problem that cannot be avoided. Soft errors caused by alpha rays in DRAM are explained as follows. In general, MOB DRAM uses polycrystalline silicon and a conductor in the substrate with a thin oxide film in between, and uses the capacitance between them to write and read data using the charge stored there as information. . So-called soft errors caused by alpha rays are caused by the generation of electron-hole pairs in the substrate semiconductor when alpha rays are incident on the part that forms the capacitance, which causes the particles to be stored. This is caused by reversing or erasing the information.

α線、によるソフトエラーを避ける手段としては。As a means to avoid soft errors caused by alpha rays.

DRAMを構成する各々のメモリーセル容量を増加させ
る方法があるが、各々のメモリーセルの面積の増加につ
ながシ%DRAMの素子サイズが大きくなってしまう為
、セル容量の増加には自ら限界がある。そこで現在採ら
れている方法は素子に、α線の発生源となるような元素
を含まない(通常Ippb以下)物質を塗布することに
より、α線が素子表面迄到達しないようにして、ソフト
エラ一対策とする方法である。このα線に対する遮蔽物
質?、素子・上に塗布する方法は、極めて有効であり、
その膜厚が数+μm以上あれば、自然界に存在するほと
んど全てのα線を阻止することが可能である。具体的に
は、MO8IC素子をケースにマウントし、ケースとペ
レットを金属細線にて接続した後、上からポリイミド系
又はシリコーン系の樹脂を滴下することによって、ペレ
ット上にα線に対する保ia膜を設る方法が一般的であ
って、セラミックケースに実装する場合に社極めて量産
性・信頼性ともに良い方法であるが、ペレットをプラい
る。即ち、ポリイミド系又はシリコン系の樹脂が1M0
8ICの外部配線取り出し用電極と、ケース・ペレット
接続用金属細線との接続部を覆い。
There is a method to increase the capacity of each memory cell that makes up a DRAM, but since this increases the area of each memory cell and increases the element size of the DRAM, there is a limit to increasing the cell capacity. . Therefore, the current method is to prevent alpha rays from reaching the element surface by coating the element with a substance that does not contain elements that can generate alpha rays (usually less than Ippb), thereby reducing soft errors. This is a countermeasure. Is this a shielding material for alpha rays? , the method of coating on the element is extremely effective,
If the film thickness is several micrometers or more, it is possible to block almost all alpha rays existing in nature. Specifically, after mounting the MO8IC element in a case and connecting the case and the pellet with a thin metal wire, a polyimide or silicone resin is dropped from above to form an ia-protective film on the pellet against alpha rays. The most common method is to use pellets, and when mounting on a ceramic case, this method has excellent mass productivity and reliability. That is, polyimide or silicone resin is 1M0
Covers the connection between the external wiring extraction electrode of 8IC and the thin metal wire for case/pellet connection.

該ポリイミド系又は、シリコーン系の樹脂と、MO8I
Cベレット封止用プラスチックとの熱膨張系数の差等の
原因によ)、ケース・ペレット接続用金属細線が断線も
しくは、MO8ICの外部配線数シ出し用電極部で接続
用金属細線が、電極からはがれてしまうという不良モー
ドを持つことになる。
The polyimide or silicone resin and MO8I
(Due to the difference in thermal expansion coefficient with the plastic for sealing C pellet), the thin metal wire for connecting the case and pellet may be disconnected, or the thin metal wire for connection may be disconnected from the electrode at the electrode section for external wiring number of MO8IC. It has a failure mode of peeling off.

上記不良モードを避けて、ソフトエラーに関して問題の
ない、プラスチック封止の高集積MO8ICを実現する
為に、ポリイミド系樹脂を塗布した後、ポリインド系樹
脂のパターンユングを行い、ケース・ペレット接続用金
属細線と、MO8IC外部配置11喉J)出し用電極と
の接続部を、ポリイミド系樹脂が僅わないようにする手
段も一部量産に適用されているが、この方法も樹脂の膜
厚を厚くするとパターンユングが困難であり、数μm〜
30μm程度が限界な為、高エネルギーのα線に対して
は阻止能力がなく、ソフトエラーに対しては完全な対策
とはならない。
In order to avoid the above failure mode and realize a plastic-sealed highly integrated MO8IC without any problems with soft errors, after applying polyimide resin, we patterned the polyimide resin and used metal for connecting the case and pellet. Some methods are used in mass production to prevent polyimide resin from getting into the connection between the thin wire and the MO8IC external arrangement 11 throat J) exit electrode, but this method also increases the thickness of the resin film. Then, pattern Jung is difficult, and the pattern is several μm~
Since the limit is about 30 μm, there is no blocking ability against high-energy α rays, and it is not a complete countermeasure against soft errors.

本発明は、ポリイミド系wWItl−接着剤として3i
′片をペレット上にはり付けることによって、ソフトエ
ラーのない、プラスチック封止の高集積度M08ICを
実現するものである。
The present invention uses 3i as a polyimide-based wWItl-adhesive.
By gluing the 'piece onto the pellet, a highly integrated M08IC sealed in plastic without soft errors is realized.

以下、第1図を用いて、現在採られているソフトエラ一
対策とプラスチック封止時の問題点について述べ、しか
る後本発明の実施例を第2図を用いて行う。
Hereinafter, with reference to FIG. 1, the currently adopted countermeasures against soft errors and the problems encountered during plastic sealing will be described, and then examples of the present invention will be explained using FIG. 2.

現在セラミックケースに実装する場合のα線対策は、M
O8ICペレット1上の素子保線用絶縁膜3に接して、
ペレット1をケースにマウントし、ケースの電極とMO
8IC外部配線取シ出し用電極2とを金属細線5で接続
した後、ポリイミド系樹脂4を滴下する。ところがポリ
イミド系樹脂4が金属細線5とMO8ICの電極2との
接続部8を完全に覆ってしまい、プラスチック封する時
に金属!i線5に加わる応力が、封止用プラスチックと
、ポリイミド系樹脂4とで異る為、金属線線5の断線又
はペレットとの接続部8でのハガレが発生し、量産上の
問題となる。
Currently, the α-ray countermeasures when mounting in a ceramic case are M
In contact with the element wire maintenance insulating film 3 on the O8IC pellet 1,
Mount pellet 1 in the case, connect the electrode of the case to the MO
After connecting the 8 IC external wiring extraction electrode 2 with a thin metal wire 5, polyimide resin 4 is dropped. However, the polyimide resin 4 completely covers the connecting part 8 between the thin metal wire 5 and the electrode 2 of the MO8IC, and when it is sealed with plastic, the metal is completely covered! Since the stress applied to the i-line 5 is different between the sealing plastic and the polyimide resin 4, the metal wire 5 may break or peel off at the connection part 8 with the pellet, which poses a problem in mass production. .

本発明は、素子保護用絶縁膜3上、ポリイミド系樹脂6
t−接着剤としてSi片7を設置することによってソフ
トエラーのない高集積度のプラスチック封止MO8IC
の製作が可能である。本発明に依れば、ポリインド果樹
6がペレットと金属細線との接続部8t−aうこともな
く、又Si片7はα線源となるような元素を含まず、厚
さも100μm以上の亀のが容易に得られる為高エネル
ギーのα線に対しても十分な遮蔽効果を持つことがら、
極めて信頼性の高いプラスチック封止MO8ICトナル
。又、 通iMo 8 I Cでα線に対してソフトエ
ラーを発生するような回路は、MO8IC全面ではなく
一部分であpl例えばMOS  DRAMの場合にはメ
モリーセル部のみなので、Si片7の大きさは、そのα
線に対しソフトエラーを発生する回路部分を覆う大きさ
にしておけばよい。
In the present invention, a polyimide resin 6 is used on an insulating film 3 for protecting an element.
Highly integrated plastic encapsulation MO8IC without soft error by installing Si piece 7 as t-glue
It is possible to produce According to the present invention, the poly-ind fruit tree 6 does not have a connecting portion 8t-a between the pellet and the thin metal wire, and the Si piece 7 does not contain any element that can become an α-ray source, and has a thickness of 100 μm or more. Since it is easy to obtain, it has a sufficient shielding effect even against high-energy alpha rays.
Extremely reliable plastic sealed MO8IC tonal. In addition, the circuit that generates a soft error due to alpha rays in the iMo8 IC is not on the entire surface of the MO8IC, but only in a part of it. For example, in the case of a MOS DRAM, it is only the memory cell part, so the size of the Si piece 7 is that α
It is sufficient to make it large enough to cover the part of the circuit that causes a soft error with respect to the line.

本発明の実施により、素子の設計を向う変更することな
く、極めて高信頼度のプラスチック封止高集積度MO8
ICが実現できる。
By implementing the present invention, an extremely reliable plastic-encapsulated highly integrated MO8 can be produced without changing the device design.
IC can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はマウント・金属細線によるペレットとケース電
極との接続後ポリイミド系樹脂を滴下した従来の半導体
装置の断面図、第2図はポリイミド系樹脂を接着剤とし
てSi 片をペレット上に設置した本発明の実施例の半
導体装置の断面図、である。 尚、図において、1・・・・・・MO8ICペレクトペ
レット・・・・MO8IC外部配線取シ出し用電極%3
・・・・・・MO8IC素子保護用絶縁暎、4・・・・
・・ボリイ(ド系11脂、5・・・・・・ケースとベレ
y)r’m続する金属細線、6・・・・・・接着剤とし
て用いるポリイミド系樹脂、7・・・・・・Si  片
、8・・・・・・金属細線5とMO8IC電極2との接
続部、である。 第1図 δ 竿2図
Figure 1 is a cross-sectional view of a conventional semiconductor device in which a polyimide resin is dropped after the pellet is connected to a case electrode using a mount and thin metal wire, and Figure 2 is a Si piece placed on the pellet using polyimide resin as an adhesive. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. In addition, in the figure, 1...MO8IC pellet...MO8IC external wiring extraction electrode%3
...Insulation for MO8IC element protection, 4...
...Bori (de-based 11 resin, 5...Case and beret) r'm continuous thin metal wire, 6...Polyimide resin used as adhesive, 7... -Si piece, 8...This is the connection part between the thin metal wire 5 and the MO8IC electrode 2. Figure 1 δ Rod Figure 2

Claims (1)

【特許請求の範囲】[Claims] 素子表面保護用絶縁膜上に、ポリイミド系樹脂を介して
シリコン片が設けられていることを特徴とする半導体装
置。
A semiconductor device characterized in that a silicon piece is provided on an insulating film for protecting an element surface with a polyimide resin interposed therebetween.
JP56176039A 1981-11-02 1981-11-02 Semiconductor device Pending JPS5877250A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56176039A JPS5877250A (en) 1981-11-02 1981-11-02 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56176039A JPS5877250A (en) 1981-11-02 1981-11-02 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5877250A true JPS5877250A (en) 1983-05-10

Family

ID=16006646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56176039A Pending JPS5877250A (en) 1981-11-02 1981-11-02 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5877250A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4826297A (en) * 1985-12-25 1989-05-02 Hitachi, Ltd. Liquid crystal display device having an extention metal film wiring which is covered by polyimide layer having low viscosity under 1.0 poise before curing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4826297A (en) * 1985-12-25 1989-05-02 Hitachi, Ltd. Liquid crystal display device having an extention metal film wiring which is covered by polyimide layer having low viscosity under 1.0 poise before curing

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