JP2003332494A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor deviceInfo
- Publication number
- JP2003332494A JP2003332494A JP2002138528A JP2002138528A JP2003332494A JP 2003332494 A JP2003332494 A JP 2003332494A JP 2002138528 A JP2002138528 A JP 2002138528A JP 2002138528 A JP2002138528 A JP 2002138528A JP 2003332494 A JP2003332494 A JP 2003332494A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- interposer
- semiconductor chip
- sealing
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、小型化、薄型化、
軽量化、低価格化の要求に応じた半導体集積回路等の半
導体装置の製造方法に関する。TECHNICAL FIELD The present invention relates to miniaturization, thinning,
The present invention relates to a method for manufacturing a semiconductor device such as a semiconductor integrated circuit, which meets the demand for weight reduction and price reduction.
【0002】[0002]
【従来の技術】図7及び図8に従来の半導体装置を示
す。図7は、一般に広く利用されているリードフレーム
に半導体チップを搭載し、樹脂封止した構造の半導体装
置の断面図である。半導体チップ1は、先ずリードフレ
ーム12にダイボンドされ、半導体チップ1上に形成さ
れたボンディングパッドとリードフレーム12の各リー
ドとは金線13でワイヤボンド接続され、その後、樹脂
6により封止される。このような構造の半導体装置は、
ワイヤボンディングエリアが必要なため、小型化、薄型
化、軽量化の妨げとなっていた。2. Description of the Related Art FIGS. 7 and 8 show a conventional semiconductor device. FIG. 7 is a cross-sectional view of a semiconductor device having a structure in which a semiconductor chip is mounted on a generally widely used lead frame and is resin-sealed. The semiconductor chip 1 is first die-bonded to the lead frame 12, and the bonding pad formed on the semiconductor chip 1 and each lead of the lead frame 12 are wire-bonded with a gold wire 13 and then sealed with a resin 6. . The semiconductor device having such a structure is
Since the wire bonding area is required, it has been an obstacle to downsizing, thinning and weight reduction.
【0003】小型化、薄型化、軽量化を実現したものと
して図8に示すような半導体装置がある。これは、半導
体チップ1を、セラミック基板、有機材料基板やフィル
ムテープ等のインターポーザ3にバンプ2により接続
し、樹脂封止したものである。バンプ接続を行っている
ため、ワイヤボンディングエリアが不要となり、半導体
装置を小型化等することができる。A semiconductor device as shown in FIG. 8 is one that has been made smaller, thinner, and lighter. This is a semiconductor chip 1 which is connected to an interposer 3 such as a ceramic substrate, an organic material substrate, or a film tape by bumps 2 and resin-sealed. Since the bump connection is performed, the wire bonding area is unnecessary, and the semiconductor device can be downsized.
【0004】このような構造の半導体装置は、半導体チ
ップ1の表面電極にバンプ電極2を形成した面を下にし
て、インターポーザ3上に形成された回路配線(図示せ
ず)とバンプ電極2とを接続した後、樹脂封止される。
ここで樹脂封止は、以下に示すようなアンダーフィル封
止工程とオーバーコート封止工程との2工程により行わ
れている。In the semiconductor device having such a structure, the circuit wiring (not shown) formed on the interposer 3 and the bump electrode 2 are faced down with the surface on which the bump electrode 2 is formed on the surface electrode of the semiconductor chip 1 facing downward. After connecting, resin is sealed.
Here, the resin sealing is performed in two steps including an underfill sealing step and an overcoat sealing step as described below.
【0005】樹脂封止工程は、まず、半導体チップ1と
インターポーザ3との隙間に、両者の熱膨張差による歪
みの弊害を避けるため、ディスペンサ等を用いてアンダ
ーフィル樹脂6Aを充填し、アンダーフィル封止する。
ここで、アンダーフィル樹脂には、狭い隙間に進入させ
るためシリカ等の微細なフィラーを含有するアンダーフ
ィル樹脂が用いられる。次に、半導体チップ表面の外力
による損傷や光被曝等を防ぐため、半導体チップ全体を
オーバーコート樹脂6Bにて封止する。In the resin encapsulation process, first, in order to avoid the adverse effect of distortion due to the difference in thermal expansion between the semiconductor chip 1 and the interposer 3, an underfill resin 6A is filled using a dispenser or the like, and the underfill resin 6A is filled. Seal.
Here, as the underfill resin, an underfill resin containing a fine filler such as silica is used in order to allow it to enter a narrow gap. Next, in order to prevent damage to the surface of the semiconductor chip due to external force, exposure to light, and the like, the entire semiconductor chip is sealed with the overcoat resin 6B.
【0006】[0006]
【発明が解決しようとする課題】図8に示す従来の半導
体装置の製造方法においては、アンダーフィル封止を行
う際に、毛管現象を利用するため、半導体チップ1個毎
にエッジに沿って樹脂を塗布する必要があり、ニードル
が通る間隔を確保するため、チップ間隔を狭くすること
ができず、一つのインターポーザ当たりの取れ個数が少
なくなり、半導体装置のコストが高くなってしまってい
た。さらに、アンダーフィル封止とオーバーコート封止
の2工程が必要なため、樹脂封止工程が長くなり、製造
コストが高くなってしまっていた。In the conventional method of manufacturing a semiconductor device shown in FIG. 8, a capillarity phenomenon is used when performing underfill encapsulation, so that resin is applied along the edge of each semiconductor chip. Since it is necessary to apply the coating solution, and it is not possible to narrow the chip spacing in order to secure the space through which the needles pass, the number of chips taken per interposer is small, and the cost of the semiconductor device is high. Furthermore, since two steps of underfill encapsulation and overcoat encapsulation are required, the resin encapsulation step is lengthened and the manufacturing cost is increased.
【0007】このように、2ステップの樹脂封止は、工
数面、材料面で不利な問題を抱えており、コスト高が避
けられないものにしていた。本発明は、上記問題点を解
消し、コストダウンが可能な半導体装置の製造方法を提
供するものである。As described above, the two-step resin encapsulation has disadvantages in terms of man-hours and materials, and high cost is inevitable. The present invention solves the above problems and provides a method of manufacturing a semiconductor device capable of cost reduction.
【0008】[0008]
【課題を解決するための手段】上記目的を達成するた
め、請求項1に係る発明は、複数の半導体チップを、該
半導体チップの一主面に形成された金属突起電極を介し
てインターポーザ上に設けられた回路配線にそれぞれ接
続する第1工程と、該インターポーザ上に接続された前
記半導体チップ表面及び該半導体チップと前記インター
ポーザとの間隙に液状樹脂を充填し、脱泡した後、加熱
処理を行い、樹脂を硬化させ、複数の前記半導体チップ
を前記インターポーザ上に一括封止する工程と、前記イ
ンターポーザ及び前記封止樹脂を切断し、個々の半導体
装置に個片化する第3工程とを有することを特徴とする
ものである。In order to achieve the above object, the invention according to claim 1 provides a plurality of semiconductor chips on an interposer via metal projection electrodes formed on one main surface of the semiconductor chips. A first step of connecting to each of the circuit wirings provided, a liquid resin is filled in the surface of the semiconductor chip connected on the interposer and a gap between the semiconductor chip and the interposer, and after defoaming, heat treatment is performed. And a step of curing the resin to collectively seal the plurality of semiconductor chips on the interposer, and a third step of cutting the interposer and the sealing resin to separate them into individual semiconductor devices. It is characterized by that.
【0009】また、請求項2に係る発明は、請求項1に
係る発明において、前記液状樹脂が、25℃における粘
度が10〜200Pa・s であることを特徴とするもので
ある。The invention according to claim 2 is the invention according to claim 1, characterized in that the liquid resin has a viscosity at 25 ° C. of 10 to 200 Pa · s.
【0010】[0010]
【発明の実施の形態】以下、本発明の製造方法の一実施
例について、インターポーザ3(寸法:59×91×
0.2mm)に多数個の半導体チップ1(寸法:0.8
×0.8×0.2mm)を接続して、多数個の半導体装
置(寸法:1.0×1.0×0.6mm)を製造する場
合を例にとり、図1〜図6を用い、工程順に説明する。BEST MODE FOR CARRYING OUT THE INVENTION An interposer 3 (dimensions: 59 × 91 ×) of one embodiment of the manufacturing method of the present invention will be described below.
A large number of semiconductor chips 1 (dimension: 0.8)
× 0.8 × 0.2 mm) to connect to manufacture a large number of semiconductor devices (dimensions: 1.0 × 1.0 × 0.6 mm), and FIGS. The steps will be described in order.
【0011】先ず、インターポーザ3上にバンプ2(金
属突起電極)を能動面に設けた半導体チップ1を所定の
間隔で配置し、各バンプとそれに対応するインターポー
ザ3上の回路配線(図示せず)とを接続する(図1)。
ここで、半導体チップと隣接する半導体チップとの間の
寸法は、樹脂封止後に行うダイシングの切りしろ4に、
半導体チップ1から切りしろ4までの樹脂距離5(半導
体装置の樹脂厚に相当)の2倍の寸法を加えた値に設定
する。また、インターポーザ3と半導体チップ1の能動
面までの隙間は、5μm以上に設定する。First, the semiconductor chips 1 having the bumps 2 (metal projection electrodes) provided on the active surface are arranged on the interposer 3 at predetermined intervals, and circuit wiring (not shown) on the bumps and the corresponding interposer 3 is arranged. And (Fig. 1).
Here, the dimension between the semiconductor chip and the adjacent semiconductor chip is determined by the cutting margin 4 of the dicing performed after the resin sealing.
It is set to a value obtained by adding a dimension twice the resin distance 5 (corresponding to the resin thickness of the semiconductor device) from the semiconductor chip 1 to the cutting margin 4. The gap between the interposer 3 and the active surface of the semiconductor chip 1 is set to 5 μm or more.
【0012】具体的に、切りしろ4は、従来通り165
μmとし、樹脂距離5は、従来350μmとしていたも
のを、本実施例では100μmとした。これは本発明の
製造方法では、ディペンサのニードル等を用いて行うア
ンダーフィル封止が不要であるため、半導体チップ間隔
を狭く設定できるからである。Specifically, the cutting margin 4 is 165 as in the conventional case.
The resin distance 5 was set to 350 μm in the related art, but was set to 100 μm in this embodiment. This is because the manufacturing method of the present invention does not require underfill sealing performed by using a needle of a dispenser or the like, so that the semiconductor chip interval can be set narrow.
【0013】次に、インターポーザ3と半導体チップ1
との隙間及び半導体チップ1の表面全体を樹脂6で封止
する(図2)。ここで封止には、フィラーとして粒径1
〜20μm、平均粒径4μmのシリカを含み、25℃に
おける粘度100Pa・s の一液性無溶剤の液状樹脂を用
いた。大気圧下で印刷工法により樹脂をチップ上方に塗
布した後、665Pa以下の減圧下で20分間の脱泡を
行い、樹脂塗布時に巻き込んだ気泡やインターポーザ3
と半導体チップ1との隙間に閉じ込められた気泡を除去
し、隙間に樹脂を流入させる。Next, the interposer 3 and the semiconductor chip 1
The gap between and the entire surface of the semiconductor chip 1 is sealed with resin 6 (FIG. 2). Here, for sealing, a particle size of 1 as a filler is used.
A one-liquid solvent-free liquid resin containing silica having a particle diameter of ˜20 μm and an average particle diameter of 4 μm and having a viscosity of 100 Pa · s at 25 ° C. was used. After the resin is applied to the upper part of the chip by the printing method under the atmospheric pressure, defoaming is performed for 20 minutes under the reduced pressure of 665 Pa or less, and the air bubbles and the interposer 3 caught during the resin application
The air bubbles trapped in the gap between the semiconductor chip 1 and the semiconductor chip 1 are removed, and the resin is caused to flow into the gap.
【0014】次に、100℃で1時間、150℃で2時
間の加熱処理を行い、樹脂を硬化させる。なお、樹脂の
塗布方法は、ディスペンサを用いたポッティング工法で
もよい。Next, heat treatment is performed at 100 ° C. for 1 hour and 150 ° C. for 2 hours to cure the resin. The resin application method may be a potting method using a dispenser.
【0015】以下、封止樹脂面に、印刷工法又はレーザ
ー工法によりマーキングを行い、マーク7を付ける(図
3)。次に、封止樹脂面にダイシングテープ8を貼り付
け、ダイシングブレード9によりインターポーザ3側か
らダイシングする(図4)。本実施例では、サイズ59
×91mmのインターポーザより、22個×16個を1
ブロックとして8ブロック、計2816個の半導体装置
が得られる。Thereafter, the sealing resin surface is marked by a printing method or a laser method to give a mark 7 (FIG. 3). Next, the dicing tape 8 is attached to the sealing resin surface, and the dicing blade 9 is used to perform dicing from the interposer 3 side (FIG. 4). In this embodiment, size 59
22 x 16 from the 91mm interposer
As a block, 8 blocks, that is, 2816 semiconductor devices in total are obtained.
【0016】各個片化された半導体装置をテープ8に貼
り付けた状態で、次工程の電気的試験を行う(図5)。
電気的試験はテストプローブ10を用いて行うが、多数
個を同時に試験することも可能である。次に、外観検査
を行い、梱包材11に収納する(図6)。An electrical test in the next step is conducted with the individual semiconductor devices attached to the tape 8 (FIG. 5).
The electrical test is performed using the test probe 10, but it is also possible to test a large number at the same time. Next, the appearance is inspected and stored in the packing material 11 (FIG. 6).
【0017】以上が、本発明の一実施例の概要である。
本発明では、特別のアンダーフィル封止を行うことなく
単一の液状樹脂で全体の封止を行うようにしたので、樹
脂封止工程を短縮できるという利点がある。The above is the outline of one embodiment of the present invention.
According to the present invention, the entire liquid is sealed with a single liquid resin without special underfill sealing, which has an advantage that the resin sealing process can be shortened.
【0018】また上述の実施例では、樹脂距離5を従来
の350μmから100μmに縮小することができ、半
導体装置は、従来品の1.5mm□から1.0mm□に
小型化することができた。Further, in the above-described embodiment, the resin distance 5 can be reduced from 350 μm of the conventional type to 100 μm, and the semiconductor device can be downsized from 1.5 mm □ of the conventional product to 1.0 mm □. .
【0019】なお、実施例では樹脂として、25℃にお
ける粘度100Pa・s の液状樹脂用いたが、粘度25℃
における粘度が200Pa・s 以下、10Pa・s 以上の液
状樹脂であれば、同様に利用可能である。また、これら
の粘度の液状樹脂を用いた場合も、インターポーザと半
導体チップとの隙間に入り込む粒径のフィラーを含む樹
脂を用いることで、隙間に樹脂を流入させることができ
る。なおフィラーの粒径は、インターポーザ3と半導体
チップ1の能動面までの隙間の寸法に応じて、適宜選択
すればよい。In the examples, a liquid resin having a viscosity of 100 Pa · s at 25 ° C. was used as the resin.
Liquid resins having a viscosity of 200 Pa · s or less and 10 Pa · s or more can be used in the same manner. Further, even when a liquid resin having these viscosities is used, the resin can be made to flow into the gap by using a resin containing a filler having a particle size that enters the gap between the interposer and the semiconductor chip. The particle size of the filler may be appropriately selected depending on the size of the gap between the interposer 3 and the active surface of the semiconductor chip 1.
【0020】[0020]
【発明の効果】以上説明したように、本発明の製造方法
では、樹脂封止の工程において、半導体チップ表面及び
該半導体チップとインターポーザとの隙間を含め、単一
液状樹脂を用いて封止するため、樹脂封止工程を短縮す
ることができる。また、アンダーフィルを充填するため
のディスペンサのニードルを使用する必要もないので、
半導体チップ間隔を狭くすることができ、半導体装置の
小型化や、取れ個数の増加により製造コストの低減を図
ることができる。As described above, in the manufacturing method of the present invention, in the step of resin sealing, the semiconductor chip surface and the gap between the semiconductor chip and the interposer are sealed with a single liquid resin. Therefore, the resin sealing process can be shortened. Also, since it is not necessary to use a dispenser needle to fill the underfill,
The semiconductor chip interval can be narrowed, and the manufacturing cost can be reduced by downsizing the semiconductor device and increasing the number of semiconductor devices to be taken.
【図1】 本発明の一実施例説明図である。FIG. 1 is an explanatory diagram of an embodiment of the present invention.
【図2】 本発明の一実施例の説明図である。FIG. 2 is an explanatory diagram of an embodiment of the present invention.
【図3】 本発明の一実施例の説明図である。FIG. 3 is an explanatory diagram of an embodiment of the present invention.
【図4】 本発明の一実施例の説明図である。FIG. 4 is an explanatory diagram of an example of the present invention.
【図5】 本発明の一実施例の説明図である。FIG. 5 is an explanatory diagram of an example of the present invention.
【図6】 本発明の一実施例の説明図である。FIG. 6 is an explanatory diagram of an example of the present invention.
【図7】 従来の半導体装置の説明図である。FIG. 7 is an explanatory diagram of a conventional semiconductor device.
【図8】 従来の別の半導体装置の説明図である。FIG. 8 is an explanatory diagram of another conventional semiconductor device.
1:半導体チップ、2:バンプ、3:インターポーザ、
4:切りしろ、5:樹脂距離、6:樹脂、6A:アンダ
ーフィル樹脂、6B:オーバーコート樹脂、7:マー
ク、8:ダイシングテープ、9:ダイシングブレード、
10:テストプローブ、11:梱包材、12:リードフ
レーム、13:金線。1: semiconductor chip, 2: bump, 3: interposer,
4: Cutting margin, 5: Resin distance, 6: Resin, 6A: Underfill resin, 6B: Overcoat resin, 7: Mark, 8: Dicing tape, 9: Dicing blade,
10: test probe, 11: packing material, 12: lead frame, 13: gold wire.
Claims (2)
一主面に形成された金属突起電極を介してインターポー
ザ上に設けられた回路配線にそれぞれ接続する第1工程
と、 該インターポーザ上に接続された前記半導体チップ表面
及び該半導体チップと前記インターポーザとの間隙に液
状樹脂を充填し、脱泡した後、加熱処理を行い、樹脂を
硬化させ、複数の前記半導体チップを前記インターポー
ザ上に一括封止する工程と、 前記インターポーザ及び前記封止樹脂を切断し、個々の
半導体装置に個片化する第3工程とを有することを特徴
とする半導体装置の製造方法。1. A first step of connecting a plurality of semiconductor chips to a circuit wiring provided on an interposer via metal projection electrodes formed on one main surface of the semiconductor chip, and connecting on the interposer. The surface of the semiconductor chip and the gap between the semiconductor chip and the interposer are filled with a liquid resin, and after defoaming, heat treatment is performed to cure the resin, and the plurality of semiconductor chips are collectively sealed on the interposer. And a third step of cutting the interposer and the sealing resin into individual semiconductor devices.
0〜200Pa・s であることを特徴とする請求項1記載
の半導体装置の製造方法。2. The liquid resin has a viscosity of 1 at 25 ° C.
The method for manufacturing a semiconductor device according to claim 1, wherein the method is 0 to 200 Pa · s.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006287235A (en) * | 2005-04-04 | 2006-10-19 | Infineon Technologies Ag | Package of laminated die |
KR100930156B1 (en) * | 2006-11-28 | 2009-12-07 | 가시오게산키 가부시키가이샤 | Semiconductor device and manufacturing method |
JP2015211215A (en) * | 2014-04-29 | 2015-11-24 | インテル・コーポレーション | Underfill material containing block copolymer for adjusting thermal expansion coefficient and tensile modulus |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006287235A (en) * | 2005-04-04 | 2006-10-19 | Infineon Technologies Ag | Package of laminated die |
KR100930156B1 (en) * | 2006-11-28 | 2009-12-07 | 가시오게산키 가부시키가이샤 | Semiconductor device and manufacturing method |
US7790515B2 (en) | 2006-11-28 | 2010-09-07 | Casio Computer Co., Ltd. | Semiconductor device with no base member and method of manufacturing the same |
JP2015211215A (en) * | 2014-04-29 | 2015-11-24 | インテル・コーポレーション | Underfill material containing block copolymer for adjusting thermal expansion coefficient and tensile modulus |
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