JPS587645Y2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS587645Y2 JPS587645Y2 JP3487876U JP3487876U JPS587645Y2 JP S587645 Y2 JPS587645 Y2 JP S587645Y2 JP 3487876 U JP3487876 U JP 3487876U JP 3487876 U JP3487876 U JP 3487876U JP S587645 Y2 JPS587645 Y2 JP S587645Y2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic plate
- semiconductor device
- solder
- metallized layer
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Die Bonding (AREA)
Description
【考案の詳細な説明】
本考案は半導体装置、特に、素子を放熱板に対して、絶
縁して取付けるようにした絶縁型半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to an insulated semiconductor device in which an element is mounted insulated from a heat sink.
従来、この種半導体装置は、第１図に示すように、放熱
板１上に、両面にメタライズ層３，３・・・・・・を形
成したセラミック板２を半田４を介して固着し、その上
に、半田４，４．４を介して素子５並びにリード線６，
６を固着し、素子５の電極とリード線６゜６とをコネク
タ７．７により接続したものであった。Conventionally, in this type of semiconductor device, as shown in FIG. 1, a ceramic plate 2 having metallized layers 3, 3, . On top of that, an element 5 and a lead wire 6,
6 was fixed, and the electrode of the element 5 and the lead wire 6.6 were connected by a connector 7.7.
而して、各半田４，４．・・・・・・は、セラミック板
２の両面所望個所にメタライズ層３，３．・・・・・・
を形成した後、溶融半田中に浸漬することにより形成す
るのであるが、しばしば、半田４，４．・・・・・・が
、第２図に示すように、一端に片寄って、その厚みが不
均一になり易かった。Then each solder 4, 4. . . . metallized layers 3, 3 .・・・・・・
After forming the solder 4, 4. However, as shown in FIG. 2, the thickness tended to be biased toward one end, making the thickness uneven.
このような、半田厚が不均一なセラミック板２を、放熱
板１上に半田付けしたり、その上に、素子５を半田付け
したりすると、素子５のセラミック板２への熱伝導並び
に、セラミック板２の放熱板１への熱伝導が、不均一と
なって、良好な放熱効果が得られなくなるという欠点が
あった。When such a ceramic plate 2 with uneven solder thickness is soldered onto the heat sink 1 or the element 5 is soldered thereon, heat conduction from the element 5 to the ceramic plate 2 and There is a drawback that heat conduction from the ceramic plate 2 to the heat sink 1 becomes non-uniform, making it impossible to obtain a good heat dissipation effect.
本考案は上記欠点を改良、除去するために提案されたも
ので、セラミック板上に形成するメタライズ層を島状に
細分化することを特徴とする。The present invention has been proposed to improve and eliminate the above-mentioned drawbacks, and is characterized by subdividing the metallized layer formed on the ceramic plate into island shapes.
すなわち、第３図において、同図ａは、セラミック板２
の表面側を、又同図Ｃは、セラミック板２の裏面側を示
すもので、素子５が半田付けされるメタライズ層４並び
に放熱板１に半田付けされるメタライズ層４に、十字状
又はＸ字状の除去部を設けて、夫々のメタライズ層４，
４を、４つの島状に細分化しである。That is, in FIG. 3, a shows the ceramic plate 2.
Figure C shows the back side of the ceramic plate 2, and the metallized layer 4 to which the element 5 is soldered and the metallized layer 4 to be soldered to the heat sink 1 have cross-shaped or A letter-shaped removed portion is provided to remove each metallized layer 4,
4 was subdivided into four island shapes.
このように、メタライズ層４，４を島状に細分化してお
くと、溶融半田中に浸漬した場合、第４図に示すように
、半田４，４．・・・・・・が均一な厚みで付着する。When the metallized layers 4, 4 are subdivided into island shapes in this manner, when immersed in molten solder, the solder layers 4, 4. ...is attached with a uniform thickness.
尚、上記実施例は、素子を樹脂で封止するモールド型半
導体装置に本考案を適用した場合であるが、カンケース
型の半導体装置にも適用することができる。Although the above embodiment is a case in which the present invention is applied to a mold type semiconductor device in which elements are sealed with resin, the present invention can also be applied to a can case type semiconductor device.
又、上記実施例では、素子固着部並びに放熱板への固着
部のみのメタライズ層を、島状に細分化したが、必要に
応して、リード線固着部のメタライズ層も、島状に細分
化してもよい。Furthermore, in the above embodiment, the metallized layer of only the element fixing part and the part fixed to the heat sink is subdivided into island shapes, but if necessary, the metallized layer of the lead wire fixing part can also be subdivided into island shapes. may be converted into
本考案は以上のような構成にすることにより、半田厚が
均一となって、放熱効果を良好なものとすることができ
るばかりか、メタライズ層の除去部から、半田付は時に
発生するガスを排出することができ、半田中の気泡によ
り、放熱効果の劣化も防止することができる。By configuring the present invention as described above, not only can the solder thickness be uniform and the heat dissipation effect be good, but also the gas that is sometimes generated during soldering can be removed from the removed part of the metallized layer. It is also possible to prevent deterioration of the heat dissipation effect due to air bubbles in the solder.
第１図は絶縁型半導体装置の側断面図、第２図は従来の
半導体装置に用いるセラミック板の側断面図、第３図は
本考案に係る半導体装置に用いるセラミック板の上下面
図、第４図は第３図に示すセラミック板に半田を形成し
た場合の側断面図である。
１・・・・・・放熱板、２・・・・・・セラミック板、
３・・曲メタライズ層、４・・・・・・半田、５・・間
素子。FIG. 1 is a side sectional view of an insulated semiconductor device, FIG. 2 is a side sectional view of a ceramic plate used in a conventional semiconductor device, and FIG. 3 is a top and bottom view of a ceramic plate used in a semiconductor device according to the present invention. FIG. 4 is a side sectional view when solder is formed on the ceramic plate shown in FIG. 3. 1... Heat sink, 2... Ceramic plate,
3... curved metallized layer, 4... solder, 5... inter-element.
Claims (1)
板を半田付けし、その上に素子を半田付けするものにお
いて、メタライズ層を島状に細分化して形成したことを
特徴とする半導体装置。1. A semiconductor device in which a ceramic plate having metallized layers formed on both sides is soldered onto a heat sink, and an element is soldered thereon, characterized in that the metallized layer is formed by dividing it into island shapes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3487876U JPS587645Y2 (en) | 1976-03-23 | 1976-03-23 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3487876U JPS587645Y2 (en) | 1976-03-23 | 1976-03-23 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52126758U JPS52126758U (en) | 1977-09-27 |
| JPS587645Y2 true JPS587645Y2 (en) | 1983-02-10 |
Family
ID=28494255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3487876U Expired JPS587645Y2 (en) | 1976-03-23 | 1976-03-23 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS587645Y2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60109332U (en) * | 1983-12-27 | 1985-07-25 | 富士通株式会社 | Hybrid integrated circuit device |
| JPH0834274B2 (en) * | 1989-02-10 | 1996-03-29 | 三菱電機株式会社 | Hybrid integrated circuit device for automobiles |
| CA2015336A1 (en) * | 1989-05-19 | 1990-11-19 | F. Hoffmann-La Roche Ag | Imidazodiazepines for the treatment of neurological symptoms |
| US8587019B2 (en) * | 2011-10-11 | 2013-11-19 | Ledengin, Inc. | Grooved plate for improved solder bonding |
-
1976
- 1976-03-23 JP JP3487876U patent/JPS587645Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52126758U (en) | 1977-09-27 |
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