JPS5870662A - Digital integrated circuit - Google Patents

Digital integrated circuit

Info

Publication number
JPS5870662A
JPS5870662A JP56168711A JP16871181A JPS5870662A JP S5870662 A JPS5870662 A JP S5870662A JP 56168711 A JP56168711 A JP 56168711A JP 16871181 A JP16871181 A JP 16871181A JP S5870662 A JPS5870662 A JP S5870662A
Authority
JP
Japan
Prior art keywords
signal
circuits
lines
connection lines
multilevel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56168711A
Inventor
Shunpei Kawasaki
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56168711A priority Critical patent/JPS5870662A/en
Publication of JPS5870662A publication Critical patent/JPS5870662A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/20Arrangements affording multiple use of the transmission path using different combinations of lines, e.g. phantom working

Abstract

PURPOSE:To reduce the rate of area of wirings on one chip, by decreasing the number of connection lines between circuits, through the transmission of signals between the circuits with multilevel signal. CONSTITUTION:A binary signal in N-bit on N lines of external connection lines 3a-3m on an LSI chip 1 is inputted to a signal conversion circuit 2a, where the binary signal is converted into a multilevel signal. The obtained multilevel signal is given to signal conversion circuits 2b, 2c through connection lines 5a- 5m, less than N lines, and the signal is inverted into a binary signal in N-bit and given to a processing circuit 4 and an external device.
JP56168711A 1981-10-23 1981-10-23 Digital integrated circuit Pending JPS5870662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56168711A JPS5870662A (en) 1981-10-23 1981-10-23 Digital integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56168711A JPS5870662A (en) 1981-10-23 1981-10-23 Digital integrated circuit

Publications (1)

Publication Number Publication Date
JPS5870662A true JPS5870662A (en) 1983-04-27

Family

ID=15873028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56168711A Pending JPS5870662A (en) 1981-10-23 1981-10-23 Digital integrated circuit

Country Status (1)

Country Link
JP (1) JPS5870662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9544169B2 (en) 1999-10-19 2017-01-10 Rambus Inc. Multiphase receiver with equalization circuitry

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5035373A (en) * 1973-07-27 1975-04-04
JPS5694862A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Signal transmission circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5035373A (en) * 1973-07-27 1975-04-04
JPS5694862A (en) * 1979-12-28 1981-07-31 Fujitsu Ltd Signal transmission circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9544169B2 (en) 1999-10-19 2017-01-10 Rambus Inc. Multiphase receiver with equalization circuitry
US9998305B2 (en) 1999-10-19 2018-06-12 Rambus Inc. Multi-PAM output driver with distortion compensation

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