JP2002323944A - Multilevel voltage signal bus interface circuit, functional block and integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a multilevel voltage signal bus interface circuit, with which bus width (number of signal lines) is reduced by converting n-bit parallel data to the multilevel voltage signals of 2-squared stages and supplying them to a bus, with a simple configuration, and to surely switch inputting/outputting to the bus. SOLUTION: A functional block side input/output switching part 5 supplies 2-bit data outputted from a processor 1 to a bit compressing part 6. The bit compressing part 6 converts 2-bit data to a quaternary voltage signal. A bus side input/output switching part 8 supplies the quaternary voltage signal outputted from the bit compressing part 6 to a bus BUS. The bus side input/ output switching part 8 supplies the quaternary voltage signal supplied from the side of a memory 2 through a bus converter 4 and the bus BUS to a bit expanding part 7. The bit expanding part 7 converts the quaternary voltage signal to 2-bit data. The function block side input/output switching part 6 supplies 2-bit data outputted from the bit expanding part 7 to the processor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-valued voltage signal bus interface circuit and a multi-valued voltage signal bus interface which use a multi-valued voltage signal for information transmission between functional blocks to double the bus utilization efficiency. The present invention relates to a functional block including a circuit and an integrated circuit including a multilevel voltage signal bus interface circuit.

[0002]

2. Description of the Related Art Since data transferred via a bus is binary data, it is necessary to increase the bus width in order to increase the amount of data to be transferred. As the bus width is gradually increased to, for example, 32 bits, 64 bits, 128 bits, etc., the number of pins of integrated circuit elements constituting functional blocks such as a CPU and a memory increases, and the wiring area of the bus also increases. The device becomes larger. Further, even in a one-chip microcomputer or the like in which a CPU, a memory, and the like are configured on the same chip, the bus wiring area increases as the bus width increases, and the bus wiring design becomes difficult.

In a bus configuration for transferring binary data, it is difficult to reduce the bus width. Therefore, a technique for converting the binary data into a multi-valued voltage signal and transmitting the converted signal to reduce the bus width is known (for example, Japanese Patent Application Laid-Open No. 2001-77870).

[0004]

For example, by converting 2-bit data into quaternary voltage signals and transmitting the converted signals, 2-bit information can be transmitted by one bus (signal line). Since information transmitted via the bus is bidirectional, it is necessary to switch input and output. For example, when a processor unit as a first functional block and a memory unit as a second functional block are connected via a bus, when data is supplied from the processor unit to the memory unit, the processor unit transmits parallel data. The multi-valued voltage signal is converted to a multi-valued voltage signal and supplied to the bus. The memory unit converts the multi-valued voltage signal supplied via the bus to parallel data and supplies it to the memory unit. When the memory is supplied, the memory unit converts the parallel data into a multi-valued voltage signal and supplies it to the bus, and the processor unit converts the multi-valued voltage signal supplied via the bus into parallel data and sends it to the processor unit. Need to supply. Therefore, the multi-valued voltage signal bus interface circuit for switching between the operation of converting the bit-parallel data to the multi-valued voltage signal, the operation of re-conversion from the multi-valued voltage signal to the bit-parallel data, and the switching of the input / output direction is a simple circuit. It is desired to be realized by a configuration.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to solve such a problem. Bit parallel data output from a functional block is converted into a multilevel voltage signal and supplied to a bus, and supplied via the bus. It is an object of the present invention to realize a multi-level voltage signal bus interface circuit which converts the multi-level voltage signal converted into bit parallel data and supplies it to a functional block with a simple circuit configuration. Further, switching between the operation of converting the bit-parallel data to the multi-valued voltage signal and the operation of re-converting the multi-valued voltage signal to the bit-parallel data, and the switching of the input / output direction can be reliably performed with a simple circuit configuration. It is an object to provide a multi-level voltage signal bus interface circuit.

[0006]

According to the present invention, there is provided a multi-valued voltage signal bus interface circuit according to the present invention.
a bit compression unit that converts n-bit parallel data into a multi-valued voltage signal of 2 n power stages, a bit expansion unit that converts a multi-valued voltage signal of 2 n power stages into n-bit parallel data, and outputs from the functional block A function block side input / output switching unit for supplying the n-bit parallel data obtained to the bit compression unit and supplying the n-bit parallel data output from the bit expansion unit to the function block, and a multi-valued voltage output from the bit compression unit A bus-side input / output switching unit for supplying a signal to the bus and for supplying a multi-valued voltage signal supplied via the bus to the bit developing unit.

A multi-valued voltage signal bus interface circuit according to the present invention converts n-bit (for example, 2-bit) parallel data output from a functional block (for example, a processor) into a 2 n -th power (for example, 4-level) voltage signal. And supplies it to the bus, and converts a 2 n (for example, quaternary) voltage signal supplied via the bus into parallel data of, for example, n bits (for example, 2 bits) to convert it into a functional block (for example, 2 bits). Processor). A function block side input / output switching section is provided between the function block side and the input side of the bit compression section and between the function block side and the output side of the bit expansion section,
Since the bus side input / output switching unit is provided between the output side of the bit compression unit and the bus and the input side of the bit expansion unit and the bus, the conversion operation to the multi-valued voltage signal and the re-conversion operation of the multi-valued voltage signal are performed. Switching and switching of input and output to and from the bus can be performed reliably and with a simple circuit configuration.

[0008] By configuring the bit compression section using a decoding circuit for decoding n-bit parallel data and a plurality of buffer circuits operating at different power supply voltages, the bit compression section can be easily configured.

[0009] The bit expansion section is configured by using a plurality of buffer circuits having different threshold voltages and an encoding circuit for generating n-bit parallel data based on each of these buffer circuits and outputs. The unit can be easily configured.

A multi-valued voltage signal bus interface circuit according to the present invention is interposed between a processor and a bus, and a multi-valued voltage signal bus interface circuit according to the present invention is interposed between a memory and a bus. Thus, the bus width between the processor and the memory can be reduced, and the input / output can be reliably switched.

By providing the multi-level voltage signal bus interface circuit according to the present invention in the functional block, the width of the bus connecting the functional blocks can be reduced, and the input / output can be reliably switched.

By providing the integrated circuit with the multilevel voltage signal bus interface circuit according to the present invention, the number of pins of the external bus terminals can be reduced, and the input / output can be switched reliably. Further, in an integrated circuit for a one-chip microcomputer or the like, the bus wiring area between each internal functional block can be reduced.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a multilevel voltage signal bus system using a multilevel voltage signal bus interface circuit according to the present invention. The multi-value voltage signal bus system shown in FIG. 1 converts 2-bit data transmitted between the processor 1 and the memory 2 into 4-value data between the bit converters (multi-value voltage signal bus interface circuits) 3 and 4. By transmitting a voltage signal, 2-bit information is transmitted over one bus BUS.

A first bit converter (multi-valued voltage signal bus interface circuit) 3 is arranged between the processor 1 and the bus BUS, and a second bit converter (multi-valued voltage signal bus interface circuit) 3 is connected to the bus. It is arranged between the BUS and the memory 2. The processor 1 and the first bit converter 3 are connected by two processor-side buses, a bus (bit 0) and a bus (bit 1). The bit converters 3 and 4 are connected by one bus BUS. A bus (BIT0) and a bus (BIT) are provided between the second bit converter 4 and the memory 3.
It is connected by the two memory side buses of 1). Write / read control signal R / W output from processor 1
Are supplied to the bit converters 3 and 4 and the memory 2.

The configurations of the bit converters 3 and 4 are the same. The first bit converter 3 includes a function block side input / output switching unit (parallel data input / output switching unit) 5, a bit compression unit 6, a bit expansion unit 7, and a bus side input / output switching unit (multi-valued voltage signal). An input / output switching unit) 8. The second bit converter 4 includes a bus-side input / output switching unit (multi-value voltage signal input / output switching unit) 9, a bit expansion unit 10, and a bit compression unit 11.
And a function block side input / output switching unit (parallel data input / output switching unit) 12.

A function block side input / output switching unit (parallel data input / output switching unit) 5 is provided with a write / read control signal R
If / W indicates a write state to the memory 2, the 2-bit parallel data (D0, D1) supplied from the processor 1 via each bus (bits 0, 1)
Is supplied to the bit compression unit 6. The bit compression unit 6 converts the 2-bit parallel data (D0, D1) into a quaternary voltage signal and outputs it. The bus-side input / output switching unit (multi-valued voltage signal input / output switching unit) 8 outputs a write / read control signal R /
When W indicates a write state to the memory 2, the quaternary voltage signal output from the bit compression unit 6 is supplied to the bus BUS. As a result, the 2-bit parallel data (D0, D1) output from the processor 1 becomes 4 bits.
It is converted to a voltage signal of a value and supplied to the bus BUS.

The bus-side input / output switching unit (multi-valued voltage signal input / output switching unit) 9 is supplied via the bus BUS when the write / read control signal R / W indicates a write state to the memory 2. The four-valued voltage signal is supplied to the bit developing unit 10. The bit developing unit 10 converts the quaternary voltage signal into 2-bit parallel data and outputs it. The function block side input / output switching unit (parallel data input / output switching unit) 12 outputs the 2-bit data output from the bit expansion unit 10 when the write / read control signal R / W indicates a write state to the memory 2. The parallel data is supplied to the memory 2.

When the write / read control signal R / W indicates the state of reading from the memory 2, the function block side input / output switching section (parallel data input / output switching section) 12 , 1) are supplied to the bit compression section 11 with the 2-bit parallel data (D0, D1). The bit compression unit 11 converts the 2-bit parallel data (D0, D1) into a quaternary voltage signal and outputs it. The bus-side input / output switching unit (multi-valued voltage signal input / output switching unit) 9 outputs a write / read control signal R /
When W indicates the state of reading from the memory 2, the quaternary voltage signal output from the bit compression unit 11 is supplied to the bus BUS. Thereby, the 2-bit parallel data (D0, D1) output from the memory 2 is converted into a quaternary voltage signal and supplied to the bus BUS.

When the write / read control signal R / W indicates a read state from the memory 2, the bus-side input / output switching section (multi-valued voltage signal input / output switching section) 8
The quaternary voltage signal supplied via the US is supplied to the bit developing unit 7. The bit expansion unit 7 converts the four-valued voltage signal into two
The data is converted into bit parallel data and output. Function block side input / output switching unit (parallel data input / output switching unit) 5
When the write / read control signal R / W indicates a state of reading from the memory 2, the 2-bit parallel data output from the bit developing unit 7 is
Supply to

As described above, through the bit converters 3 and 4, 2-bit data can be transmitted by one bus. When each of the bit converters 3 and 4 converts 3-bit data into an 8-valued voltage signal and converts the 8-valued voltage signal into 3-bit data again,
It is possible to transmit 3-bit data on one bus.

FIG. 2 is a circuit diagram of the bit compression unit.
The bit compression units 6 and 11 are AND gate circuits (AND gate circuits) constituting a 2-bit data decoding circuit
13, 14, 15 and each AND gate circuit 13, 14,
The OR gate circuits (NOR gate circuits) 16, 17, and 18 for selecting and specifying the output buffer circuits 19, 20, and 21 for generating the voltage output signals based on the respective outputs of the power supply voltages Va, Vb, Each output buffer circuit (tristate buffer circuit) 1 supplied with Vc
9, 20, and 21.

Each of the output buffer circuits 19, 20, and 21 is of a tri-state output type, and when the output control signal supplied to each of the control input terminals 19a, 19b, and 19c is at L level, Put the output in a high impedance state. The first output buffer circuit 19 has a power supply voltage V
a is supplied. The power supply voltage Vb is supplied to the second output buffer circuit 20. The power supply voltage Vc is supplied to the third output buffer circuit 21. Here, the power supply voltage Va is set at least twice the power supply voltage Vb and at least four times the power supply voltage Vc. The power supply voltage Va may be set to twice the power supply voltage Vb and four times the power supply voltage Vc. Further, the power supply voltages Va, Vb, and Vc may be set to have a constant voltage difference, for example, 3 volts, 2 volts, and 1 volt.

One input terminal of the first AND gate circuit 13 is supplied with an input signal D1 on the upper bit side, and the other input terminal is supplied with an input signal D0 on the lower bit side. One input terminal of the second AND gate circuit 14 is supplied with an input signal D1 on the upper bit side, and the other input terminal is supplied with a signal obtained by inverting the input signal D0 on the lower bit side via an inverter. You. One input terminal of the third AND gate circuit 15 has an input signal D1 on the upper bit side.
Is supplied through an inverter, and the other input terminal is supplied with an input signal D0 on the lower bit side.

The output of the first AND gate circuit 13 is the first
Is supplied to the input terminal of the output buffer circuit 19. Second
Of the AND gate circuit 14 is supplied to the input terminal of the second output buffer circuit 20. The output of the third AND gate circuit 15 is supplied to the input terminal of the third output buffer circuit 21. The output terminals of the output buffer circuits 20 are commonly connected.

The output of the second AND gate circuit 14 is supplied to one input terminal of the first OR gate circuit 16, and the output of the third AND gate circuit 15 is supplied to the other input terminal. Is done. The output of the first OR gate circuit 16 is connected to the control input terminal 19 of the first output buffer circuit 19.
a. The output of the first AND gate circuit 13 is supplied to one input terminal of the second OR gate circuit 17, and the third AND gate circuit 15 is supplied to the other input terminal.
Is supplied. This second OR gate circuit 17
Is the control input terminal 2 of the second output buffer circuit 20.
0a. The output of the first AND gate circuit 13 is supplied to one input terminal of the third OR gate circuit 18, and the second AND gate circuit 1 is supplied to the other input terminal.
4 outputs are provided. This third OR gate circuit 1
The output of 8 is supplied to the control input terminal 21a of the third output buffer circuit 21.

When the 2-bit input signals D0 and D1 supplied from the function block side input / output switching units 5 and 9 are both at the H level, the output of the AND gate circuit 13 is at the H level, and the other two logic signals are output. Since the outputs of the product gate circuits 14 and 15 are both at L level, the output of the OR gate circuit 16 is at H level and the output buffer circuit 19 supplies the power supply voltage V
a voltage signal (output signal) is output. When the input signal D0 on the lower bit side is at L level and the input signal D1 on the upper bit side is at H level, the output of the AND gate circuit 14 becomes H level, and the output of the OR gate circuit 17 becomes H level. Therefore, a voltage signal (output signal) of the power supply voltage Vb is output from the output buffer circuit 20.

When the input signal D0 on the lower bit side is H level and the input signal D0 on the upper bit side is L level,
The output of the AND gate circuit 15 becomes H level, and
Since the output of the OR gate circuit 18 becomes H level, the output buffer circuit 21 outputs a voltage signal (output signal) of the power supply voltage Vc. When both the input signals D0 and D1 are at L level, the output of the AND gate circuit 15 is at L level and the output of the OR gate circuit 18 is at H level. (Ground potential) is output.

As described above, the bit compressors 6, 11 correspond to the voltage Va, the voltage Vb, the voltage Vc,
A quaternary voltage signal with a voltage of 0 volt is generated and output. The four-valued voltage signal (output signal) is supplied to the bus BUS via the bus-side input / output switching units 8 and 9.

FIG. 3 is a circuit diagram of the bit expansion unit.
The bit expansion units 7 and 10 include buffer circuits 22, 23 and 24 having different threshold voltages Vth, and gate circuits 25, 26, 27 and 28 constituting an encoding circuit. The multi-valued voltage signal (output signal) V output from the bus-side input / output switching units 8 and 9 is supplied to each of the buffer circuits 22, 23 and 2.
4 respectively. The threshold voltage Vth1 of the first buffer circuit 22 is Va / 2, the threshold voltage Vth2 of the second buffer circuit 23 is Vb / 2, and the threshold voltage Vth3 of the third buffer circuit 23 is Vc. / 2. When the power supply voltage Va is set to twice the power supply voltage Vb and four times the power supply voltage Vc,
The threshold voltage Vth1 of the first buffer circuit 22 is set to an intermediate value between the voltages Va and Vb, the threshold voltage Vth2 of the second buffer circuit 23 is set to an intermediate value between the voltages Vb and Vc, and the third buffer The threshold voltage Vth3 of the circuit 23 is set to an intermediate value between the voltage vc and volt (ground potential). Further, each of the power supply voltages Va, Vb, Vc is 3 volts,
If the threshold voltage Vth1 of the first buffer circuit 22 is set to, for example, 2.5 volts, the threshold voltage Vth of the second buffer circuit 23 is set to 1 volt.
2 is set to 1.5 volts, for example, and the threshold voltage Vth3 of the third buffer circuit 23 is set to 0.5 volts, for example.

The output of the second buffer circuit 23 is supplied to one input terminal of the AND gate circuit 25 having two inputs.
The output of the third buffer circuit 24 is supplied to the other input terminal. The output terminal of the AND gate circuit 25 outputs the upper bit output signal D1.

Each output terminal of each of the buffer circuits 22, 23 and 14 is supplied to each input terminal of the three-input AND gate circuit 26. The output of the AND gate circuit 26 is supplied to one input terminal of the OR circuit 28.

A signal obtained by inverting the output signal of the first buffer circuit 22 through an inverter is supplied to a first input terminal of a three-input AND gate circuit 27, and a second input terminal is supplied to a second input terminal. A signal obtained by inverting an output signal of the buffer circuit 23 through an inverter is supplied, and an output signal of the third buffer circuit 24 is supplied to a third input terminal. The output of the AND gate circuit 27 is supplied to the other input terminal of the OR circuit 28. Then, an output signal D1 on the lower bit side is output from the output terminal of the OR circuit 28.

Therefore, the multi-valued voltage signal (output signal) V
Is Va, the respective buffer circuits 22,
The outputs of 23 and 24 all become H level. Therefore, the output of the AND gate circuit 25 becomes H level, the output of the AND gate circuit 26 becomes H level, and the output of the OR gate circuit 28 becomes H level. As a result, when the voltage level of the multilevel voltage signal (output signal) V is Va, each of the output signals D0 and D1 becomes H level.

When the voltage level of the multilevel voltage signal (output signal) V is Vb, the output of the buffer circuit 22 goes low and the outputs of the other two buffer circuits 23 and 24 both go high. Therefore, the output of the AND gate circuit 25 is at L level and the outputs of the other two AND gate circuits 25 are both at H level.
Is at H level, the outputs of the other AND gate circuits 26 and 27 are both at L level, and the output of the OR gate circuit 28 is at L level. Thus, when the voltage level of the multi-level voltage signal (output signal) V is Vb, the output signal D1 of the upper bit side becomes H level and the output signal D0 of the lower bit side becomes L level.

When the voltage level of the multilevel voltage signal (output signal) V is Vc, the first and second buffer circuits 22 and
The outputs of both become low, and the output of the third buffer circuit 24 becomes high. Therefore, the output of the AND gate circuit 25 becomes L level. Further, since the output of the AND gate circuit 27 becomes H level, the output of the OR gate circuit 28 becomes H level. Accordingly, when the voltage level of the multi-level voltage signal (output signal) V is Vc, the output signal D1 of the upper bit side becomes L level and the output signal D0 of the lower bit side becomes H level.

When the voltage level of the multi-level voltage signal (output signal) V is 0 volt (ground potential), the outputs of the buffer circuits 22, 23, and 4 are all at L level. Therefore, the output of the AND gate circuit 25 becomes L level. Since both the output of the AND gate circuit 26 and the output of the AND gate circuit 27 are at L level, the output of the OR gate circuit 28 is at L level. Thus, when the voltage level of the multi-level voltage signal (output signal) V is 0 volt (ground potential), the output signal D1 of the upper bit side
And the output signal D0 on the lower bit side is at L level.

As described above, the bit developing units 7 and 10 convert the quaternary voltage signal into 2-bit output signals D0 and D1, and output the signals. The output signals D0 and D1 are sent to the processor 1 and the memory 2 via the function block side input / output switching units 5 and 12, respectively.
And so on.

FIG. 4 is an explanatory diagram showing the operation of the bit compression section and the bit expansion section. When the upper bit D1 of the input signal is 0 and the lower bit D0 of the input signal is 0, the bit compressors 6 and 11 output 0 from the third output buffer circuit 21 to 0.
And outputs a multi-level voltage signal of 0 volt (ground potential). Note that the minus sign in the column of each buffer output of the bit compression unit in FIG. 4 indicates that the buffer output is in a high impedance state. When the voltage level of the multi-valued voltage signal is 0 volt, each buffer circuit 2
The outputs of 2, 23 and 24 are all logic 0 (L level), and the output signals D1 and D0, which are decoded outputs, are both logic 0.

When the upper bit D1 of the input signal is 0 and the lower bit D0 of the input signal is 1, the bit compression units 6 and 11 operate the third output buffer circuit 2 operating at the power supply voltage Vc.
The output of 1 becomes 1, and a multi-level voltage signal of voltage Vc is output. When the voltage level of the multi-level voltage signal is Vc, the output of the third buffer circuit 24 of the bit expansion units 7 and 10 becomes logic 1 (H level), and the upper bit D1 of the output signal
Is 0 and the lower bit D0 is 1.

When the upper bit D1 of the input signal is 1 and the lower bit D0 of the input signal is 0, the bit compressors 6 and 11 operate the second output buffer circuit 2 operating at the power supply voltage Vb.
The output of 0 becomes 1 and a multi-valued voltage signal of voltage Vb is output. When the voltage level of the multi-valued voltage signal is Vb, the output of the second buffer circuit 23 of the bit expansion units 7 and 10 becomes logic 1 (H level), and the upper bit D1 of the output signal
Becomes 1 and the lower bit D0 becomes 0.

When the upper bit D1 of the input signal is 1 and the lower bit D0 of the input signal is 1, the bit compression units 6 and 11 operate the first output buffer circuit 1 operating at the power supply voltage Va.
The output of 9 becomes 1 to output a multi-value voltage signal of voltage Va. When the voltage level of the multi-level voltage signal is Va, the output of the first buffer circuit 22 of the bit expansion units 7 and 10 becomes logic 1 (H level), and the upper bit D1 of the output signal
Becomes 1 and the lower bit D0 becomes 1.

FIG. 2 shows a bit compression unit for converting 2-bit data into a quaternary voltage signal, and FIG. 3 shows a bit expansion unit for re-converting a quaternary voltage signal into 2-bit data.
The bit compression unit may convert the n-bit data into a 2 n multi-level voltage signal, and the bit expansion unit may re-convert the 2 n multi-level voltage signal into n-bit data.

FIG. 5 is an explanatory diagram showing the operation of the bit compression section for converting 3-bit data into an 8-valued voltage signal and the operation of the bit expansion section for re-converting the 8-valued voltage signal into 3-bit data. This bit compression section includes seven output buffer circuits (A, B, C, D, E,
F, G). Each output buffer circuit (A, B, C,
D, E, F, G) include power supply voltages Va, Vb, Vc, V
d, Ve, Vf, and Vg are supplied, respectively. here,
Each power supply voltage is Va ≧ 2 * Vb ≧ 4 * Vc ≧ 8 * Vd ≧
It is set so as to satisfy the relationship of 16 * Ve ≧ 32 * Vf ≧ 64 * Vg. Note that each power supply voltage is Va = 2 *
Vb = 4 * Vc = 8 * Vd = 16 * Ve = 32 * Vf =
The relationship may be set to 64 * Vg. Further, each power supply voltage is, for example, Va = 7 volts, Vb = 6 volts, Vc = 5
The voltage may be set to have a constant voltage difference such as volts, Vd = 4 volts, Ve = 3 volts, Vf = 2 volts, and Vg = 1 volt.

The bit developing section has different threshold voltages.
Buffer circuits (a, b, c, d, e, f, g). The threshold voltage of the first buffer circuit a is Va / 2
The threshold voltage of the second buffer circuit b is Vb / 2
The threshold voltage of the third buffer circuit c is Vc / 2
The threshold voltage of the fourth buffer circuit d is Vd / 2
The threshold voltage of the fifth buffer circuit e is Ve / 2
The threshold voltage of the sixth buffer circuit f is Vf / 2
The threshold voltage of the seventh buffer circuit g is Vg / 2
Are set respectively. Note that the threshold voltage of the first buffer circuit a is an intermediate value between the voltages Va and Vb, the threshold voltage of the second buffer circuit b is an intermediate value between the voltages Vb and Vc, The threshold voltage of the buffer circuit c is the intermediate value between the voltages Vc and Vd, the threshold voltage of the fourth buffer circuit d is the intermediate value between the voltages Vd and Ve, and the fifth buffer circuit e Is the threshold voltage V
e and the threshold value of the voltage vf, the threshold voltage of the sixth buffer circuit f is the intermediate value of the voltage Vf and the voltage Vg, and the threshold voltage of the seventh buffer circuit g is the voltage Vg and 0 volt. (Ground battery).

The bit compression section outputs a 3-bit input signal D
2, 8 values (Va, Vb, Vc, V
d, Ve, Vf, Vg and 0 volt (ground potential)
And outputs the voltage signal. The bit expansion unit determines the voltage level of the voltage signal of eight values (Va, Vb, Vc, Vd, Ve, Vf, Vg and 0 volt (ground potential)) and converts the 3-bit output signals D2, D1, D0. Generate and output. With such a configuration, 3-bit information can be transmitted by one bus (signal line).

FIG. 6 is a diagram showing a specific example of a functional block including a multi-level voltage signal bus interface circuit according to the present invention. By incorporating the bit converter 3 in the processor 100, the external bus input / output terminals of the processor 100 can be reduced. Similarly, by incorporating the bit converter 4 in the memory 200, the external bus input / output terminals of the memory 200 can be reduced.

In a one-chip microcomputer integrated circuit having a processor, a RAM, a ROM, and the like mounted on the same chip, each functional block of the processor, the RAM, the ROM, and the like includes the bit converter according to the present invention. Thus, the bus width between the functional blocks such as the processor, the RAM, and the ROM can be reduced. Thereby, the wiring area of the internal bus can be reduced.

[0048]

As described above, the multi-level voltage signal bus interface circuit according to the present invention comprises a bit compression section for converting n-bit parallel data into a multi-level voltage signal having 2 @ n power levels, and a 2 @ n power level. A bit decompressor for converting the multi-level voltage signal of the stage into n-bit parallel data; and a function for supplying the n-bit parallel data output from the functional block to the bit compressor and for n-bit parallel data output from the bit decompressor Function block side input / output switching unit that supplies to the block, and bus side that supplies the multi-valued voltage signal output from the bit compression unit to the bus and supplies the multi-valued voltage signal supplied via the bus to the bit expansion unit With the configuration including the input / output switching unit, the bus width (number of signal lines) connecting the functional blocks can be reduced, and the multi-value voltage signal can be reduced. Switching of the conversion operation and re-conversion of the multi-level voltage signal, and the switching of the input and output to the bus can be performed by reliably and simple circuit structure.

It should be noted that the bit compression section can be easily configured by using a decoding circuit for decoding n-bit parallel data and a plurality of buffer circuits operating at different power supply voltages. it can.

Further, the bit developing section is constituted by using a plurality of buffer circuits having different threshold voltages and an encoding circuit for generating n-bit parallel data based on each of these buffer circuits and the output. The bit expansion unit can be easily configured.

For example, a multi-level voltage signal bus interface circuit according to the present invention is provided between a processor and a bus, and a multi-level voltage signal bus interface circuit according to the present invention is provided between a memory and a bus. Thus, the bus width between the processor and the memory can be reduced, and the input / output can be reliably switched.

Further, by providing the multi-level voltage signal bus interface circuit according to the present invention in the functional block, the width of the bus connecting between the functional blocks can be reduced, and the input / output can be reliably switched.

Further, by providing the multi-level voltage signal bus interface circuit according to the present invention in the integrated circuit, the number of pins of the external bus terminals can be reduced, and the input / output switching can be performed reliably. Further, in an integrated circuit for a one-chip microcomputer or the like, the bus wiring area between each internal functional block can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multilevel voltage signal bus system using a multilevel voltage signal bus interface circuit according to the present invention.

FIG. 2 is a circuit configuration diagram of a bit compression unit.

FIG. 3 is a circuit configuration diagram of a bit expansion unit.

FIG. 4 is an explanatory diagram illustrating operations of a bit compression unit and a bit expansion unit.

FIG. 5 is an explanatory diagram illustrating an operation of a bit compression unit that converts 3-bit data into an 8-level voltage signal and an operation of a bit expansion unit that re-converts an 8-level voltage signal into 3-bit data.

FIG. 6 is a diagram showing a specific example of a functional block including a multi-level voltage signal bus interface circuit according to the present invention.

[Explanation of symbols]

1,100 processor 2,200 memory 3,4 bit converter (multi-valued voltage signal bus interface circuit) 5,12 function block side input / output switching unit 6,11 bit compression unit 7,10 bit expansion unit 8,9 bus side I / O switching unit 13, 14, 15 AND gate circuit constituting decoding circuit 16, 17, 18 OR gate circuit 19, 20, 21 Output buffer circuit (tristate buffer circuit) 22, 23, 24 Buffer circuit 25, 26, 27 AND gate circuit forming an encoding circuit 28 OR gate circuit forming an encoding circuit BUS Bus through which a multi-valued voltage signal is transmitted

Claims (7)

[Claims] 1. A bit compression section for converting n-bit parallel data into a multi-valued voltage signal having a power of 2 n, and a bit expanding section for converting a multi-valued voltage signal having a power of 2 n into n-bit parallel data. A function block side input / output switching unit that supplies n-bit parallel data output from the function block to the bit compression unit and supplies n-bit parallel data output from the bit expansion unit to the function block; A bus-side input / output switching unit that supplies the multi-valued voltage signal output from the compression unit to the bus and supplies the multi-valued voltage signal supplied via the bus to the bit expansion unit. Multi-level voltage signal bus interface circuit. 2. The multi-value voltage signal bus according to claim 1, wherein said bit compression unit includes a decoding circuit for decoding n-bit parallel data, and a plurality of buffer circuits operating at different power supply voltages. Interface circuit. 3. The bit expansion section includes a plurality of buffer circuits having different threshold voltages, and an encoding circuit for generating n-bit parallel data based on each of the buffer circuits and an output. The multi-level voltage signal bus interface circuit according to claim 1. 4. The multi-level voltage signal bus interface circuit according to claim 1, wherein said functional block is a processor. 5. The multi-level voltage signal bus interface circuit according to claim 1, wherein said functional block is a memory. 6. A functional block comprising the multi-level voltage signal bus interface circuit according to claim 1. 7. An integrated circuit comprising the multi-level voltage signal bus interface circuit according to claim 1.