JPS5694862A - Signal transmission circuit - Google Patents

Signal transmission circuit

Info

Publication number
JPS5694862A
JPS5694862A JP17194879A JP17194879A JPS5694862A JP S5694862 A JPS5694862 A JP S5694862A JP 17194879 A JP17194879 A JP 17194879A JP 17194879 A JP17194879 A JP 17194879A JP S5694862 A JPS5694862 A JP S5694862A
Authority
JP
Japan
Prior art keywords
levels
binary signals
piece
transmission line
signal transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17194879A
Other languages
Japanese (ja)
Inventor
Miki Tanaka
Yasuhisa Sugao
Masayoshi Kimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17194879A priority Critical patent/JPS5694862A/en
Publication of JPS5694862A publication Critical patent/JPS5694862A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To regenerate two binary signals, by transmitting the four levels corresponding to the combinations of four different levels of the two binary signals to a piece of transmission line and then comparing the reception level with the three levels. CONSTITUTION:The transmission terminal DV transmits the four combinations (HH, HL, LH and LL) of the levels of the two binary signals A and B to a piece of transmission line SL in correspondence to the 1st-4th levels L1-L4(L1>L2>L3> L4). The reception terminal RV has the comparators COMP1-COMP4 to identify the reception signal level based on the 1st-3rd reference levels VA, VB and VC (L1>VA>L2, L2>VB>L3 and L3>VC>L4) to obtain the 1st and 2nd binary signals A and B. As a result, the two binary signals are transmitted with a piece of transmission line and in an asynchronous way.
JP17194879A 1979-12-28 1979-12-28 Signal transmission circuit Pending JPS5694862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17194879A JPS5694862A (en) 1979-12-28 1979-12-28 Signal transmission circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17194879A JPS5694862A (en) 1979-12-28 1979-12-28 Signal transmission circuit

Publications (1)

Publication Number Publication Date
JPS5694862A true JPS5694862A (en) 1981-07-31

Family

ID=15932758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17194879A Pending JPS5694862A (en) 1979-12-28 1979-12-28 Signal transmission circuit

Country Status (1)

Country Link
JP (1) JPS5694862A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870662A (en) * 1981-10-23 1983-04-27 Hitachi Ltd Digital integrated circuit
JPS5997258A (en) * 1982-11-24 1984-06-05 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Multiple level communication circuit for communicating digital signal between integrated circuit
JPS62185438A (en) * 1986-02-10 1987-08-13 Hitachi Ltd Multi-value input/output method
US5394261A (en) * 1990-09-25 1995-02-28 Canon Kabushiki Kaisha Optical communication system and transmitting apparatus for use therein
JP4841786B2 (en) * 2000-01-06 2011-12-21 ラムバス・インコーポレーテッド Low latency multilevel communication interface
JP2012126046A (en) * 2010-12-16 2012-07-05 Konica Minolta Holdings Inc Inkjet recording apparatus and method for generating drive waveform signal

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5870662A (en) * 1981-10-23 1983-04-27 Hitachi Ltd Digital integrated circuit
JPS5997258A (en) * 1982-11-24 1984-06-05 インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン Multiple level communication circuit for communicating digital signal between integrated circuit
JPH0339425B2 (en) * 1982-11-24 1991-06-13 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62185438A (en) * 1986-02-10 1987-08-13 Hitachi Ltd Multi-value input/output method
US5394261A (en) * 1990-09-25 1995-02-28 Canon Kabushiki Kaisha Optical communication system and transmitting apparatus for use therein
JP4841786B2 (en) * 2000-01-06 2011-12-21 ラムバス・インコーポレーテッド Low latency multilevel communication interface
JP2012126046A (en) * 2010-12-16 2012-07-05 Konica Minolta Holdings Inc Inkjet recording apparatus and method for generating drive waveform signal

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