SU930665A1 - Binary-coded decimal-to-decimal code converter - Google Patents

Description

(5k BINARY DECIMAL CODE TO DECIMAL CONVERTER

one

The invention relates to the field of automation and computing.

There are known converters of binary-decimal code to decimal, containing transistors, inverters, AND, AND-NOT and OR Q elements.

The closest to the invention is a converter of a binary-decimal code to a decimal, containing four input buses and ten output buses, each of which is connected to the collector of the same-name transistor, while the first input bus is connected to the input of the first inverter, the output of which It is connected to the bases of odd transistors, and through the second inverter is connected to the bases of zero and even transistors, as well as the AND-NOT element. the output of which is connected to the emitters of the zero and first transistors, the first input to the second input bus, the second input to the third input bus

and the direct input of the main element OR, and the third input is connected to the fourth input bus, the inverse input of the main element OR is connected to the output of the AND element, and its output is connected to the emitters of the sixth and seventh transistors 2.

A disadvantage of the known devices is a large power consumption.

The purpose of the invention is to reduce the power consumption of the converter of the binary-decimal code to the decimal.

This goal is achieved by the fact that in the converter of a binary-decimal code into a decimal, 1 containing four input buses and ten output buses, each of which is connected to the collector of a single transistor, the first input bus is connected to the input of the first investor, OUTPUT — of which is directly connected to the bases of odd transistors, and through the second inverter - to the bases of zero and even transistors.

and the NAND element whose output is connected to the emitters of the zero and first transistors, the first output to the second input bus, the second input to the third input bus and the forward input of the main OR element, and the third input is connected to the fourth input bus, the inverse input the main element OR is connected to the output of the element AND, and its output is connected to the emitters of the sixth and seventh transistors; two implication elements are introduced; the direct input of the first of which is connected to the inverse input of the second implication element and the second input bus; The second input is connected to the forward input of the second implication element and the third input bus, and the output is connected to the emitters of the second and third transistors and the first input of the And element, the second input of which is connected to the output of the second implication element and to the emitters of the fourth and fifth transistors, The fourth input bus is connected to the emitters of the eighth and ninth transistors.

The drawing shows a functional diagram of a converter of a binary-decimal code into a decimal.

The device contains input buses, output buses 5-1, each of which is connected to the collector of the transistor 15-2 of the same name, input bus 1 is connected to the input of inverter 25, the output of which is directly connected to the bases of odd transistors 1b, 18, 20, 22, 2k and Through the inverter 26 - with the bases of zero 15 and even 17, 19, 21, 23 transistors, the element AND-NOT 27, the output of which is connected to the emitters of transistors 15 and 16, the first input - to the input bus 2, the second input - to the input bus 3 and the direct input of the element OR 25, and the third input is connected to the input bus t, the inverse input the element OR 28 is connected to the output of the element AND 29, and its output is connected to the emitters of the transistors 21 and 22, the implication elements 30 and 31, the direct input of the first of which is connected to the inverse input of the element 31 and the input bus 2, the inverse input is connected to the direct the input element 3V and the input bus 3, and the output is connected to the emitters of transistors 17 and 18 and the first input element And 29,

The second input of which is connected to the output of the element 31 and the emitters of the transistors 19 and 20, the input bus is connected to the emitters of the transistors 23 and 2.

The device will work as follows. When supplying, for example, a single logic level to the input buses l-tj, the outputs of the inverter 25 and the IS-NOT element 27 form a zero logic level, as a result of which only the transistor 15 will be opened. The P0th supply, for example, a single logic level on the input bus 1 and / 4 and zero logic level on the input bus 2 and 3, at the outputs of the elements 30 and 31 and the element 29 is formed a single logic level. And as a result of this, we have zero logic level at the output of the OR 28 element and only the transistor 21 opens.

Thus, the introduction of additional OR elements and new constructive connections makes it possible to reduce the power consumption of the proposed converter of the binary-decimal code to the decimal in comparison with the known one.

invention formula

The converter of the binary-decimal code to the decimal, containing four input buses and ten output buses, each of which is connected to the collector of the transistor of the same name, while the first input bus is connected to the input of the first inverter whose output is directly connected to the bases of odd transistors, and through the second inverter - with bases of zero and even transistors, as well as the NAND element, the output of which is connected to the emitters of the zero and first transistors, the first input to the second input bus, the second input - to the third input the bus and the forward input of the main element OR, and the third input is connected to the fourth input bus, the inverse input of the main element 59 OR is connected to the output of the AND element, and its output is connected to the emitters of the sixth and seventh transistors, in order to reduce power consumption There are two implication elements, the direct input of the first of which is connected to the inverse input of the second implication element and the second input bus, the inverse input is connected to the direct input of the second implication element and the third input bus, and the output connected to the emitters of the second and third transistors and the first input element And, the second input

t L and a and It L1 G Vl V J «U

  HZ U

and

,

j L

g

tt ii o

tzd 5 of which is connected to the output of the second implication element and to the emitters of the fourth and fifth transistors, while the fourth input bus is connected to the emitters of the eighth and ninth transistors. Sources of information taken into account in the examination 1.Bukreev I.N. Nikroelectronic circuits of digital devices. M. Soviet Radio, 1975, p.311., 2. Analog and digital integrated circuits. Ed. Yakubovsky S.V. N., Soviet Radio, 1979, p. 7, fig. 3.1.27 (prototype).

Claims (3)

claims A binary-decimal to decimal code converter containing four input buses and ten output buses, each of which is connected to the collector of the transistor of the same name, with an atom, the first input bus 45 is connected to the input of the first inverter, the output of which is directly connected to the bases of odd transistors and through the second inverter with the bases of zero and even transistors, and 50 also an NAND element, the output of which is connected to the emitters of the zero and first transistors, the first input to the second input bus, the second to od - to the third input bus 55 and the direct input of the main element OR, and the third input is connected to the fourth input bus, the inverse input of the main element 5 930665 OR is connected to the output of the element And, and its output is connected to the emitters of the sixth and seventh transistors, characterized in that, in order to reduce power consumption, two implication elements are introduced, the direct input of the first of which is connected to the inverse input of the second implication element and the second input bus, the inverse input is connected to the direct input of the second implication element and its input bus, and the output is connected to the emitters of the second and third transistors and the first input of the And element., the second input 6 of which is connected to the output of the second implication element and to the emitters of the fourth and fifth transistors, while the fourth input bus is connected to the emitters of the eighth and ninth transistors. 4 Sources of information taken into account in the examination 1. Bukreev I.N. et al. Microelectronic ^10- circuit digital devices. M., Soayatstkoe Radis ¹¹ , 1975 ”p.311. 2. Analog and digital integrated circuits. Ed. Yakubovsky S.V. I., ’’ Soviet Radio, 1979 ”p. 74, fig. 3-1.27 (prototype).