JP2003188929A - Semiconductor integrated circuit and data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which is equipped with in-out interface capable of transacting ternary signal without increasing circuit scale or power consumption. <P>SOLUTION: This semiconductor integrated circuit is equipped with an output interface 10 capable of setting each of a plurality of output terminals in some state of a plurality of signal levels or in high impedance, and this is constituted so that the output data may be outputted from the output interface 10, constituted of a multivalued signal taking either the plurality of signal levels or the high impedance. Furthermore, this is constituted so that the signal lines L1 and L2 may be inputted into the input interface 20, being set to a first potential Vtt by the terminating resistor connected to the signal line, when the output of the output interface 10 is in high impedance. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique useful when applied to a data transfer system, for example, an electronic device having a plurality of logic devices mounted therein, and an LSI (Large Scale Integrated Circuit) having a plurality of logic modules integrated therein. Alternatively, the present invention relates to a technique useful for utilizing in a communication network or the like in which a plurality of communication devices are connected via a communication cable.

[0002]

2. Description of the Related Art In recent years, as the amount of data handled by electronic devices has increased, the number of input / output pins of electronic devices and the number of signal lines of buses provided inside electronic devices and LSIs have increased. Such an increase in the number of input / output pins and an increase in the bus width cause the electronic device and the electronic substrate on which the electronic device is mounted to become large in size, resulting in a high manufacturing cost. In order to improve the throughput of data transfer without increasing the number of signal lines, a method of increasing the data transfer frequency or converting the data signal into multi-valued data and transferring it is possible. The present inventors have studied a method of converting a data signal into a multi-valued one and transferring it. As a conventional technique for converting a data signal into multiple levels, there is, for example, a multilevel logic device, a bus system and a network system disclosed in Japanese Patent Laid-Open No. 2000-47768.

[0003]

Most of the conventional multi-valued techniques are techniques of four-valued data signals.
In the output interface, the potential for multi-valued is prepared, and any one of the potentials is output to the signal line. However, in order to stably prepare a large number of levels of potential, a regulator circuit or the like is required, and the circuit scale becomes large, and there is a problem that power consumption increases in order to stably supply a large number of levels of potential. Let

On the signal input side, an AD converter for identifying a multilevel signal is required.
The converter has a circuit configuration different from that of a binary logic circuit and has a drawback that it is weak against noise as compared with a binary logic circuit. In particular, when the signal has four or more values, the noise resistance of the AD converter for identifying it becomes a problem in data transfer.

The object of the present invention is to improve the data transfer rate without increasing the input / output pin and the bus width by using the multi-valued signal, and to reduce the regulator circuit etc. required for generating the multi-valued signal. The object is to provide a semiconductor integrated circuit and a data transfer system capable of reducing the circuit scale and power consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, an output interface capable of setting each of the plurality of output terminals to any of a plurality of signal levels or a high impedance state,
The output data is composed of a multi-valued signal having any one of the plurality of signal levels and the high impedance, and is output from the output interface. Then, when the output of the output interface is high impedance, the signal line is set to the first potential by the terminating resistor connected to the signal line and is input to the input interface. According to such means, since the output high impedance state is used as one of the multi-valued signals, a regulator circuit or the like for generating the output level is not required, and the circuit scale and power consumption are reduced accordingly. Can be planned.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a data transfer system to which the present invention is preferably applied. FIG. 2 is a data chart showing the relationship between the ternary signal and the data value adopted in this data transfer system. In the data transfer system of FIG. 1, for example, one of the two device ICs (semiconductor integrated circuits) 1 and 2 has an output interface 10 and the other input interface 20 and a plurality of signal lines L1.
It is constructed by connecting with L2. The output interface 10 includes tri-state buffers 11a and 11b provided corresponding to the signal lines L1 and L2, and a ternary conversion circuit 14 that converts a data value represented by binary logic into a ternary form. And are provided.

Tristate buffers 11a and 11b
Is, for example, a high-level potential Vo3 that is a power source potential of the positive electrode.
And a low level potential Vo1 which is the power source potential of the negative electrode, and a circuit capable of setting the output node to a high impedance. For example, the positive and negative power source terminals of the CMOS inverter are respectively MOSFET switches. It is realized by a configuration that enables switching control of connection or disconnection with a power source using the above. The tri-state buffers 11a and 11b are conventionally provided for the purpose of avoiding collision of input / output signals or bus-connected interfaces in an I / O interface for inputting / outputting signals using the same pin. Is similar to that provided for the purpose of avoiding collision of output signals between a plurality of devices, and also has a combination of these functions.

The ternary conversion circuit 14 performs conversion into a ternary form according to a predetermined conversion rule.
The value form signal is transmitted to each of the tri-state buffers 11a and 11a.
It is formed from two kinds of binary signals respectively output to the input terminal u1 and the control terminal u2 of b. Then, the tri-state buffers 11a and 11a are generated by the signal from the control terminal u2.
b is set to either the output high impedance or the normal output, and the output of the tristate buffers 11a and 11b is set to the high level or the low level by the signal of the input terminal u1.

The conversion rule to the ternary form is, for example, as shown in the data chart of FIG. 2, the value of the data constituted by a plurality of binary signals (in FIG. 2, the decimal data value "0 to 7"). And the combination of the output states of the plurality of tri-state buffers 11a and 11b are defined to correspond one-to-one.
Further, a combination in which all of the tri-state buffers 11a and 11b of one output interface 10 have high impedance is determined to be excluded from the combination representing the signal configuration of transfer data. For example, in this embodiment, since the output interface is composed of two tri-state buffers 11a and 11b, the combination in which both of them are high impedance is excluded from the signal structure representing data. When there are three or more, only cases where all three have high impedance are excluded.

Further, the ternary conversion circuit 14 has a high impedance control signal HiZ input from an internal control circuit or the like.
Based on the above, the control terminals of all the output circuits 11a and 11b are set to the high level, and all the output circuits 11a and 11b are set to the output high impedance. With this function, for example, in the case of an input / output interface configured to perform signal input / output with the same pin, collision of input / output signals can be avoided, or output signals can be output between a plurality of devices connected by a bus. It is possible to avoid the collision. The reason why the combination of high impedance of all terminals is excluded from the signal configuration representing data is that in the case of high impedance of all terminals, there is no output as described above.

On the other hand, the input interface 20 includes two input circuits 2 provided corresponding to the respective signal lines L1 and L2.
1a, 22b, and a binary conversion circuit 24 for converting the signals in the ternary form received from these input circuits 21a, 22b into a binary signal by performing the reverse conversion of the ternary conversion circuit 14 described above. .

FIG. 3 is a detailed circuit diagram of the input circuit 21a shown in FIG. 1, and FIG. 4 is a diagram for explaining the reference potentials Va, Vb and Vtt used in the input circuit 21a. The input circuits 21a and 21b are ternary-input AD converters that identify whether the input signal belongs to the high level V3 (FIG. 4), the low level V1 or the intermediate level V2, and a reference for generating the reference voltages Va and Vb. Voltage generation circuit (resistors R1, R
2, R3) and comparators OPh and OPl for comparing the input signal with these reference voltages Va and Vb. The input circuits 21a and 21b have one end connected to the signal lines L1 and L2, respectively, and the other end connected to an intermediate level reference voltage (first potential) Vtt.
tm is attached.

The terminating resistor Rtm is connected to the input circuit 2
In addition to being provided in 1a and 21b, for example, it may be provided in the output interface 10 or may be provided on the electronic substrate on which the signal lines L1 and L2 are formed. According to the output interface 10 and the input interface 20 configured as described above, the signal of the high level Vo3 or the low level Vo1 output from the output circuit 11a is not terminated.
It is input to the input circuit 21a as a signal of high level V3 or low level V1 which is slightly affected by m or the like. Further, the high impedance signal output from the output circuit 11a is input to the input circuit 21a as a signal of the intermediate potential V2 supplied to the signal line L1 via the terminating resistor Rtm. This enables input / output of a ternary signal between the output interface 10 and the input interface 20.

FIG. 5 shows a circuit diagram of another example of the input circuit constituting the input interface 20. The input circuit 21a 'is configured by using two types of CMOS inverters INVh and INVl having different threshold voltages Vth. The inversion threshold voltage Vth of the one inverter INVh is the reference voltage Vb, and the inversion threshold voltage Vth of the other inverter INVl is the reference voltage Va.
Is formed. As a result, similar outputs ob1 and ob2 can be obtained by substantially the same operation as the circuit of FIG.

FIG. 6 shows an example of the configuration of a data transfer system in which a plurality of devices provided with the above-mentioned input / output interface are connected. This system includes, for example, peripheral circuits 70 and 80 such as a communication processing device and a display processing device.
And a controller 60 for controlling the operation of these peripheral circuits 70, 80 are connected via an address bus B1 and a data bus B2. The controller 60 and the peripheral circuits 70 and 80 are semiconductor LSIs formed and packaged on one semiconductor chip such as single crystal silicon, and the buses B1 and B2 are LSIs.
Is provided on a printed wiring board on which is mounted. Alternatively, the controller 60, the peripheral circuit 70,
The bus 80 and the buses B1 and B2 may be regarded as, for example, components of a system LSI integrated on one semiconductor chip.

The controller 60 and the peripheral circuits 70 and 80 are provided with ternary interfaces I3 and I3O having the output interface 10 and the input interface 20 for inputting and outputting the above-mentioned ternary signals, and these ternary interfaces I3. , I3O are connected to the buses B1 and B2, respectively. More specifically, the ternary interface I3O of the controller 60 connected to the address bus B1 has only the output interface 10 that outputs an address, and the other ternary interface I3 includes the output interface 10 and the input interface 20. The input terminal and the output terminal are provided in common. Also, only one terminating resistor Rtm is connected to each signal line.

According to the data transfer system thus constructed, the bus width can be reduced to about ⅔ or less of the conventional binary logic even when the data amount is made equal. For example, 128 buses in binary logic can be 81 buses in ternary logic. Therefore, even if the amount of data is the same as the conventional one, it is possible to reduce the number of terminals and the bus width of the device (or macro cell) to 2/3 or less of the conventional one, and thereby the device (or macro cell) or the bus. It is possible to reduce the occupied area and power consumption.

Also, the output interface 10 of the embodiment.
According to the above, since the output high impedance state is used as one of the three-valued signals, it corresponds to another signal level in addition to the power supply voltage used for the conventional high-level and low-level signals of binary logic. There is no need to generate an intermediate electric potential. Therefore, compared to a ternary output interface that generates an intermediate potential in addition to the power supply voltage and outputs it as one of the ternary signals, a regulator circuit or the like that generates the intermediate potential is not required, and the circuit scale is reduced. It is possible to reduce the size and power consumption.

Also, the output interface 10 of the embodiment.
Has a configuration in which the ternary conversion circuit 14 is added to the conventional binary logic output interface, and therefore, as an additional configuration, for example, the number of tri-state buffers required for binary logic output are provided. And set the internal signal to 3
It is possible to switch between ternary conversion via the value conversion circuit 14 and sending to the output buffer as it is.
The output of the value logic and the output of the ternary logic can be switched and used.

Further, in the input interface 20, since the input level of the input circuit has only three stages, it is possible to input a high level signal and a low level signal of binary logic while maintaining high noise resistance. is there. Therefore,
Also in the input interface 20, as an additional configuration, the input signal can be switched between binary conversion via the binary conversion circuit 24 or sent to the internal circuit as it is. The three-valued logic input can be switched and used.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the embodiment, it is described that the high-impedance signal on the output side is input as the signal of the intermediate level V2 by connecting the reference potential Vtt of the intermediate level to one end of the terminating resistor Rtm. If a potential higher than the high level Vo3 or a potential lower than the low level Vo1 is connected to one end of the terminating resistor Rtm, a high impedance signal is input as a signal of these potential levels. Also, various modifications can be made to the circuit configuration of the tri-state buffer and the input circuit.

In the above description, the invention made by the present inventor was mainly described for the data transfer on the electronic substrate or in the system LSI which is the field of application which is the background, but the present invention is not limited thereto.
For example, it can be widely used for data transfer in a computer network.

[0024]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, the number of input / output terminals of the device and the bus width can be reduced by the data transfer by the multi-valued signal, and thereby the circuit scale can be reduced and the power consumption can be reduced. Further, according to the output interface of the present invention, since the output high-impedance state is one signal output state, the configuration for generating the potential of the signal level is not necessary, and the circuit scale is reduced and the power consumption is reduced. There is an effect that reduction can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a data transfer system to which the present invention is preferably applied.

FIG. 2 is a data chart showing a relationship between a 2-bit ternary signal and a data value.

FIG. 3 is a circuit diagram showing a detailed configuration example of an input circuit.

FIG. 4 is a diagram illustrating a relationship between reference potentials used in an input circuit.

FIG. 5 is a circuit diagram showing another example of the input circuit.

FIG. 6 is a diagram showing a configuration example of a data transfer system according to the present invention.

[Explanation of symbols]

10 output interface 11a, 11b tri-state buffer 14 three-value conversion circuit 20 input interface 21a, 21b input circuit 24 binary conversion circuit Rtm termination resistor Vtt reference potential

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03K 19/00 101L 101R (72) Inventor Kenni Nishimoto 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Group F-term (reference) 5J042 BA13 BA18 CA18 DA02 DA04 5J056 AA01 AA04 AA11 BB17 BB53 CC00 CC04 CC09 DD00 EE15 FF06 FF07 FF09 GG12 5K029 BB03 CC01 DD04 DD23 FF02 GG07 HH01

Claims (5)

[Claims] 1. An output interface capable of setting each of a plurality of output terminals to any one of a plurality of signal levels or a high impedance state, wherein the output data is a plurality of signal levels and a high impedance state. A semiconductor integrated circuit comprising a multilevel signal that takes any of the above and is configured to be output from the output interface. 2. The semiconductor integrated circuit according to claim 1, wherein the output data does not include a combination in which all of the plurality of output terminals have high impedance. 3. A conversion circuit for converting output data represented by a plurality of binary signals into data represented by a multi-valued signal, wherein the output interface comprises the multi-valued signal based on the output of the conversion circuit. The semiconductor integrated circuit according to claim 1 or 2, wherein the output data is output. 4. The semiconductor integrated circuit according to claim 1, wherein the multi-valued signal is a ternary signal having any one of high level, low level and high impedance. 5. A plurality of signal lines, an output interface capable of outputting a multi-valued signal having any one of a plurality of signal levels or a high impedance to each of the plurality of signal lines, one end of the plurality of signal lines, and A plurality of terminating resistors respectively connected to one potential terminal, and an input interface for receiving a multi-valued signal having any one of the plurality of signal levels and the first potential via the plurality of signal lines. The high-impedance signal output from the output interface is input to the input interface as the signal of the first potential, whereby the data composed of the multilevel signal is transferred from the output interface to the input interface. A data transfer system characterized by being configured as follows.