JPS586569A - Memory device - Google Patents

Abstract

PURPOSE:To select a memory block freely, by splitting a memory board into a plurality of blocks, providing an address designating device, an address comparator and a decoder for each block and arbitrarily setting the address designating device. CONSTITUTION:An address designating device 13 which splits a memory board into a plurality of blocks and can designate arbitrary address information for each block, an address comparator 12 which compares upper-order bits AB15- AB12 transmitted from a CPU with the designated information of the device 13 through inverters 19-19''' for output, and a decoder 14 which interpretes address signals 10 and 11 and selects each of memory element groups X0-X3 in a memory block 11, are provided. A signal controlled with a data readout signal Mr and a switch (SW)1 is inputted to the decoder 14 via an inverter 15 and an AND gate 16. Thus, by the input of arbitrary address information to the device 13 and the control of the SW1 a signal is transmitted from the CPU to the decoder 13 or the transmission is prohibited.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory device, and particularly to a memory device having a plurality of memory elements on one memory substrate.

Conventionally, in a memory device consisting of multiple memory boards,
To select a memory board, a decoder attached to each memory board decodes the upper bits of the address sent from the central processing unit.

Only when an address signal to select itself is received, a decoder signal for selecting a memory board is output to the corresponding memory board, so that the memory board specified by the central processing unit is selected. Ta. However, when a memory board is selected using such a method, all address addresses of the selected memory board are consecutively selected.

Consecutive address addresses used within one memory board could not be used as addresses for another memory board. That is, even if there was an unused address area in the memory board, it was not possible to use it as an address for another memory board. This has the disadvantage that as the memory capacity (number of address addresses) of one memory board increases, the address area that is wasted increases, and a correspondingly larger memory capacity is required.

An object of the present invention is to provide a memory device in which one address address can be shared by a plurality of memories.

The present invention is divided into a plurality of memory blocks on a memory board, and includes an address designator that can set a fixed address for each processor, and an address sent from a central processing unit (CPU) and the address designator. Includes an address comparator that compares output information with a decoder. The address comparator compares the information set by the address designator with the address signal input through the address bus, and when the two match, drives the decoder. state,
The feature is that when there is a mismatch, the decoder is disabled.

According to the present invention, by inputting arbitrary address information into the address designator provided for each group, 9. C.P.
Since the signal sent from U can be sent to the decoder or inhibited, one address can be used for multiple memraps.

Furthermore, since the memory group on the board can be distributed and used in block units, even if the board has a large capacity memory, one address address can be used for each block of memory IPK. Therefore, different data can be written to and read from the same address on one memory board, so the memory board can be used effectively.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the memory device of the present invention.

In this embodiment, the inside of the memory board 1 is divided into three memory blocks 2, 2', and 2', and each block is equipped with an address designator 3, 3' that can set an arbitrary address.
, 3'' and an address comparator 4=4 that compares the information output from this address designator with the address signal input into the memory board l through the address bus AB.
'-4'h Decoders 5, 5', 5' connected to this address comparator and decoding address signals
, and RAM (#) or ROM elements, and includes nine memory element blocks 6, 6', and 6'. The present embodiment shown in FIG. 1 will be explained in detail with reference to FIG. 2.

FIG. 2 shows one of the nine memory blocks shown in FIG. The figure shows an address designator 13 that includes a group of switches and can designate arbitrary address information;
Upper 4 bits of address sent from CPU y)AB
n~AB, , to inverters 19, 19', 19", 19
An address comparator 12 inputs through 1 and compares it with 9 information specified by address specification @13 and outputs a control signal to the decoder 14, and an address signal λB3·, AB,
, and selects each of the memory element groups X·, Xl, X, , X, in the memory block 11. Furthermore, the memory block 11 has a data write signal MY, data buses DB, ~DB, .
Address pins B, ~AB, are connected, and the decoder 14
The signal from the Ka address comparator 12 is inverted and inputted to the inverter 18, which further inverts the inverter 15,
A data read signal Mm is inputted via an AND gate 16. Further, a signal controlled by SW, CH (switch 8W≠L) is input to the input terminal of the AND gate 16 via the inverter 17.

That is, in this embodiment, the address information specified by the address estimator 13 and the address pin (ABl).

~ABi, is compared with the address signal set by ABi, and when both signals match, the signal is
A zero level is input to the decoder 14.

With this output level, the decoder 14 is in an operable state with the sea address bit λB. The signals of the nine people Bn are decoded and one of the memory elements WX.,X,,X,,X, is selected. On the other hand, when the address signals of the address bits and toms λ13n to 13ss do not match the information of the address designator 13, the comparator 12 outputs the "Ql level" and the decoder 14
is prohibited, address AB1. ．． The signal of person Bll is not decoded and memory block 11 is not selected. When the write signal Mw is input, the data bus DB・
~DB, when the original data is written and the switch SW is in the on state.

When the read signal MR reaches the 10a level, the inverter 15 outputs 10 lB to the decoder 14, and this 80@ level makes the decoder 14 ready for operation. The selected signal is decoded and outputted to the memory block 11. The memory element group selected by this selection signal has an address pin)
The data stored in the address designated by AB, ~AB, is output to the data bus DB, ~DB.

As described above, according to the fifth embodiment, the memory board is divided into a plurality of blocks, and each block is provided with an address designator, an address comparator, and a decoder, and the address designator can be set arbitrarily. This allows the decoder to be controlled arbitrarily, thereby allowing the memory block to be freely selected. Therefore, one address signal sent via one address bus AB, ~AB, etc. can be used for multiple memory processors, and the memory as a storage area for programs and data can be used effectively. Can be done.

Further, in the present invention, a switch is used as the HIRO address designator, but the information of the HIRO address designator may be changed arbitrarily by a program and inputted to the comparator, and the switch in the memory board may be freely changed as appropriate. Even if it is divided into two parts, the effects of the present invention can be sufficiently obtained. Furthermore, when one memory processor has a small memory capacity, one decoder may select a plurality of memory blocks.

44. Brief Description of the Drawings FIG. 1 shows a schematic diagram showing an embodiment of the memory device of the present invention, and FIG. 2 shows a circuit diagram showing an embodiment of the memory block shown in FIG. 1. .

Claims (1)

[Claims] The present invention includes means for setting predetermined information, and means for comparing the set information and address information and accessing the memory using the address information when both satisfy a predetermined relationship. Mesori device called IFfIm.