JPS61199293A - Bank switching circuit - Google Patents

Abstract

PURPOSE:To prevent increase of memory space that can not be accessed by increase of the number of banks by inputting a data signal and selecting a memory space at the time of a bank switching mode. CONSTITUTION:When an address signal for bank switching is inputted, the mode goes to a bank switching mode. Supposing that a data signal corresponding to bank Bm is inputted from an inputting buffer 16, the FF 32 is set, and a bank enable signal BEm is retained at high level, and the bank Bm goes to the state of selection. When the set signal Sm of FF 32 goes to high level, resetting is made to FF32 of all other banks B1-Bm-1. Bank enable signals BE1-BEm-1 are retained at low level, and other banks are not selected. When a bank other than the bank Bm is selected, one of input signals S1-Sm-1 of an OR circuit 30 of the bank Bm goes to high level, and accordingly, FF32 of the bank Bm is reset, and the bank Bm is switched to the state of non- selective.

Description

Detailed Description of the Invention (Technical Field) The present invention comprises a plurality of memory spaces each having a capacity that can be selected by an address signal via a row decoder and a column decoder, and one of the memory spaces is selected by a bank switching circuit. The present invention relates to a bank switching circuit in a bank switching type semiconductor memory used.

The bank switching type semiconductor memory is also used as a custom memory such as a split ROM used in, for example, a game machine, or as a RAM or other general semiconductor memory.

(Prior Art) As an example of a bank switching type ROM, as shown in FIG. 3, there is known a type in which bank switching is performed using only address signals. In the same figure, m
M1 to Mm are memories, and each memory M+-Mm is accessed by row decoders Dr+ to Drm and column decoder Dc.

2 is an address buffer to which an n-bit address signal A(n) is input. Each of the memories M1 to Mm has a 2-address memory space that can be accessed by an n-bit address signal A(n), and the memory as a whole has a memory space of m.2. 4 is a bank switching circuit for selecting either memory M+=Mm;
"m banks b+ to bm are provided corresponding to "Mm.Banks b) to bm are composed of address decoders and latches, and bank enable signal B of any bank is provided.
E1 to BEm are at a high level, and when an address signal is input and a predetermined address signal is input, bank enable signal BED-BEm is switched. 6 is an output buffer.

In the bank switching circuit 4 in this ROM.

Using only address signals, banks are switched by associating m independent addresses with m banks b1 to bm. Therefore, among the two memory spaces of each memory M1 to Mm, m spaces corresponding to the number of banks b1 to bm become inaccessible areas. These m memory spaces become wasted areas in which read/write operations, which are normal memory functions, cannot be performed. and,
As the number of banks increases, the amount of inaccessible memory space increases.

(Objective) An object of the present invention is to provide a bank switching circuit in a bank switching type semiconductor memory in which the inaccessible memory space does not increase even if the number of banks increases.

(Configuration) The present invention is a bank switching circuit that performs bank switching operation using both address signals and data signals, and includes an address decoder that inputs an address signal and outputs a bank switching mode signal, and a capacitor that can be accessed by the address signal. is provided corresponding to each memory space, and includes a circuit that inputs a data signal and outputs a bank signal for selecting a memory space when the bank switching mode detected by the address decoder is detected, and a circuit that latches the bank signal. It is composed of a bank.

Hereinafter, one embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 schematically represents a ROM to which an embodiment is applied.
Reference numeral 10 designates a bank switching circuit as an embodiment of the present invention, which, similarly to FIG. Bank enable signals BE+-BEm of a certain bank become high level, one of the memories M1-Mm is selected, and a read/write operation is performed in that memory.

The bank switching circuit 10 receives a bank enable signal BE+.
``In order to switch BEm, both the address signal from the address buffer 2 and the data signal from the I10 buffer 12 are input.

FIG. 2 shows a portion of the bank switching circuit 1'0 in FIG. 1 related to bank Bm.

14 is an address decoder which inputs an address signal, and when the address signal is an address signal corresponding to a bank switching address (an address not used for memory read/write), a high level bank switching mode is set. Outputs signal AE. Only one address decoder 14 is provided for the bank switching circuit 10, and its bank switching mode signal AE is commonly supplied to all banks B+''Bm and also supplied to the I10 buffer 12.

Reference numeral 16 designates an input buffer in the I10 buffer 12 in FIG. 1. One input is a signal obtained by inverting the bank switching mode signal AE from the address decoder 14 by an inverter 18, and the input data signal from the I10 pad 20 is input to the other. It consists of a series circuit of a NOR circuit 22 and an inverter 24, which serve as inputs. This manual buffer 16 is provided for the word length of the data signal. This human buffer 1
Only one 6 is provided for the bank switching circuit 10,
The output data signal is commonly supplied to all banks 81-Bm.

Bank Bm includes a data decoder 26 that inputs the data signal from input buffer 16 and outputs bank signal DEm, and a gated RS flip-flop 32 that has an AND circuit 28 on the set input side and an OR circuit 30 on the reset input side. It consists of. The AND circuit 28 uses the bank switching mode signal AE of the address decoder 14 as one input signal, uses the bank signal DEm of the data decoder 26 as the other input signal, and outputs the output signal Sm from the flip-flop 3.
2 set signal, and the other banks 81 to B
This becomes a reset signal for the m-+ flip-flop. OR
The circuit 30 receives the output signal St -8m-+ of the AND circuits 28 of all the other banks Bl to Bm-l, and its output signal Rm serves as a reset signal for the flip-flop 32. The output signal BEm of the flip-flop 32 is the bank enable signal BEm.

Next, the operation of the bank switching circuit of this embodiment will be explained.

When an address signal for a bank switching address (an address not used for memory read/write) is input from the address line, the normal read/write sequence is deselected, the output buffer becomes floating in the I10 buffer 12, and the bank is switched. mode. At this time, in the address decoder 14, its output signal, the bank switching mode signal AE, becomes high level, and I1
An external data signal is input from the I10 pad 20 to the 0 buffer input cover sofa 16.

The m banks 81 to Bm are made to correspond to independent data signals, respectively. If a data signal corresponding to bank Bm is now input from the input buffer 16,
Bank signal DEm, which is the output signal of data decoder 26 of bank Bm, becomes high level, and set signal Sm of flip-flop 32 of bank Bm becomes high level. As a result, the flip-flop 32 is set, and its output signal, the bank enable signal BEm, is held at a high level, so that the bank Bm is selected. Moreover, when the set signal Sm of the flip-flop 32 of this bank Bm becomes high level, the flip-flops 32 of all other banks 81 to Bm-+ are reset by the signal Sm, so that all the other banks 81 ~Bm-+ bank enable signals BE1~BEm
-+ is held at low level, and other banks are not selected.

Next, if a bank other than bank Bm is selected,
One of the bank signals DE+=DEm-+ becomes high level, one of the set signals S I''S m-t becomes high level, and the flip-flop 32 of the selected bank is set. Therefore, one of the input signals S! to Sm-1 of the OR circuit 3o of the bank Bm becomes high level, so the flip-flop 32 of the bank Bm is reset and held at the low level.In other words, the bank Bm Switched to unselected state.

(Effects) Conventional bank switching circuits perform bank switching operations using only address signals, which requires as many independent addresses as there are banks, making it impossible to read and write as many memory areas as there are banks. It had become. and,
There was a drawback that as the number of banks increased, the amount of wasted memory area also increased.

In this invention, the address used for bank switching is only one address for setting the bank switching mode, and bank selection is performed by a data signal. Therefore, even if the number of banks increases, only one memory area is always wasted, and there is an advantage that the memory area can be used effectively.

[Brief explanation of drawings]

Figure 1 shows a ROM using a bank switching circuit according to one embodiment.
FIG. 2 is a circuit diagram showing part of a bank switching circuit of one embodiment, and FIG. 3 is a schematic block diagram showing a ROM using a conventional bank switching circuit. M+ -Mm・・・Memory, Dr”Drm・
...Row decoder, Dc...Column decoder, B+=Bm...Bank, 10...
...Bank switching circuit, 12...I10/
<FF, 14...address decoder,
26...Data decoder, 28...
...AND circuit, 30...OR circuit, 32
...RS flip-flop.

Claims (1)

[Claims] (1) In a bank switching circuit that selects a memory space in a semiconductor memory that has a plurality of memory spaces with capacities that can be selected by an address signal via a row decoder and a column decoder, an address signal is input and a bank switching mode signal is output. an address decoder provided corresponding to each of the memory spaces, a circuit that inputs a data signal and outputs a bank signal for selecting a memory space when in a bank switching mode detected by the address decoder, and a circuit that latches the bank signal. A bank switching circuit comprising: a bank including a circuit for switching.