JPS5863231A - Initial clearing circuit - Google Patents

Abstract

PURPOSE:To ensure initial clearing regardless of the rise time of a power supply, by releasing the clear signal with a delay of a certain period after the power supply voltage reaches the prescribed level. CONSTITUTION:A constant voltage diode D41 is not conductive and transistors TRQ41 and TRQ42 are turned off and on respectively at a moment when the power supply voltage VCC is applied. Thus an input VIN of a Schmitt trigger inverter 1 has no rise, and an output inverter 2 delivers a clear signal. When the voltage VCC exceeds the Zener voltage of the diode D41, the TRQ41 and TRQ42 are turned on and off, respectively. Then a delaying circuit consisting of a resistance R44 and a capacitor C41 starts its operation. Thus the voltage VIN of the inverter 1 starts rising. The output of the inverter 1 releases the clear signal delivered from an output inverter 2 after a certain period that is decided by the time constant of the delaying circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an initial clear circuit. Digital electronic equipment generally requires an initial clear circuit that clears the registers, flip-flops, etc. in each building to their initial state when the power is turned on.

The conventional initial clear circuit is an integrated circuit as shown in Figure 5g1.
) and an output inverter (2), and a delay circuit including a resistor (R, ) and a capacitor (C1) is provided at the input (vIN) of the Schmitt trigger inverter (1). Fig. 2 is a time chart showing the operation of this circuit, where the input (VI, ) is applied after the power supply voltage c (vcc) rises, depending on the time constant of the resistor (Ru) and capacitor (C,). The threshold voltage (VTR) is reached after a certain time delay, and from Tt2 to Tt2, the output inverter (2)
The CXrHkR output of is kept at LOW level. Therefore, with the time constant of the resistor RIL and the capacitor C11, the intoxication signal becomes LOW level and the registers and flip-flops are kept in a clear state until the original Vac rises completely. However, since the power supply VCC has a soft start function and requires a short startup time of several tens to hundreds of ms, it does not have a sufficiently fast startup time as shown in FIG. FIG. 3 shows an example where the rise of the power supply voltage (Mac) is slow.

In this example, the human power (VIN) of the Schmitt trigger inverter (1) raises the voltage shield (Vrg) before the voltage (EECVcc) reaches the minimum operating voltage (MhouuN) of the circuit. If this is exceeded, the circuit that allows ktj1 clear to enter normally will not operate stably. Also (V
D(!MIN) is the lowest voltage at which the inverter (1) operates logically, and although the delay time standard of integrated circuit elements is not guaranteed, the logical DC level of input and output operates. The voltage is lower than “Co MIX”, generally 2
It is about ~3v. Therefore, when the power supply voltage (Vco) is lower than VDOMXM, the level of the clear signal is not determined. To solve the problem that the shuffler signal - does not enter normally due to the slow rise time of the power supply voltage, increase the resistance (RIL) and capacitor (C,) so that the input (vIN) is connected to the inverter (1). ) One way to solve this problem is to make the time it takes to reach the threshold voltage of the element even longer than the rise time of the power supply voltage (Vcc), but no matter how large the resistor (R1) is, the input low voltage of the element There is no effect on the level current m (E L), so the only option is to increase the capacitance of the capacitor (am).

However, a large capacity capacitor has a large shape and is difficult to mount on a substrate.

The present invention has been made in view of the above points, and is designed to release the clear signal not at the time the power is turned on, but after the power supply voltage reaches a predetermined value, with a certain period of delay. An object of the present invention is to provide an initial clear circuit that can perform a reliable initial clear regardless of the short time it takes for a power supply to start up. The present invention will be described in detail below based on the drawings.

Figure R4 is a circuit diagram showing one embodiment of the present invention, (1) is a Schmitt trigger inverter, (2) is an output inverter,
(R44) and (C, □) are resistors and capacitors constituting a delay circuit, which are the same as those in the conventional circuit shown in FIG. In addition, Schmidt Drika Inverter (
As 1), this embodiment uses a TTL integrated circuit 7414 manufactured by Texas Instruments Inc., and a 74O4 as an inverter (2).

(I), ) are constant voltage diodes, (C41) and (C4
9) are respectively T2V star) and power supply voltage (Vaa)
When the diode (n4t) is turned on, the diode (n4t) is non-conductive, so the transistor (C41) is "O?IF", the transistor (C4) is in the "OM" shape, and the inverter (
1) is configured to stop the input (vIN) from increasing.

When the power supply voltage (Vac) exceeds the sum of the Zener voltage of the constant voltage diode (D4□) and the pace-emitter drop voltage of the transistor (C41), the transistor (C4
1) Is the transistor (C49) 'ON'?'
Then, the delay circuit consisting of a resistor (it44) and a capacitor (C41) starts working and the input ('V
IN) starts to rise. Therefore, by appropriately selecting the Zener voltage of the constant voltage diode (n4t), the transistor (C41) should be turned on when the power supply voltage (Tea) reaches the minimum operating voltage (VCICMIN). , the input voltage (Vcc MIN ) of the inverter (1) exceeds its threshold voltage (VTR) after a certain period of time according to the time constant determined by C41 and R44, and the inverter (2 )
clear signal is released. This constant voltage diode (n
The Zener voltage of 4t) is desirably set to 4.0V in consideration of the fact that the voltage drop between the transistor (C41) and the emitter is about 0.75V.

Figures 4 and 5 show the operation timing of this circuit when the power supply voltage (VcC) rises. As described above, (VDC! MIN) is the lowest voltage value at which the DC logic level of the inverter (1) operates, and is approximately 2 to 3V. Power supply voltage (vc
cM” minimum operating voltage (voo MIN = 4.75'
The transistor (C41) is “0IPF” until it reaches V).
'', the transistor (Q-) is ON', and as mentioned above, the rise in 'Ri' of the input (MIN) of the inverter (1) is stopped.

Therefore, during this period, the -6E*"i,'n outputs of the inverter (2) are ideally in the 'Lov' state, but the voltage (Tea) of the Schmitt trigger inverter (1) is VDOMll.
(The Ih output is actually uncertain between 'l'st and T-, since the logic level is not determined until it reaches the above level. However, between T0n and T114, the Ih output is at the I+OW level. During this time, the circuit power supply has a sufficient operating voltage E!l, so registers, flip-flops, etc. can be cleared.

When the power supply voltage (Vcc) rises and becomes 4 or more than QCMIN, the transistor (C41) turns on, and the transistor V
The star (C4s) is “0ff7”, the resistor (R4-)
The current is charged to the capacitor (C41), and the input (
The voltage of V (M) begins to rise. When the input (V) exceeds the threshold snow pressure (vTir) of the inverter (1), the CLffA R output changes from bow to Hlgh.
), clearing is canceled.

In this embodiment, as described above, between KT61 and T0, ■1
1 output is uncertain, and this is sufficient for general digital equipment, but generally digital ICs have a minimum guaranteed operating voltage of 4.757, and when the voltage exceeds 1.5'V to 3.0V, Since this will result in an unstable output, if it is required that the clear signal be reliably LOW even at this low voltage, a circuit shown in the configuration shown in FIG. 6 may be used. In FIG. 6, the same parts as in FIG. 4 are given the same numbers.

In this embodiment, a transistor (Q
41) and add two resistors (R,,), (R,,),
The collector of the transistor (Q411) and the output of the output inverter (3) b are connected to form a wire FOR.

Therefore, an open collector (for example, 817405) is used as the output inverter (3). Also, resistance (R
47) is a pull-up resistor.

FIG. 7 shows the operation timing of Jin's circuit when the power is turned on.

The power supply voltage (vcc) is connected to transistors (Q41) and (Q
41) Pace Emitsuku drop Senou (0,75M
> or more, this transistor (Q41) and (Q
411) becomes “ON”, and in/<-1(1) (D
At the same time as stopping the voltage rise of the input (vIN), the CLICAR output of the output inverter (3) is transferred to the transistor p (Q
41) Keep Kyop at zow level, at this time inverter (1) and output inverter (3) have not yet reached the operating state. 1! Source t! E (Vcc) is the minimum operation pressure (
Vcc MrN), the diode (D, 1) becomes conductive and the transistor (Q41) becomes 1ON'''.
Transistors (Q4) and (Q4m) are @oyz: "7. At this time, inverter (1) and output inverter (3)
has reached the operating state, so even if the transistor (Q41) becomes "oyy", the output of the Yanagawa inverter (3) whose input (Vr) is LOW is bow, and ? 5
'T;'RTPi: Output Id Remains LOW.

The power supply voltage (Tca) is the minimum operating voltage (Vc (!
), the capacitor (C4t) is charged and the input (VzN) voltage rises, and when it exceeds the threshold voltage (VTa) of the inverter (1), CLEAR
The output becomes 11gh'' and the clear signal is released at this point. In this embodiment, as shown in FIG. 7, while the ξ1j output is uncertain, the power supply voltage (V
cc) reaches 0.75v (Tts).

If the power supply voltage (vcc) is 0.75V or less, it is the voltage before the integrated circuit element to be cleared operates, and W is sufficiently low.
Since it is an EE value, no problem will occur.

Note that in the circuits shown in FIGS. 4 and 6 described above, the minimum operation tFFf and the charging start voltage to the capacitor (C4t) are equal for simplicity, but in reality there are variations in the constant voltage diode. . If the maximum charge start voltage is set to 4-75V or less, the minimum value is 4. Even if charging starts from this minimum value, the 0LIAR output remains low until the Il power supply voltage (Vac) reaches 4.75'V or more.
It is desirable to make the time constants of the resistor (R46) and capacitor (041) large so that .

As explained above, in the circuit according to the present invention.

Since the clear signal is released with a one-hour delay after the power supply voltage reaches a predetermined value, rather than when the power is turned on, reliable rear operation can be achieved regardless of the time of lightning or power source rising.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional circuit, Figures 2 and 3 are timing charts showing its operation, Figure 4 is a circuit diagram showing an embodiment of the present invention, and Figure 5 is a diagram showing its operation. 6 is a circuit diagram showing another embodiment of the present invention, and FIG. 7 is a timing chart showing its operation. In FIG. 0, (1) is a unit trigger inverter, (2) and (3) are output inverters, (D4□) are constant voltage diodes, (Q4□), (Q42) and (Q41
1) is the transistor, (R,,) is the resistance% (041
) is a capacitor. Applicant's agent Kiyoshi Inomata Figure 1 4 Figure 2 ll Tl 2 Figure 3 porridge 111 1 1 1 ``31 '' 32 ``33 '' 34 Figure 4 cc '4P15 ゛+51 '52'53 T54 Oval 6 Figure 7 Jishu, Saku 3 T74

Claims (1)

[Claims] For electronic devices that require initial clearing when the power is turned on, the
*When it is detected that the power supply voltage has reached a predetermined voltage or higher,
The initial clear circuit is characterized in that the clear signal is released after a certain period of time has elapsed from the point of detection.