JPS5860545A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5860545A
JPS5860545A JP16064381A JP16064381A JPS5860545A JP S5860545 A JPS5860545 A JP S5860545A JP 16064381 A JP16064381 A JP 16064381A JP 16064381 A JP16064381 A JP 16064381A JP S5860545 A JPS5860545 A JP S5860545A
Authority
JP
Japan
Prior art keywords
resin
chip
wafer
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16064381A
Other languages
Japanese (ja)
Inventor
Shuichi Osaka
大坂 修一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16064381A priority Critical patent/JPS5860545A/en
Publication of JPS5860545A publication Critical patent/JPS5860545A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To improve the memory retention characteristic by forming a laminated body of resin both by coating and dropping methods and thereby increasing the thickness of a film and the uniformity thereof. CONSTITUTION:A wafer 1 is coated with resin 3, and the wafer whereon the resin 3 is left only in a prescribed part by photoengraving is cut in a prescribed size, whereby a chip 7 is formed. Next, the chip 7 is fixed at a prescribed position 8 in a semiconductor vessel 5, wire bonding with an Al wire 9 is conducted thereafter, liquid resin 10 is dropped thereon and cured by heating, and then sealing is made by a cover 11.

Description

【発明の詳細な説明】 この発明は半導体装置の製造方法、特に大容量半導体記
憶素子の記憶保持特性を改善した半導体装置の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with improved memory retention characteristics of a large-capacity semiconductor memory element.

上記大容量記憶素子における記憶保持を不安定にさせる
原因としては、一般的には半導体素子を収納する半導体
用の容器中に微量に含まれている、クラン、トリウム等
の放射性5元素の直崩壊の際に発生するα粒子が、半導
体素子中に浸入し、α粒子の持つエネルギーによ゛り半
導体素子中に′Ic離現象が発生し、電離により発生し
た多量の電子が一1時的に記憶動”作を混私させるもの
である。
The cause of unstable memory retention in the above-mentioned large-capacity storage elements is the direct decay of five radioactive elements, such as clan and thorium, which are generally contained in trace amounts in semiconductor containers that house semiconductor elements. The α particles generated during this process penetrate into the semiconductor device, and due to the energy possessed by the α particles, an 'Ic dissociation phenomenon occurs in the semiconductor device, and a large number of electrons generated by ionization temporarily dissipate. It confuses memory and action.

現在、このように半導体素子に侵入するα粒子を遮蔽す
る方法としては高純度に精製゛した樹脂を半導体素子の
表面にコーティングする方法が多く用いられている。第
1図及び第2図を参照して現在多く用いられているコー
ティング方法とその欠点を述べる。
Currently, a method of coating the surface of a semiconductor element with a highly purified resin is often used as a method for shielding alpha particles from entering a semiconductor element. With reference to FIGS. 1 and 2, coating methods that are currently widely used and their drawbacks will be described.

第1図にクエハー状態でクエハーの所定部分に樹脂を塗
布する方法を示す。先ずオ1図囚に示すようにクエハー
(1)をスピナー(2)上に固定し樹脂(3)をクエハ
ー(1)の表面に均一に塗布する。
FIG. 1 shows a method of applying resin to a predetermined portion of a quefer in a quefer state. First, as shown in Figure O1, the quefer (1) is fixed on a spinner (2), and the resin (3) is uniformly applied to the surface of the quefer (1).

第1図fBl li均一に車重された樹脂(3)とクエ
ハー11)を示す。次に第1図fclに示すように写真
製版の技術でクエハーCI+の所定部のみに樹脂13)
を残す◇このように形成したクエハーを所定寸法に切断
後、半導体容器内に実装する方法である。
Figure 1 f shows resin (3) and quahar 11) with uniform vehicle weight. Next, as shown in FIG.
◇This is a method in which the thus formed wafer is cut into predetermined dimensions and then mounted inside a semiconductor container.

この場合、樹脂の粘度、および各ビナ−の回転数により
樹脂の膜厚をコントロールできるが、写真製°版による
限度および膜厚コントロールの限度からto−go =
クロン程度の膜厚のものしか再現性良く製造することが
できず、数10ミクロン以上の膜厚を得ること1は困難
となる欠点がある。
In this case, the resin film thickness can be controlled by the viscosity of the resin and the rotation speed of each biner, but due to the limitations of photolithography and the limits of film thickness control, to-go =
It has the drawback that it can only be manufactured with a film thickness of about 10 microns with good reproducibility, and it is difficult to obtain a film thickness of several tens of microns or more.

第8図に、クエハーを切断してチップ(4)にした後に
所定半導体容器(5)に固定後、所定ワイヤボンディン
グを完了し、その鎌、滴状樹脂(6)を滴下する方法を
示す。この方法の場合′、滴下後加熱硬化した後で滴下
中心部と周辺部とで膜厚の差が大きい欠点がある。また
(両所の種類によっては液状樹脂の広がりが悪く、滴下
後に機械的に樹脂を広げたり圧縮空気を吹きつけて樹脂
を広げる等の余分な工数を必要とする欠点がある。
FIG. 8 shows a method of cutting the wafer into chips (4), fixing them in a predetermined semiconductor container (5), completing predetermined wire bonding, and dropping the sickle and drop-shaped resin (6). This method has the disadvantage that there is a large difference in film thickness between the center of the drop and the periphery after the drop is heated and cured. In addition, depending on the type of liquid resin, the liquid resin does not spread well, and there is a drawback that extra man-hours are required, such as mechanically spreading the resin after dropping or blowing compressed air to spread the resin.

本発明は上記方法の欠点を政情するためになされたもの
である。第8図にその実施例を示し説明する。まず第1
図と同様な方法によりり工ハーfil K樹脂(3)を
塗布し、写真製版を用いて所定部分のみに樹脂(3)を
残したクエハーを所定寸法に切断してチップ(7)を形
成する。盗にこのチップ(7)を半導体容器(5)の所
定位置(81に固定する。
The present invention has been made to address the drawbacks of the above methods. An embodiment thereof is shown and explained in FIG. 8. First of all
Coat the wafer fil K resin (3) in the same manner as shown in the figure, and use photolithography to cut the wafer into a predetermined size, leaving the resin (3) only in the predetermined portions, to form a chip (7). . This chip (7) is securely fixed at a predetermined position (81) in the semiconductor container (5).

その後、Al線(9)によるワイヤボンディングを行っ
た後に、液状の樹脂(lαを滴下し、加熱硬化したもの
を蓋(11)で封止しているものである。
After that, wire bonding is performed using an Al wire (9), and then a liquid resin (lα) is dropped, and the resin is cured by heating and sealed with a lid (11).

以上のように、この発明は塗布法と滴下法とを併用して
樹脂積層体を形成するようにし九ので、樹脂層全体とし
て数105クロン以上の膜厚が容易に得られる他、樹脂
層の分布のバラツキが小さくなるとともに樹脂層の最も
薄い層の限度が明確となる。又、硬化した樹脂上に滴状
樹脂を滴下することで樹脂の広がりが良くなりかつ膜厚
の均一性を向上することができる。
As described above, since the present invention uses both the coating method and the dropping method to form a resin laminate, it is possible to easily obtain a film thickness of several 105 chrome or more for the entire resin layer. As the variation in distribution becomes smaller, the limit of the thinnest resin layer becomes clear. Further, by dropping droplet-shaped resin onto the cured resin, the spread of the resin can be improved and the uniformity of the film thickness can be improved.

また膜厚の増大と均一性向上によって、半導体記憶素子
の記憶保持特性を大中に改善することができる。
Furthermore, by increasing the film thickness and improving uniformity, the memory retention characteristics of the semiconductor memory element can be significantly improved.

尚、クエハー表面上に選択的に形成する樹脂層成分とそ
の後さらに滴下する液状樹脂の成分は必ずしも同一のも
のでなくてよい。
Note that the components of the resin layer selectively formed on the surface of the quefer and the components of the liquid resin further dropped thereafter do not necessarily have to be the same.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第8図は従来例を示す断面図、第8図は本
発明の一実施例1を示す断面図である。 illクエハー、+21スピナー、131樹脂、(4)
チップ、(6)半導体容器、(61液状樹脂、(7)チ
ップ、(111容器の所定位置、AI細線、Ua液液状
樹脂、(■)封止蓋O 代理人  葛 野  信 − 第1図 rr: Q図
1 and 8 are sectional views showing a conventional example, and FIG. 8 is a sectional view showing a first embodiment of the present invention. ill Quahar, +21 spinner, 131 resin, (4)
Chip, (6) Semiconductor container, (61 Liquid resin, (7) Chip, (111 Predetermined position of container, AI thin wire, Ua liquid liquid resin, (■) Sealing lid O Agent Shin Kuzuno - Figure 1 rr : Q diagram

Claims (1)

【特許請求の範囲】[Claims] 半導体記憶素子が形成されたクエハの表面にα線を遮蔽
する樹脂を塗布する工程、上記樹脂が塗布されたクエハ
を所定形状に切断してチップを形成する工程、上記チッ
プを半導体容器に固定してワイヤボンディングを行う工
程、然る後、上記樹脂の上にα線を遮蔽する液状樹脂を
滴下して樹脂積層体を形成する工程を含む半導体装置の
製造方法。
A step of applying a resin that shields alpha rays to the surface of the wafer on which a semiconductor memory element is formed, a step of cutting the wafer coated with the resin into a predetermined shape to form a chip, and a step of fixing the chip to a semiconductor container. A method for manufacturing a semiconductor device, the method comprising the steps of: performing wire bonding, and then dropping a liquid resin that blocks alpha rays onto the resin to form a resin laminate.
JP16064381A 1981-10-06 1981-10-06 Preparation of semiconductor device Pending JPS5860545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16064381A JPS5860545A (en) 1981-10-06 1981-10-06 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16064381A JPS5860545A (en) 1981-10-06 1981-10-06 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5860545A true JPS5860545A (en) 1983-04-11

Family

ID=15719364

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16064381A Pending JPS5860545A (en) 1981-10-06 1981-10-06 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5860545A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5891662A (en) * 1981-11-27 1983-05-31 Nec Corp Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5891662A (en) * 1981-11-27 1983-05-31 Nec Corp Semiconductor device and manufacture thereof
JPS6211508B2 (en) * 1981-11-27 1987-03-12 Nippon Electric Co

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